**** BEGIN LOGGING AT Sat Jul 20 02:59:58 2013 Jul 20 14:24:09 gm Jul 20 14:24:20 anybody following the iio list? Jul 20 14:24:28 Russ: koen ping.. Jul 20 14:32:48 anyone? Jul 20 15:10:33 happy saturday! Jul 20 16:55:03 yes? Jul 20 16:59:37 Jonathan wants all bug fixes to adc driver squashed into one big patch.. Jul 20 16:59:55 ok by you? Jul 20 17:00:25 for the continuous mode.. Jul 20 17:00:40 http://thread.gmane.org/gmane.linux.kernel/1527809 Jul 20 21:00:25 Russ: ping.. Jul 20 21:09:27 have a hunch driver wont get upstreamed without a proper iio trigger.. Jul 20 21:10:00 and adding an iio trigger seems like reworking the entire driver. doesn't seem like something to patch later on. Jul 20 21:10:26 especially considering jonathan has stated that submit one patch for the continuous mode.. Jul 20 21:24:18 jj2baile, ping? Jul 20 21:24:28 ka6sox, ping? Jul 20 22:28:08 mluckham, pong Jul 20 22:28:19 hi tom Jul 20 22:28:51 howdy mike, how goes it today? Jul 20 22:29:10 i made some progress getting jj2baile pru Boundary running, I can see something on my logic analyzer Jul 20 22:29:19 excellent Jul 20 22:29:26 not with panto's kernel though Jul 20 22:29:37 did you see that the openjtag guys are using an FPGA? Jul 20 22:29:59 is that new? i thought it was a cpld Jul 20 22:30:10 oh maybe it is cpld Jul 20 22:30:12 my error Jul 20 22:30:35 they both look like little black thingies to me Jul 20 22:30:57 they are GLUE in this case Jul 20 22:31:07 think of them as nothing more than logic blocks Jul 20 22:31:11 yes Jul 20 22:31:25 the PRU is doing the heavy lifting Jul 20 22:31:58 i am used to using Digiview DV3100 USB logic analyzer, it was nice + reliable Jul 20 22:32:18 this probably will be too..but I hope for less $$$ Jul 20 22:32:29 the Open Bench Logic Sniffer is not as consistent - but yes, $50 vs $400 Jul 20 22:33:08 I'm thinking more like $100 vs $400 when you factor in the board Jul 20 22:33:18 that will be good Jul 20 22:33:37 but the software presentation will make it or break it? Jul 20 22:33:50 doesn't it always? Jul 20 22:33:57 except panto, he hates GUI ;) Jul 20 22:34:10 or rather, loves CLI Jul 20 22:34:30 I am hoping this can be used with IDEs and stuff Jul 20 22:34:36 me too Jul 20 22:34:37 and be a ethernetable things Jul 20 22:34:47 for things like gdb-server Jul 20 22:35:01 jj2baile's Boundary demo does the boundary scan all in the PRU, right? Jul 20 22:35:07 yes Jul 20 22:35:13 its all PRU, all the time... Jul 20 22:36:03 it looks like the sequence is: Test Logic Reset, Run Test Idle, Select DR scan, Select IR scan, repeat - does that sound right? Jul 20 22:36:19 that's what the LogicSniffer Logic Analyzer Client JTAG analyzer tells me Jul 20 22:36:27 :) Jul 20 22:36:34 looks good! Jul 20 22:36:42 passes the smell test, at least Jul 20 22:37:20 I guess I could wire it to something (Stellaris Launchpad)? Jul 20 22:37:45 I make it that P9.27 is TDO, P9.25 TDI, P8.12 TCK, P8.11 TMS - does that sound right? Jul 20 22:38:31 admittedly I didn't look that far...been focused on the board. Jul 20 22:38:40 i'll ask jj2baile about this Jul 20 22:39:02 I did verify it assembled and I could get it to go into the PRUs Jul 20 22:39:15 that is on my tomorrow agenda... Jul 20 22:40:17 i'm still confused which uEnv.txt file to update - I found three of them and updated them all, to get it to work ~ Jul 20 22:40:23 you have a 4F120 board? Jul 20 22:40:28 I think it's always the one on the eMMC Jul 20 22:40:58 yes, the Stellaris Launchpad 4F120 Jul 20 22:40:58 when we start using the parallel we will need 4GB uSDs Jul 20 22:41:08 same one we have...excellent Jul 20 22:41:30 and you logic analyser (if you don't mind) will be helpful for debugging things as well :) Jul 20 22:41:50 to wire up the BBB to it's jtag header, I need to disable the front-end debug part (I forget what it is called) Jul 20 22:42:23 CPD? Jul 20 22:42:35 it's another 4f120 part ... Jul 20 22:43:34 my SD cards are 8GB and larger Jul 20 22:44:06 perfect Jul 20 22:44:19 ICDI Jul 20 22:44:23 that's it Jul 20 22:44:27 in-circuit-debug-interface Jul 20 22:44:42 we want it out-of-circuit ;) Jul 20 22:44:57 right, there is a way to disable that by pulling down on a pin Jul 20 22:45:05 icdi_rst. Jul 20 22:45:11 it goes to a couple of diodes Jul 20 22:45:22 yes - but if you want logic analyzer captures I can do that with the icdi active Jul 20 22:46:04 in this case what I'm after is making the BBB do the work and having the LA capture the exchanges. Jul 20 22:46:27 right Jul 20 22:46:44 we can start with the CPLD outputting 5mhz so the exchanges are slow and predictable Jul 20 22:46:47 i'll try to post a screenshot of what I see now Jul 20 22:46:52 thanks Jul 20 22:47:05 jj2baile, ping? Jul 20 23:02:27 mluckham: Code that is up doesnt do boundary scan, just fetches the idcode Jul 20 23:02:57 ok Jul 20 23:02:58 I should push the code that samples the pin states Jul 20 23:03:17 i was thinking of abstracting more before i did so, but i could just push it now Jul 20 23:05:03 i want to get panto's vring stuff working next, now that I can load pru stuff Jul 20 23:05:53 i notice his kernel is bone_capemgr.8, latest Angstrom is capemgr.9 - does that matter? Jul 20 23:09:59 can you see this screen capture? https://www.dropbox.com/s/wx91ijgiz8dh1sb/prucap1.jpg Jul 20 23:12:11 yes, we can see it Jul 20 23:12:17 hiya jj2baile Jul 20 23:15:28 Good morning, seems i slept for a rather long time Jul 20 23:15:39 understood..happens. Jul 20 23:17:33 did you see mluckham's captures about what you are sending? Jul 20 23:20:32 yes Jul 20 23:20:50 the logic analyzer seems quite handy Jul 20 23:22:21 that was at 1 MHz sampling rate, it can go up to 200 mhz Jul 20 23:22:38 but triggering is needed to catch the signals of interest Jul 20 23:25:22 i forgot, i am -away ... Jul 20 23:30:20 you disable ICDI supposedly by pull EXT DBG to low, however that didnt really change anything as far as the results of the test scan **** ENDING LOGGING AT Sun Jul 21 02:59:58 2013