**** BEGIN LOGGING AT Tue Aug 13 03:00:00 2013
Aug 13 18:43:00 <panto> gregkh, ping if you're around
Aug 13 18:51:57 <mluckham> ka6sox, ping
Aug 13 18:55:55 <ka6sox> mluckham, pong
Aug 13 18:56:06 <gregkh> panto: pong
Aug 13 18:56:22 <mluckham> hi Tom, did you see my discussion with panto yesterday?
Aug 13 18:56:31 <panto> gregkh, bugs, bugs everywhere
Aug 13 18:57:32 <panto> note that it doesn't crash immediately on removal because my crash fix patchset is applied
Aug 13 18:57:55 <ka6sox> mluckham, just read that.
Aug 13 18:58:48 <mluckham> ok - so I have some C++ code that operates P8 pins using gpio - will use that to implement a bitbang interface for OpenOCD as stage 1
Aug 13 18:59:10 <mluckham> I'm setting up a github repo - my first time so probably won't be ready for a few days
Aug 13 18:59:35 <mluckham> next is to shift the bitbang interface to PRU - using downcalls and sysfs nodes
Aug 13 19:00:10 <mluckham> these will give the necessary experience with OpenOCD and JTAG that I need
Aug 13 19:00:56 <mluckham> how is the cape coming along?
Aug 13 19:02:02 <mluckham> was there some reason to separate input pins and output pins, to different PRUs?
Aug 13 19:06:56 <panto> gregkh, sent - but don't apply yet; still waiting for input by the maintainers
Aug 13 19:07:02 <gregkh> panto: ok.
Aug 13 19:10:16 <ka6sox> mluckham, talked a bit with panto, we can use downcalls for most if not all...I just want some low speed control/status with sysfs stuff.
Aug 13 19:12:15 <panto> I bid thee good night
Aug 13 19:12:19 <panto> bbt
Aug 13 19:14:22 <ka6sox> nite panto
Aug 13 19:14:41 <ka6sox> mluckham, the PRUs have GPI *or* GPO
Aug 13 19:14:43 <ka6sox> not GPIO
Aug 13 19:15:32 <mluckham> ok
Aug 13 19:16:11 <mluckham> a bit awkward though?
Aug 13 19:16:15 <ka6sox> not really
Aug 13 19:16:28 <ka6sox> the FDX process we are using can be nicely split up
Aug 13 19:16:50 <mluckham> when clocking a bit out, have to clock one in as well - needs some kind of pru-pru coordination?
Aug 13 19:17:01 <ka6sox> just a wire
Aug 13 19:17:10 <ka6sox> clock line
Aug 13 19:17:28 <mluckham> feedback signal wire?
Aug 13 19:18:02 <ka6sox> no, just common clock
Aug 13 19:18:14 <ka6sox> actually I'm wrong
Aug 13 19:18:52 <ka6sox> the CPLD is a FIFO and the CPLD controls when things need to happen with the PRU to either feed or remove data from the FIFOs
Aug 13 19:19:21 <mluckham> CPLD will listen to 'one pru' and talk to 'other pru' ?
Aug 13 19:19:40 <mluckham> transferring the TCLK signal as needed?
Aug 13 19:20:14 <ka6sox> yes
Aug 13 19:20:21 <mluckham> that works
Aug 13 19:20:24 <ka6sox> the PRU will set the clock rates
Aug 13 19:20:38 <ka6sox> and the divider on the CPLD will handle the TCK lines
Aug 13 19:20:51 <ka6sox> the PRU will engage TMS as needed
Aug 13 19:21:29 <ka6sox> TDI/TDO are abstracted thru the FIFO<>PISO/SIPO interfaces
Aug 13 19:21:59 <mluckham> do you have a writeup for this?
Aug 13 19:22:13 <ka6sox> I've got a block diagramme...
Aug 13 19:22:25 <ka6sox> we need a common repo to put things into however
Aug 13 19:23:41 <mluckham> want to use mine?  but, you already have one (cape schematics)
Aug 13 19:23:55 <ka6sox> yes, let me go ahead and get it up there.
Aug 13 19:24:01 <mluckham> good
Aug 13 19:24:43 <mluckham> i have to do some work outside, back in a couple of hours
Aug 13 19:28:08 <ka6sox> I also need to do some work as well.
**** ENDING LOGGING AT Wed Aug 14 02:59:59 2013