**** BEGIN LOGGING AT Sun Jun 12 02:59:58 2016
Jun 12 05:49:53 <ZeekHuge> Wormo: ..
Jun 12 05:50:07 <ZeekHuge> I just added a few functions to my module
Jun 12 05:50:29 <ZeekHuge> and now its not loading saying that the versioning number is not there.
Jun 12 05:50:40 <ZeekHuge> It was loading earlier.
Jun 12 05:50:56 <ZeekHuge> I am building it on the BBB itself
Jun 12 05:52:20 <ZeekHuge> and there is no way I can build a complete kernel there.
Jun 12 05:52:32 <ZeekHuge> and then it was working earlier
Jun 12 05:52:58 <ZeekHuge> I am almost done with the module, I just need to test it now, but its not loading. :(
Jun 12 05:53:24 <ZeekHuge> Abhishek_: ^
Jun 12 05:53:31 <ZeekHuge> m_w: ^
Jun 12 10:27:38 <chanakya_vc> hey karki_ and Abhishek_ I have a fundamental doubt with regarding to SPI.Can you help me out?
Jun 12 10:28:49 <chanakya_vc> nerdboy, Wormo ^^
Jun 12 14:32:12 <jic23> ZeekHuge, I suggest you take the time to get a cross building setup running in a PC. It isn't hard and avoids any possible version numbering fun as kernel and modules built together.
Jun 12 14:33:12 <jic23> It is far to easy to get into weird versioning issues doing external builds plus ultimate aim is to upstream a driver which will definitely.
Jun 12 14:33:28 <jic23> Need to be in the kernel tree.
Jun 12 14:34:19 <chanakya_vc> jic23, Hey !I have a doubt regarding SPI
Jun 12 14:34:29 <jic23> Sure... ?
Jun 12 14:35:39 <chanakya_vc> jic23, Okay so I have this doubt regarding the clock phase and clock polarity.
Jun 12 14:36:09 <chanakya_vc> When you say that clock phase is say 1  and clock polarity is also 1.
Jun 12 14:36:36 <chanakya_vc> Toh that means that we would be sampling at the second rising edge of the clock.
Jun 12 14:37:20 <jic23> Hmm will need to check spec. It is all kind of made up conventions away!
Jun 12 14:37:25 <chanakya_vc> Now does the slave does that on its own(because it is internally programmed ) to only start sample on the second rising edge
Jun 12 14:38:35 <chanakya_vc> I mean mosi can be anything before this event happens. But only when the master generates the clock in this manner does the slave start sampling?
Jun 12 14:39:58 <chanakya_vc> Like the master does not worry about setting mosi in between the clock cycle.Like mosi can be set before the clock cycle
Jun 12 14:40:06 <jic23> Hmm cpol 1 means high when not clocking.
Jun 12 14:40:33 <jic23> Cpha 1 means sample on falling edge.
Jun 12 14:41:14 <chanakya_vc> Yes sorry the second falling edge incase of cpol=1 and cpha=1
Jun 12 14:41:35 <jic23> Sure it is second?
Jun 12 14:42:09 <jic23> Master is driving both clock and data so can set data before clock starts.
Jun 12 14:43:05 <ZeekHuge> Hey jic23 !
Jun 12 14:43:15 <chanakya_vc> Yes,that's what I wanted to know. Like if I say I am transmitting at cpol=1 and cpha=1,my slave is designed to work like that right?
Jun 12 14:43:17 <chanakya_vc> jic23,
Jun 12 14:43:21 <chanakya_vc> jic23, ^^
Jun 12 14:43:26 <jic23> Slave can set data on chipselect drop. Doesn't need first edge.
Jun 12 14:44:05 <jic23> Is it a common spec, thinking it maybe that very few devices use it...
Jun 12 14:44:12 <ZeekHuge> Yep I already had a cross building setup ,  I just wanted to avoid that full kernel building process, as it takes some time. though it is just required once. I have it working now.
Jun 12 14:44:16 <ZeekHuge> jic23: ^
Jun 12 14:44:38 <jic23> Find one that does in kernel tree then look at that data sheet.
Jun 12 14:45:16 <chanakya_vc> jic23,  Okay,please take a look at this whenever you are free:https://github.com/chanakya-vc/PRU-I2C_SPI_master/blob/wip_on_spi/pru0_spi.c
Jun 12 14:45:21 <jic23> ZeekHuge, sure time consuming first time plus on updates of the tree.
Jun 12 14:45:43 <chanakya_vc> And let me know what do you think of the logic jic23 ?
Jun 12 14:48:38 <jic23> Chanakya_vc masking for the zero writes is odd I think... I think you want &=~(1<<x)
Jun 12 14:48:55 <jic23> To avoid hammering other bits.
Jun 12 14:49:10 <jic23> Anyhow back later probably.
Jun 12 14:50:44 <chanakya_vc> jic23, Okay got it. Though I didn't understand why what I have done is wrong
Jun 12 15:46:08 <chanakya_vc> hey alexhiam I have pushed updated code along with an updated makefile and updated readme.
Jun 12 15:47:44 <chanakya_vc> So now one can compile code from scratch following the  readme
Jun 12 15:51:00 <chanakya_vc> alexhiam,  Can you check out the code and see if its producing the right waveforms?Whenever you are free
Jun 12 16:28:07 <nerdboy> you doubt it will work?  you doubt it exists? what...
Jun 12 16:51:16 <chanakya_vc> nerdboy, Is that question to me?
Jun 12 16:52:04 <chanakya_vc> nerdboy, It's just that I donot have connecting wires. And I am stuck at home for the weekend so I cannot test my code.
Jun 12 17:50:41 <m_w> ZeekHuge: you get the kernel module to load yet?
Jun 12 17:51:59 <ZeekHuge> m_w: yes yes, almost ready .
Jun 12 17:52:19 <m_w> okay
Jun 12 17:52:21 <m_w> phew
Jun 12 17:52:25 <ZeekHuge> just putting things together.
Jun 12 18:00:26 <ZeekHuge> m_w: I can put my copyright on things that i write from scratch based on various generic sources and examples from kernel.org ?
Jun 12 18:00:57 <m_w> sure
Jun 12 18:01:14 <ZeekHuge> okay .
Jun 12 18:46:40 <pmezydlo> mw: I tested MCSPI, driver copied the data from RX0 to TX0. I don't see problem with loading data from TX to shift register during transmision.
Jun 12 18:46:48 <pmezydlo> m_w: hi ^^
Jun 12 18:47:15 <m_w> without toggling the chip select?
Jun 12 18:48:15 <pmezydlo> yes
Jun 12 18:48:21 <pmezydlo> without cs
Jun 12 18:48:23 <pmezydlo> transactions up to 32 bytes should work without problems
Jun 12 18:49:17 <m_w> you have to load tx based on the first half of rx in the case of SPI NOR
Jun 12 18:52:21 <m_w> the address of the data is received and the data is expected on the next clock cycle
Jun 12 18:53:35 <pmezydlo> I think that SPI NOR can be a problem
Jun 12 18:55:44 <m_w> excellent progress btw the way
Jun 12 18:56:09 <m_w> by the way
Jun 12 18:56:34 <pmezydlo> load tx then receive rx and send tx is real and will work quite well
Jun 12 18:59:14 <m_w> seems backwards
Jun 12 18:59:23 <pmezydlo> we have to wait for further development then we can say more
Jun 12 19:03:55 <nerdboy> better than having your feet on backwards...
Jun 12 19:04:05 <pmezydlo> _av500_ alexhiam m_w: On Wednesday, I can not be at the meeting
Jun 12 19:05:09 <pmezydlo> I have to go on exam wtih Analog Electronic Systems
Jun 12 19:14:22 <m_w> okay note that in your report for the week
Jun 12 19:16:10 <chanakya_vc> hey m_w Are you free for the moment?
Jun 12 19:16:23 <m_w> sure
Jun 12 19:16:41 <m_w> whats up?
Jun 12 19:16:54 <chanakya_vc> Can you please check the waveforms my code is generating?
Jun 12 19:17:01 <chanakya_vc> https://github.com/chanakya-vc/PRU-I2C_SPI_master/tree/wip_on_spi
Jun 12 19:17:33 <chanakya_vc> I have updated the instructions on Readme.md?If you are free please do check it out
Jun 12 19:18:02 <chanakya_vc> And tell me if they look okay? m_w
Jun 12 19:18:22 <m_w> sure
Jun 12 19:19:31 <chanakya_vc> hey jic23 ,I could not understand your earlier point about the code that you wrote. Why is this __R30&=(0<<P8_11) wrong?
Jun 12 19:20:42 <m_w> 0 << anything is 0
Jun 12 19:21:05 <chanakya_vc> m_w, DO you have the PRU code generation tools and Software support package installed?
Jun 12 19:21:15 <chanakya_vc> So it won't shift 0 to P8_11?
Jun 12 19:21:31 <m_w> absolutely not
Jun 12 19:22:40 <m_w> are you trying to only set that bit to zero?
Jun 12 19:22:48 <chanakya_vc> Yes m_w
Jun 12 19:23:28 <m_w> then the rest have to be ones before anding
Jun 12 19:23:34 <chanakya_vc> It won't work? But even if I do this __R30&=~(1<<P8_11)
Jun 12 19:24:02 <chanakya_vc> It is shifting one and then turning that bit to zero right?
Jun 12 19:24:11 <m_w> that is better
Jun 12 19:24:31 <chanakya_vc> But I still don't get why?
Jun 12 19:24:44 <chanakya_vc> I mean when I say 0<<P8_11
Jun 12 19:25:07 <m_w> because all of the bit will be zero
Jun 12 19:25:19 <m_w> 0 << anything = 0
Jun 12 19:25:43 <chanakya_vc> So it will generate a number like 000000?
Jun 12 19:25:54 <m_w> yeah
Jun 12 19:25:59 <m_w> just 0
Jun 12 19:26:36 <m_w> so it would clear the whole register with the and operation
Jun 12 19:27:01 <chanakya_vc> Oh okay.And when I am doing ~(1<<P8_11) So this would generate 0 at the specified bit and 1 at all others?
Jun 12 19:27:47 <chanakya_vc> Am I right in my reasoning m_w ?
Jun 12 19:28:35 <chanakya_vc> Let me just correct this m_w ?Will take me just 5 minutes.Perhaps you could check after that?
Jun 12 19:28:38 <m_w> yeah
Jun 12 19:28:45 <m_w> sure
Jun 12 19:31:59 <chanakya_vc> m_w, Done.
Jun 12 19:33:59 <m_w> chanakya_vc: lets take a look
Jun 12 19:34:22 <chanakya_vc> m_w, I have not mentioned about the pins that you need to configure using config pin,P8_11 and P8_12
Jun 12 19:34:39 <chanakya_vc> i.e mosi and clock
Jun 12 19:44:06 <chanakya_vc> m_w, Did it compile correctly?
Jun 12 19:45:01 <m_w> I don't have the evironment setup for this
Jun 12 19:45:13 <m_w> do you have wiki that show how to do it?
Jun 12 19:45:46 <chanakya_vc> You don't have the PRU code generation tools and the software support pkg?
Jun 12 19:45:49 <chanakya_vc> m_w, ?
Jun 12 19:46:03 <m_w> not on this machine
Jun 12 19:46:35 <chanakya_vc> Just wait a minute. Maybe I will give you the links to download?
Jun 12 19:46:38 <chanakya_vc> m_w, ?
Jun 12 19:46:51 <m_w> how about a howto wiki?
Jun 12 19:47:02 <m_w> with the exact steps
Jun 12 19:47:52 <chanakya_vc> Well there is no exact howto wiki.I have given the steps on the readme.But they are not too elaborate I guess
Jun 12 19:47:57 <chanakya_vc> m_w, ^^
Jun 12 19:48:41 <m_w> let me look at the readme and see if it is sufficient
Jun 12 19:48:54 <chanakya_vc> m_w, Okay I think the first step should to be make the readme as more helpful as possible.
Jun 12 19:50:00 <chanakya_vc> I modified the makefile and introduced the variable PRU_SW_PKG .
Jun 12 19:51:11 <m_w> please document the process of getting the build environment setup from scratch and send me an email when it is ready
Jun 12 19:52:05 <alexhiam> chanakya_vc: just tried the new firmware - you're still missing the resource table
Jun 12 19:52:34 <chanakya_vc> alexhiam, It's not compiling?
Jun 12 19:52:45 <alexhiam> it's compiling, but not loading on the pru
Jun 12 19:52:56 <alexhiam> that same 'header-less resource table' issue
Jun 12 19:53:45 <chanakya_vc> alexhiam, Strange I have not changed that part at all.
Jun 12 19:53:51 <chanakya_vc> m_w, I will definitely do so
Jun 12 19:54:38 <m_w> other non specific comment - why are the binaries in the repository?
Jun 12 19:55:34 <alexhiam> chanakya_vc: wait, nvm, for some reason git just isn't pulling down the latest...
Jun 12 19:56:39 <chanakya_vc> m_w, Got committed by mistake.Actually it generates the obj file in the gen folder and it lies on the folder I pushed. I will remove it
Jun 12 19:56:50 <chanakya_vc> Sorry for that m_w
Jun 12 19:57:01 <alexhiam> .gitignore is your friend
Jun 12 19:57:22 <m_w> yeah add it to the .gitignore
Jun 12 19:57:53 <chanakya_vc> So I add that gen folder to .gitignore?So how do I do it?
Jun 12 19:58:49 <m_w> gen/*
Jun 12 19:59:58 <chanakya_vc> so will this echo gen/*>>.gitignore ?
Jun 12 20:00:29 <chanakya_vc> m_w, alexhiam ^^
Jun 12 20:00:49 <m_w> or just edit the file and add the line manually
Jun 12 20:01:27 <m_w> you will need to remove the files from the repo too
Jun 12 20:01:50 <m_w> try google it is your friend
Jun 12 20:02:08 <chanakya_vc> I have no .gitignore in my folder :P I never realized until now
Jun 12 20:02:10 <chanakya_vc> m_w,
Jun 12 20:02:19 <m_w> it is a hidden file
Jun 12 20:02:35 <m_w> and it is in the repository so it is probably there
Jun 12 20:02:40 <alexhiam> ls -a
Jun 12 20:02:58 <alexhiam> it has some stuff in it already
Jun 12 20:03:06 <chanakya_vc> alexhiam, Do tell whenever you get my latest commit.
Jun 12 20:03:28 <chanakya_vc> Ohh but it doesn't show in the nautilus
Jun 12 20:03:49 <alexhiam> ctrl+h in nautilus
Jun 12 20:04:02 <chanakya_vc> Oh okay
Jun 12 20:04:21 <alexhiam> chanakya_vc: getting closer: http://pasteboard.co/1DrgBw9x.png
Jun 12 20:05:24 <chanakya_vc> The clock seems to be uniform now at least for some part
Jun 12 20:06:14 <alexhiam> does the spi spec call for a 50% duty cycle?
Jun 12 20:06:49 <alexhiam> that pulse is pretty small
Jun 12 20:07:37 <chanakya_vc> alexhiam, You know I have this fundamental doubt regarding SPI modes.When you say we are going to be using cpha=1 and cpol=1,the slave itself(due to its internal programming),will sample at the appropriate edge of the clock?
Jun 12 20:08:07 <alexhiam> chanakya_vc: the slave dictates the clock mode
Jun 12 20:09:15 <alexhiam> e.g. CPHA=1 might be required if the device needs some extra time to think before it starts sending or receiving
Jun 12 20:09:57 <chanakya_vc> alexhiam, Just take a look at the code. I have set mosi before I toggle the clock,Here I am assuming that the slave will automatically sample when the appropriate edge comes
Jun 12 20:10:42 <chanakya_vc> I mean the master doesnot have to worry about setting the mosi line at the appropriate edge.It just has to toggle clock
Jun 12 20:10:54 <chanakya_vc> According to the clock polarity
Jun 12 20:11:10 <alexhiam> right, but if it's designed for a max of 10MHz or whatever, and it depends on the next edge to change state, it's possible that edge could come too early if it's not a 50% duty cycle
Jun 12 20:11:24 <alexhiam> I don't actually know if that's a concern with spi though...
Jun 12 20:12:43 <chanakya_vc> hmmn this complicates things a bit.
Jun 12 20:13:10 <alexhiam> chanakya_vc: were you planning on implementing the clock speed?
Jun 12 20:13:10 <chanakya_vc> alexhiam, Maybe I can put a delay between the toggle of the clock?
Jun 12 20:13:53 <chanakya_vc> Clock speed of 10 Mhz initially
Jun 12 20:14:06 <chanakya_vc> If that's what you are asking alexhiam
Jun 12 20:14:51 <alexhiam> well, I wouldn't worry about that yet anyways
Jun 12 20:15:07 <alexhiam> still something to figure out with the logic
Jun 12 20:19:00 <chanakya_vc> alexhiam, The number of times the clock is toggling is also not correct right?
Jun 12 20:19:37 <alexhiam> chanakya_vc: right. Interestingly with clock mode 0 it does look right: http://pasteboard.co/1Dsd3Iar.png
Jun 12 20:20:03 <chanakya_vc> It should go from 1 to 0 to 1 8 times
Jun 12 20:20:28 <chanakya_vc> Yes it does look right alexhiam except the last clock pulse
Jun 12 20:20:28 <alexhiam> yeah
Jun 12 20:20:44 <alexhiam> the slightly longer one?
Jun 12 20:20:48 <chanakya_vc> Yes
Jun 12 20:20:56 <alexhiam> yeah, not sure why that would happen///
Jun 12 20:20:58 <alexhiam> ...
Jun 12 20:21:21 <chanakya_vc> Second last one.It does look strange.
Jun 12 20:22:29 <alexhiam> note that you couldn't just add a delay to even out the clock pulses because you're already at 10MHz. I guess you'd have to either optimize this more or switch to assembly to get 10MHz with a 50% duty cycle
Jun 12 20:22:53 <chanakya_vc> But it is transmitting 110.
Jun 12 20:23:06 <alexhiam> huh?
Jun 12 20:23:57 <chanakya_vc> No I was just saying it is transmitting 6 which is correct :P
Jun 12 20:24:20 <alexhiam> oh, chanakya_vc, that slightly longer pulse is likely a red herring, my probe setup is very messy
Jun 12 20:25:04 <chanakya_vc> alexhiam, But writing it from scratch in assembly will be a difficult task now that I have spent so much time already on embedded c
Jun 12 20:25:05 <alexhiam> probably just a lot of noise which kept the signal above the logic analyzer's threshold a bit longer
Jun 12 20:25:26 <alexhiam> chanakya_vc: no, it'll be much easier because now you know spi so well ;)
Jun 12 20:25:46 <alexhiam> chanakya_vc: I wouldn't worry about the duty cycle at all right now
Jun 12 20:26:12 <chanakya_vc> Okay. It will even more difficult for me to test using my test setup of sigrok clone and cheap wires.
Jun 12 20:26:34 <chanakya_vc> alexhiam, I will likely borrow a mixed signal oscilloscope from the lab
Jun 12 20:26:42 <chanakya_vc> and test it on it
Jun 12 20:27:21 <alexhiam> chanakya_vc: cool. best to do any timing measurements with the analog channels for that very reason
Jun 12 20:27:35 <alexhiam> here's a cleaner looking capture: http://pasteboard.co/1DsNjN8E.png
Jun 12 20:32:09 <chanakya_vc> But I am glad atleast it is working in case 0.Might work for case 1 also because the code is exactly same as case 0.
Jun 12 20:32:11 <chanakya_vc> alexhiam, ^^
Jun 12 20:32:27 <chanakya_vc> I have to got to optimize it for case 2 and case 3
Jun 12 20:32:57 <alexhiam> chanakya_vc: here's a scope capture: http://pasteboard.co/1Dtbt9Vi.png
Jun 12 20:33:07 <alexhiam> (you can see how noisy it is)
Jun 12 20:33:40 <alexhiam> and the logic analyzer doesn't have shielded cables
Jun 12 20:34:50 <alexhiam> chanakya_vc: wait, yeah, 1 is exactly the same, you're not handling the clock phase
Jun 12 20:36:46 <chanakya_vc> alexhiam, That's what my doubt is? In case of 1 the slave will automatically start sampling after if I give one clock cycle right?
Jun 12 20:37:00 <chanakya_vc> So all I have to do is add a clock cycle?
Jun 12 20:39:03 <alexhiam> no, it's not a full cycle
Jun 12 20:39:43 <alexhiam> basically if CPOL=0 it data is sampled on the first clock edge, and if it's 1 it's sampled on the second
Jun 12 20:40:00 <chanakya_vc> Yes the falling edge in this case
Jun 12 20:40:05 <chanakya_vc> alexhiam, ^^
Jun 12 20:40:07 <alexhiam> and whether the first clock edge is rising or falling depends on CPOL
Jun 12 20:40:15 <alexhiam> https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Clock_polarity_and_phase
Jun 12 20:40:15 <gcl-bot> [WIKIPEDIA] Serial Peripheral Interface Bus#Clock polarity and phase | "The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include Secure Digital cards and..."
Jun 12 20:40:27 <alexhiam> shut up gcl-bot
Jun 12 20:40:37 <alexhiam> :P
Jun 12 20:40:45 <chanakya_vc> I doubt it understands that
Jun 12 20:40:57 <chanakya_vc> Maybe we could code that into it later :P
Jun 12 20:42:29 <chanakya_vc> alexhiam,  Anyway,what I was saying in case 1,where cpol=0 and cpha=1,the slave would sample on the falling edge ,i.e when clock will go from 0-1-0,then itwill
Jun 12 20:43:19 <chanakya_vc> So it would work.I mean the master doesn't care which edge the slave is sampling as long it knows that CPOL=0
Jun 12 20:43:32 <alexhiam> case 1 is cpha=1 and cpol=0
Jun 12 20:43:47 <alexhiam> you put cpol in bit 2
Jun 12 20:43:54 <alexhiam> bit 1 that is...
Jun 12 20:45:51 <chanakya_vc> alexhiam, I didn't get your last statement? CPOL=0 and CPHA=1 will result in case 1 I think
Jun 12 20:46:38 <alexhiam> yup, read it backwards the first time you wrote it...
Jun 12 20:47:03 <chanakya_vc> Ohh
Jun 12 20:48:48 <chanakya_vc> alexhiam,  So what do you think? Will my logic work?I think the master is not concerned with which edge the slave samples.Only thing the master should know is CPOL.
Jun 12 20:49:48 <chanakya_vc> Because if you look at the analyzer capture,even if the slave read at falling edges,it would still give the correct value
Jun 12 20:53:19 <alexhiam> chanakya_vc: right, but if cpol=0, with that 12.ns pulse, what if a device expecting 10MHz doesn't have enough time to read the data before you change it again?
Jun 12 20:53:25 <alexhiam> that's where that might be a problem
Jun 12 20:56:10 <chanakya_vc> That can be a problem in case 0 also right alexhiam ?
Jun 12 20:56:49 <alexhiam> right, sorry, not cpol=0, that's when cpha=0
Jun 12 20:57:36 <chanakya_vc> But if I introduce any sort of delay in clock,frequency will get messed up
Jun 12 20:57:49 <alexhiam> yeah, Id say leave it for now
Jun 12 20:58:34 <chanakya_vc> I can deal with it in the end
Jun 12 20:58:59 <chanakya_vc> alexhiam, The frequency in the scope is 11.1 Mhz,Got to get that to 10 Mhz
Jun 12 20:59:26 <alexhiam> chanakya_vc: burn a few cycles between those clock toggles then ;)
Jun 12 21:00:42 <chanakya_vc> alexhiam,  Haha :P But I am assuming that these slave devices would have some tolerance to frequency variations?
Jun 12 21:01:04 <alexhiam> with spi devices just give their max frequency
Jun 12 21:01:27 <alexhiam> so if it is 10MHz for a device, 11.1MHz may not work...
Jun 12 21:01:27 <chanakya_vc> ohh
Jun 12 21:01:50 <chanakya_vc> Ohh.This may be a problem
Jun 12 21:02:28 <chanakya_vc> alexhiam, And I thought getting frequency upto 10 Mhz would be a challenge :P
Jun 12 21:03:48 <chanakya_vc> alexhiam,  So I am set for case 0 and case 1 for now I guess. I will work on case 2 and case 3 tomorrow and hopefully get them right?
Jun 12 21:03:57 <chanakya_vc> *.
Jun 12 21:04:45 <alexhiam> cool
Jun 12 21:06:12 <chanakya_vc> alexhiam, The other thing that I wanted to ask you is regarding the stuff you were talking about a way to access the shared mem?
Jun 12 21:06:41 <chanakya_vc> During the meeting,when you and ds2 were suggesting some way?
Jun 12 21:08:17 <alexhiam> chanakya_vc: which way? The 2 big options are having the pru access the DDR3 RAM, or having the ARM access the PRU-ICSS RAM
Jun 12 21:08:58 <chanakya_vc> alexhiam, I am checking the logs.I don't remember it exactly.
Jun 12 21:09:17 <alexhiam> the former means the PRU is going through the L3 interconnect, which adds unpredictable latencies, and means if you need realtime behavior on the PRU you basically need to use 1 PRU for accessing the DDR3 and 1 for your application
Jun 12 21:09:21 <alexhiam> (which is a bummer)
Jun 12 21:09:52 <alexhiam> using a single PRU it's best to have the ARM access the PRU-ICSS RAM
Jun 12 21:13:29 <chanakya_vc> Yes found it alexhiam PRU interrupts A8 and A8 does a burst read
Jun 12 21:15:13 <chanakya_vc> Okay so I get the ARM to access the PRU-ICSS ram.But this method won't use the RPMsg I believe?
Jun 12 21:15:18 <chanakya_vc> alexhiam, ^^
Jun 12 21:16:41 <alexhiam> right
Jun 12 21:18:24 <chanakya_vc> alexhiam,  Also,on the PRU side, if I simply declare a pointer say int *a=0x0000,this would point to a mem loc in this RAM right?
Jun 12 21:18:53 <chanakya_vc> Please ignore the incorrect def of a pointer
Jun 12 21:19:59 <chanakya_vc> I mean if I say &a=0x0000
Jun 12 21:20:19 <chanakya_vc> It will point to a mem loc in this RAM right?
Jun 12 21:20:46 <alexhiam> yeah, you were right the first time ;)
Jun 12 21:21:01 <alexhiam> the PRU reference guide has the local memory map
Jun 12 21:21:46 <alexhiam> no virtual memory, so your C code can directly access anything in there at the addresses given (so plenty of ways to break things :P)
Jun 12 21:21:58 <chanakya_vc> But *a is the value right?&a is the address to which it points?
Jun 12 21:22:13 * chanakya_vc needs to revise basic concepts of pointers
Jun 12 21:22:54 <alexhiam> yeah, definitely read up on pointers!
Jun 12 21:23:11 <alexhiam> * does different things in c
Jun 12 21:23:46 <alexhiam> & gets the address of something, but isn't be used in declaring or assigning
Jun 12 21:24:36 <chanakya_vc> Ohh,so If I say int *a-0x0000,it actually assigns the pointer to that memory loc?
Jun 12 21:24:58 <chanakya_vc> int *a=0x0000
Jun 12 21:26:29 <chanakya_vc> alexhiam,  Maybe I got confused.Because I remember that(atleast in c++) *a returns the value of the pointer.
Jun 12 21:28:02 <alexhiam> a pointer is just a number. If you declare 'int *a=0', you've created the pointer a with the value 0. You can then use that to access what's at 0 in memory, and the 'int *' part tells the compiler what type to expect there
Jun 12 21:29:44 <alexhiam> you can also dereference (or 'follow') a pointer with *, so '(*a)=1' would go try to set the value stored at the memory location given by the value of 'a' to 1
Jun 12 21:31:45 <alexhiam> e.g.: 'int a = 10; int *b = &a; (*b) = 20;' after that the value of 'a' would be 20
Jun 12 21:42:19 <chanakya_vc> alexhiam,  I am just confused in the first bit,when you are saying int *a =0, now 'a' points to the memory loc 0 or the value stored at the mem loc where a points is 0?
Jun 12 21:43:15 <alexhiam> a stores the value 0, and can be used to access whatever value is there
Jun 12 21:50:04 <chanakya_vc> Got it alexhiam .
Jun 12 22:00:24 <chanakya_vc> alexhiam, It is a bit confusing. In table 4 it says that IRAM begins at 0X0000_0000. Then in table 5 it says that data ram 0f 8kb also starts at the same address?
Jun 12 22:01:10 <chanakya_vc> Why is that?
Jun 12 23:06:41 <ZeekHuge> so its here https://github.com/ZeekHuge/BeagleScope/tree/master/examples/kernel_examples
Jun 12 23:06:43 <ZeekHuge> finally
Jun 12 23:08:28 <ZeekHuge> please provide some review on it .. I have tried to take care of every single thing. coding style, function names, use of generic methods and everything that i have known till now, about the kernel module writing
Jun 12 23:08:34 <ZeekHuge> except comments
Jun 12 23:09:00 <ZeekHuge> I will add them along ... but along doing next steps
Jun 12 23:10:06 <ZeekHuge> and yeah, need to add mutex locks also at some places, where I felt there might be chance of call of a function while other is trying to change a critical value
Jun 12 23:10:26 <ZeekHuge> I have even tried to take care of Makefiles
Jun 12 23:11:21 <ZeekHuge> I mean I have put a lot of efforts in it. To understand, to write and to read (other docs) .. please provide some feedback :)
Jun 12 23:11:26 <ZeekHuge> m_w: ^
Jun 12 23:11:29 <ZeekHuge> Abhishek_: ^
Jun 12 23:11:32 <ZeekHuge> ds2: ^
Jun 12 23:12:21 <ZeekHuge> alexhiam: ^
Jun 12 23:17:43 <ZeekHuge> and a post explaining about rpmsg and all this code will be up by the next meeting. I should now focus on next steps.
Jun 12 23:29:40 <ZeekHuge> anyone ? reading or read ?
Jun 12 23:33:27 <m_w> gimmie a minute
Jun 12 23:35:16 <ZeekHuge> okay :)  ... I'll be back in a minute
Jun 12 23:41:03 <ZeekHuge> On mobile... Actually my external monitor is having some problem. First it starts at low resolution .
Jun 12 23:41:27 <ZeekHuge> Then I use xrandr to go higher
Jun 12 23:41:58 <ZeekHuge> It works for an hour or so and the starts disconnecting/connecting
Jun 12 23:42:10 <ZeekHuge> Anyways ..
Jun 13 00:42:18 <m_w> ZeekHuge: you back?
**** ENDING LOGGING AT Mon Jun 13 02:59:58 2016