**** BEGIN LOGGING AT Mon Feb 20 03:00:01 2017
Feb 20 11:30:32 <tokencolour> Hello all.
Feb 20 11:31:01 <zeekhuge> Hey tokencolour !
Feb 20 11:31:49 <tokencolour> I want to participate in GSoC this year through BeagleBoard.org.
Feb 20 11:32:08 <tokencolour> I went through http://elinux.org/BeagleBoard/GSoC/Ideas.
Feb 20 11:32:51 <zeekhuge> And ? what idea seems interesting to you ?
Feb 20 11:33:04 <tokencolour> and I am interested in the idea BeagleBone/Beagle board PRU DMA
Feb 20 11:33:29 <zeekhuge> Do you have a BBB ? some experience with PRUs ?
Feb 20 11:33:54 <zeekhuge> and about DMA ?
Feb 20 11:34:49 <tokencolour> I am unable to find some references in relation to this.
Feb 20 11:35:06 <zeekhuge> like about the PRUs ? or about what DMA is ?
Feb 20 11:35:38 <tokencolour> I did run a few examples with the PRU.
Feb 20 11:36:03 <tokencolour> and I have studied what DMA is in my microprocessor classes.
Feb 20 11:36:19 <zeekhuge> cool !
Feb 20 11:36:21 <tokencolour> but I am unable to find a starting point.
Feb 20 11:37:04 <zeekhuge> so, the point is about sharing data between the main processor (A8) and the PRUs.
Feb 20 11:37:17 <zeekhuge> since there is no DMA support as of now.
Feb 20 11:37:32 <zeekhuge> what we mostly do is :
Feb 20 11:37:43 <zeekhuge> use 1 PRU to manage the I/O
Feb 20 11:38:08 <zeekhuge> and use the other PRU to do all the data transfer between PRUSS and the A8
Feb 20 11:38:35 <zeekhuge> that project aims at developing DMA support to get data from the PRUSS
Feb 20 11:38:58 <tokencolour> so that we can free the second PRU
Feb 20 11:38:59 <zeekhuge> and hence allow developers to use both PRUs to manage I/O or other processing.
Feb 20 11:40:16 <tokencolour> Thanks zeekhuge for the explanation.
Feb 20 11:41:04 <tokencolour>  However, I am stuck as to how to start with the planning required to start with the proposal
Feb 20 11:41:28 <tokencolour>  I need to visualize what exactly I'll need to do.
Feb 20 11:42:04 <tokencolour>  Also, I'm not very familiar with linux kernel programming.
Feb 20 11:42:10 <zeekhuge> well, ds2 will be able to guide more on that, and he'll be available (if) only after like 8-9 PM (IST)
Feb 20 11:42:35 <zeekhuge> tokencolour: you familiar with linux based os in general right ?
Feb 20 11:43:03 <tokencolour> yes. I use it daily.
Feb 20 11:43:08 <zeekhuge> Cool then .
Feb 20 11:43:37 <zeekhuge> About the project, what I can imagin is about exploring how the current methods actually work
Feb 20 11:43:52 <zeekhuge> then, diving into linux kernel code and see how DMA works there ..
Feb 20 11:44:09 <zeekhuge> you definitely need to learn kernel coding for that
Feb 20 11:44:21 <zeekhuge> there are numerous resources for that.
Feb 20 11:46:03 <tokencolour> Should I see how linux kernel does DMA and think how I'll make it work for the PRU?
Feb 20 11:46:45 <zeekhuge> I think so.
Feb 20 11:46:54 <tokencolour> Which resource for learning kernel coding do you recommend?
Feb 20 11:47:24 <zeekhuge> ldd3
Feb 20 11:48:46 <tokencolour> Thank you zeekhuge. I'll go through it.
Feb 20 15:40:51 <pmezydlo> m_w: hi, I managed to compile kernel with spi slave by Geerts. Config file was Beaglebone with some recommended changes that attach slave support,
Feb 20 15:45:55 <pmezydlo> Now i will try add slave support to OMAP. Unfortunately I don't have a lot of time but it doesn't require many modifications
Feb 20 16:55:00 <m_w> pmezydlo: awesome
Feb 20 17:06:54 <pmezydlo> Soon I will have to begin to develop my project brief
Feb 20 17:08:02 <pmezydlo> m_w: Do you think there will be FPGA project this year?
Feb 20 17:08:36 <m_w> I hope so
Feb 20 17:09:20 <pmezydlo> I would like to do project based on FPGA and beaglebone
Feb 20 17:09:37 <m_w> anything specific?
Feb 20 17:10:37 <pmezydlo> I think about ice40 cape for BBB
Feb 20 17:11:23 <pmezydlo> and using pru I want to program FPGA
Feb 20 17:11:45 <m_w> the ice40 use SPI to program actually
Feb 20 17:11:56 <m_w> so you don't need the PRU
Feb 20 17:12:24 <pmezydlo> and I think that develop bridge between fpga and arm on pru its good idea
Feb 20 17:13:27 <m_w> any advantage over mmio?
Feb 20 17:15:21 <pmezydlo> probably no advantage except relief CPU
Feb 20 17:16:05 <m_w> well the PRU needs to be accessed via mmio as well
Feb 20 17:16:07 <pmezydlo> ICE40 have support from kernel?
Feb 20 17:16:24 <m_w> there is a patch out on the mailing lists
Feb 20 17:16:37 <m_w> not sure if it was merged yet
Feb 20 17:17:01 <pmezydlo> and is it mapped in memory?
Feb 20 17:17:52 <pmezydlo> I have to look at what is this support
Feb 20 17:17:55 <m_w> it is the programming interface only
Feb 20 17:18:21 <pmezydlo> it is not too much
Feb 20 17:18:34 <m_w> interactionwith the fpga varies from platform to platform
Feb 20 17:18:59 <m_w> some use peripheral interfaces like SPI,I2C or I2S
Feb 20 17:19:10 <m_w> some use MMIO
Feb 20 17:20:14 <m_w> the FPGA support in the kernel is primarily programming and standard memory map interface drivers
Feb 20 17:20:27 <m_w> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga
Feb 20 17:21:05 <m_w> fpga-mgr is the programming interface which can also load mmio drivers
Feb 20 17:22:00 <m_w> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/fpga/fpga-mgr.txt
Feb 20 17:23:54 <m_w> check this out: https://fosdem.org/2017/schedule/event/floss_high_level_synth/
Feb 20 17:24:28 <pmezydlo> ok i will have a look
Feb 20 17:27:24 <m_w> if I make a ice40 cape, I bet they would allow a project to add support for it
Feb 20 17:28:20 <m_w> they don't like the hardware to be the focus of the project
Feb 20 17:33:13 <pmezydlo> Yes this is obvious but I don't like this. We should think about how to support this.
Feb 20 17:35:00 <m_w> shouldn't be a problem if we get the hardware ready in advance
Feb 20 17:36:16 <m_w> while I am at ELC, I can get started on the hardware
Feb 20 17:36:34 <m_w> leaving for Portland today
Feb 20 17:37:08 <pmezydlo> ok I will let you know when I prepare better about this idea
Feb 20 17:37:15 <m_w> I will post the design to github so you can colloborate
Feb 20 17:39:26 <pmezydlo> Can you give me an already started kicad project? I can finish it
Feb 20 17:40:48 <m_w> maybe, you want in on the hardware design side?
Feb 20 17:41:58 <pmezydlo> yes I want
Feb 20 17:42:18 <m_w> if I create a github you can fork it and do pull requests
Feb 20 17:42:38 <m_w> then I can mentor you through the process
Feb 20 17:42:38 <pmezydlo> yes this is good solutions
Feb 20 17:42:40 <pmezydlo> thanks
Feb 20 17:43:15 <pmezydlo> pcb design is an interesting case
Feb 20 17:43:24 <m_w> done any substantial PCB design before?
Feb 20 17:45:41 <pmezydlo> yes I created some (5 pcs) pcb
Feb 20 17:46:01 <m_w> what was the design?
Feb 20 17:46:41 <pmezydlo> mostly adapter to gold pins
Feb 20 17:47:06 <m_w> well this will be a bit more complicated than that :D
Feb 20 17:47:07 <pmezydlo> one beaglebone cape
Feb 20 17:47:42 <pmezydlo> one pcb for AVR
Feb 20 17:47:55 <m_w> I think that we should do something similar to the logi-bone but with an FPGA
Feb 20 17:48:06 <pmezydlo> how much layer do you use
Feb 20 17:48:11 <m_w> http://valentfx.com/logi-bone/
Feb 20 17:48:23 <m_w> this would be at least 4 layers
Feb 20 17:50:13 <pmezydlo> until now I used eagle
Feb 20 17:50:34 <m_w> the free version of eagle won't cut it
Feb 20 17:50:52 <pmezydlo> but kicad I used only once
Feb 20 17:51:09 <m_w> I use kicad so you might want to start doing some tutorials
Feb 20 17:51:52 <m_w> design a simple board and post it so that I can review
Feb 20 17:52:00 <m_w> so you can get used to the process
Feb 20 17:52:00 <pmezydlo> yes this is similar but tutorials is good options
Feb 20 17:52:56 <pmezydlo> I will prepare simple cape
Feb 20 17:53:42 <pmezydlo> probably for 4 uarts ports on bb
Feb 20 17:54:00 <m_w> sure that should be straight forward
Feb 20 17:54:24 <m_w> RS232?
Feb 20 17:54:41 <pmezydlo> yes -+ 12 to TTL
Feb 20 17:55:29 <m_w> okay please post the design and I will review it as you go
Feb 20 17:57:06 <pmezydlo> yes ok I have to go
Feb 20 17:57:11 <m_w> later
Feb 20 17:57:28 <pmezydlo> it's time for dinner
Feb 20 17:57:30 <pmezydlo> bye
Feb 20 22:01:57 <anandkp92> hi! I'm a GSoC 2017 aspirant and I'd like to work on this project: BeagleBone synchronous data collection [http://elinux.org/BeagleBoard/GSoC/Ideas#BeagleBone_synchronous_data_collection\
Feb 20 22:04:28 <anandkp92> i noted the possible mentor is Hunyue Yau
Feb 20 22:05:13 <anandkp92> Could I get his contact info so that I can get more details on the project?
Feb 20 22:05:57 <ds2> anandkp92: what do you want to know?
Feb 20 22:06:15 <anandkp92> I'd like to know what the project is about, and what the requirements are
Feb 20 22:06:43 <ds2> the project is building the equiv of BeagleLogic but for synchronous acquisition
Feb 20 22:07:14 <ds2> requirements are - 1) Understanding what those terms are; 2) And probally be able to at least build the BeagleLogic stuff
Feb 20 22:07:59 <ds2> rather then contacting me directly, please email the Beagle GSoC list
Feb 20 22:08:09 <anandkp92> ok I'm looking at the beaglelogic wiki
Feb 20 22:08:09 <anandkp92> https://github.com/abhishek-kakkar/BeagleLogic/wiki
Feb 20 22:08:19 <anandkp92> I assume this is a good starting point?
Feb 20 22:08:23 <ds2> do you know what it means to be synchronous?
Feb 20 22:08:27 <anandkp92> yes
Feb 20 22:08:28 <ds2> yes, that is a good starting point
Feb 20 22:08:50 <ds2> okay - the first question for you is - in what ways is the Beaglelogic stuff NOT synchronous
Feb 20 22:09:29 <anandkp92> I dont know the beagle logic part :|
Feb 20 22:10:07 <ds2> okay - have you used a logic analyzer before?
Feb 20 22:10:31 <ds2> or what may be helpful for me is - what are you studying in school right now?
Feb 20 22:10:31 <anandkp92> nope
Feb 20 22:10:43 <anandkp92> i'm in the us. carnegie mellon university
Feb 20 22:10:56 <ds2> what's your major?
Feb 20 22:11:10 <anandkp92> energy sciences, but I specialize in computer engineering
Feb 20 22:11:24 <anandkp92> i have a bachelors in computer science too
Feb 20 22:11:31 <ds2> okay, that gives a rough background
Feb 20 22:12:07 <ds2> in this case, you might want to learn what a logic analyzer is - not sure if you are allowed to, but it won't hurt to look at equipment in the lab at school
Feb 20 22:12:31 <anandkp92> i think i can.
Feb 20 22:12:33 <ds2> what you need to look for is the types of signals you hook up to the logic analyzer
Feb 20 22:12:53 <ds2> pay attention to clocks and any config things relating to it
Feb 20 22:13:03 <ds2> this would give you a background
Feb 20 22:14:00 <anandkp92> ok definitely. thanks!
Feb 20 22:16:03 <anandkp92> Btw, nice to meet you. My name is Anand Prakash
Feb 20 22:16:04 <anandkp92> :)
Feb 20 22:17:16 <ds2> same here... If you have other q's...ask... I may not respond immediately but I usually see stuff here
Feb 20 22:17:56 <anandkp92> ok, if you dont mind could you tell me about this project too BeagleBone/Beagle board PRU DMA?
Feb 20 22:18:23 <anandkp92> dma is the direct memory access?
Feb 20 22:18:59 <ds2> sure -
Feb 20 22:19:36 <ds2> all PRU code I am aware of transfer things between the PRU and the main processor by the action of either the A8 or the PRU
Feb 20 22:19:42 <anandkp92> ok
Feb 20 22:19:50 <ds2> the onboard DMA controller (EDMA) can do the work.
Feb 20 22:20:04 <ds2> the goal of that project is to figure out how to get the EDMA to do it and write sample code to show it doing it
Feb 20 22:20:30 <ds2> i.e. the beaglelogic code xfers things by using one of the PRUs to xfer data. this burns that PRU (there are only 2 per PRUSS)
Feb 20 22:20:46 <anandkp92> i see.
Feb 20 22:20:55 <ds2> moving it to the EDMA can free it up. Conversely, some setups use the ARM side to suck data from the PRUSS
Feb 20 22:21:04 <ds2> it burns cpu cycles. using EDMA can simplify it.
Feb 20 22:21:15 <ds2> so that's the project in a nuthshell
Feb 20 22:21:29 <anandkp92> yeah cause dma doesn't require cpu intervention until the xfer is complete right?
Feb 20 22:21:49 <ds2> yep
Feb 20 22:25:15 <anandkp92> cool, thanks! i'll check these projects and get back to you.
**** ENDING LOGGING AT Tue Feb 21 03:00:00 2017