**** BEGIN LOGGING AT Mon Mar 13 03:00:02 2017 Mar 13 07:57:55 Hi Mar 13 08:50:14 helllo Mar 13 12:07:03 hey someone available here who can help me with sonic anemometer because I can't reach its designated mentor nor any reply came for my post in google group for GSoC ,and also I tries to contact on GitHub but could not reach any one of Steve Arnold and Stephanie Lockwood-Childs Mar 13 12:18:28 thetransformerr: Stephen hangs out here a lot, his nick is nerdboy Mar 13 12:29:02 can you please provide me his expected time on forum or any other contact method Mar 13 12:29:44 because I had also created a issue in a repo on GitHub but no reply came Mar 13 12:30:30 just call him here by nick, he will respond when available :) Mar 13 12:32:47 actually I have never used free node,as communication channel :),so would you tell me how to do that ;) Mar 13 12:33:19 thetransformerr: just like I am calling you now Mar 13 12:34:25 you probably didn't see my meesage Mar 13 12:34:31 thetransformerr: just like I am calling you now Mar 13 12:34:48 okk great thanks Mar 13 12:34:57 most people are notified somehow when their nick is used in a message Mar 13 12:35:34 if you don't want to leave IRC session in background you can always check the logs if someone answered you Mar 13 12:35:45 http://logs.nslu2-linux.org/livelogs/beagle-gsoc/ Mar 13 12:35:50 here are archived logs Mar 13 12:35:59 or maybe try irccloud Mar 13 12:36:01 http://logs.nslu2-linux.org/livelogs/beagle-gsoc.txt Mar 13 12:36:08 and here is log of current day Mar 13 12:36:19 yes, irccloud is also nice option Mar 13 12:36:22 nerdboy:hi!!, I wanted some help for sonic anemometer with beagle board I read past year project and have also read manual of CSAT3 Mar 13 12:36:47 maciejjo:thanks you are great Mar 13 12:36:52 np :) Mar 13 12:36:58 have a nice day Mar 13 12:37:10 thanks, you too Mar 13 12:42:53 nerdboy:but found different objectives, as far as I understood they calculated wind speed directly with measurement of time of flight between a pair of transducer and recevier and then taking average of it, Mar 13 12:44:15 nerdboy:for all three axis Mar 13 15:53:11 m_w: hi, how are you? are you home yet? Mar 13 15:55:09 Hello all!! Mar 13 15:55:26 can anyone tell me if we can hook up a 3S 11.1v battery to beaglebone blue? Mar 13 15:55:36 *lipo battery Mar 13 15:59:48 I do not think 11v it's so too much Mar 13 16:20:16 kiran4399: you definitely need some voltage regulor circuit to bring it down to 5V Mar 13 16:22:13 maciejjo! Mar 13 16:22:15 thanks Mar 13 16:22:20 one more thing.. Mar 13 16:23:16 can anyone tell where I can get the connectors for beaglebone blue? Mar 13 16:24:29 https://hobbyking.com/en_us/jst-sh-6pin-male-with-pig-tail.html/?___store=en_us Mar 13 16:24:34 something like this? Mar 13 16:25:31 maybe this will help: https://github.com/beagleboard/beaglebone-blue/wiki/Accessories Mar 13 16:31:23 where'd he go? Mar 13 16:35:27 nerdboy: someone was looking for you earlier today on channel... I think he left some questions for you Mar 13 16:47:52 pmezydlo: just got home last night Mar 13 16:48:15 pmezydlo: I am moving this week to Carbondale, IL Mar 13 16:48:26 crazy month for me Mar 13 16:50:03 m_w: how can I get those connectors for beaglebone blue? Mar 13 16:52:30 m_w: sounds cool I think, I'm writing application it's almost done, It seems to be quite good, i won't bother you with checking it now Mar 13 16:54:19 We will talk when you have time Mar 13 16:58:27 use the math, luke... Mar 13 17:00:57 kiran4399: you get a blue? Mar 13 17:01:38 https://github.com/beagleboard/beaglebone-blue/wiki/Accessories Mar 13 17:02:12 there are links to the mating cables on this wiki ^ Mar 13 17:12:04 m_w: to communicate with the FPGA we will use GPMC? Mar 13 17:15:45 GPMC would be a good way to communicate Mar 13 17:16:13 that's great Mar 13 17:16:31 pmezydlo: did you add porting the icestorm toolchain to the bbb as part of the proposal? Mar 13 17:17:57 M_w leds blinking? Mar 13 17:19:12 If you want to see my proposal: https://docs.google.com/document/d/1NLaqhycVzBtNikVPBe3HOM3CPWTIxEYpIO2OU6w8aMg/edit?usp=sharing not everything is in English sorry for that Mar 13 17:22:49 m_w: I made some assumptions about the construction BeagleWire Mar 13 17:23:52 The cape I named BealgeWire I hope you like it Mar 13 17:29:28 m_w: I didn't add porting the icestorm toolchain, but I will do it Mar 13 17:54:48 jic23: they are!! Mar 13 17:55:10 pmezydlo: I like the name Mar 13 17:59:22 m_w: it seems this is awesome project, I like, Mar 13 17:59:56 There are generators that generate the bridge module in Verilog automatically. Mar 13 18:00:28 like: qsys from Altera Mar 13 18:01:10 cool Mar 13 18:01:16 You can specify the width of the bus and the size of mapped memory Mar 13 18:02:33 What do you think, do we want to do such thing? Mar 13 18:04:34 I saw that someone in fossi foundation doing it Mar 13 18:05:03 collaborate with them :) Mar 13 18:05:19 fossi is a great effort Mar 13 18:05:39 he is Olof Kindgren Mar 13 18:06:11 yes I have met Olof in person at the last GSoC mentor's summit Mar 13 18:07:11 join #librecores if you want to chat with him Mar 13 18:07:41 implementation automatically generated module can be difficult and take a lot of logic Mar 13 18:08:10 probably give up this idea Mar 13 18:08:55 do you understand me? What what do I mean? Mar 13 18:09:38 xilinx and altera support this solutions Mar 13 18:35:54 M_w cool. Board came up first time without traditional hours of head scratching? How dull :) Mar 13 18:49:38 jic23: well one of the images is not working for some reason, so I might have to debug that Mar 13 18:50:43 jic23: might have to install the header so that I can use the serial console Mar 13 18:51:15 That's a Mar 13 18:51:20 Better! Mar 13 18:51:40 don't have a ton of time for it now Mar 13 18:52:04 How it should be... Less of the blowing up or snapping off of components than my normal board bring up :) Mar 13 18:52:04 was out of the office for nearly 2 weeks and am moving this week Mar 13 18:52:16 Good luck with move! Mar 13 18:52:34 it is a minimal design so not a bunch of design worries Mar 13 18:53:24 Chip can always be rotated... And with the board house we use at work often are... Mar 13 18:54:57 Anyhow got to run. Pizza time :) Mar 13 18:58:08 enjoy! Mar 13 22:58:31 m_w: I have one last question, I used fpga to arm bridge on socfpga. it looked like that - environment automatically creates SRAM on fpga (I gave the size and data bus width). This memory has been mapped in arm memory. My FPGA module used this memory like the SRAM(adress, data, oe and we signals). This was convenient. What do you think about this solution? Mar 13 22:59:13 that's a lot of pins Mar 13 23:02:51 inside FPGA is not a problem Mar 13 23:04:31 which arm are you talking about then? Mar 13 23:04:42 ds2: am335x Mar 13 23:04:58 how do you propose to expose the SRAM to the AM335x w/o using a lot of pins? Mar 13 23:05:48 I want to create module inside FPGA which looks like SRAM, on the one side is GPMC and the other side is a SRAM signals Mar 13 23:06:13 right... but the GPMC uses a lot of pins Mar 13 23:06:14 This is to allow for efficient communication Mar 13 23:06:41 GPMC is good solutions I think Mar 13 23:07:07 and it is mapped in memory Mar 13 23:07:50 All GPMC pins are brought out on headers Mar 13 23:08:42 what are you hoping to do on the FPGA? Mar 13 23:11:39 the module is to be general and for usage by others, I just want to create a support Mar 13 23:12:01 and a few examples Mar 13 23:12:23 applications may be different Mar 13 23:13:07 seems to be burning a lot of pins for a nonspecific application Mar 13 23:13:13 you are still thinking of the ice40's right? Mar 13 23:13:22 yes Mar 13 23:13:39 pins should be enough Mar 13 23:13:59 20 gpmc signals is required Mar 13 23:18:51 ds2: I wonder if the SRAM idea is ok, We can use weird interface like fifo or something. Mar 13 23:20:19 IMO - that is too pin heavy Mar 13 23:20:41 IMO - a couple of ice40's wrapped around (or have access to different pins on the am335x Mar 13 23:21:02 so the ice40 can pop in and pre-process stuff as-needed. Worse case, it can pass through the signal Mar 13 23:26:50 Xilinx did the the trick but I do not know the possibilites of ice40 Mar 13 23:27:26 You can set the gpmc timing Mar 13 23:30:37 the ice40's have much fewer cells... it is a smaller FPGA Mar 13 23:44:16 SRAM solutions requires a lot of logic, unfortunately, Mar 13 23:49:15 ds2: it is hard to check, Mar 13 23:49:17 you might want to scope out the size of the ice40's Mar 13 23:54:32 ice40 has 7680 LUTs, on Altera i have 50000LUTs whether Altera LUTs == Lattice LUTs I dont know Mar 14 00:05:07 ds2: thanks, I will think about this, how to solve this problem Mar 14 00:05:15 now I have to go Mar 14 00:05:18 bye **** ENDING LOGGING AT Tue Mar 14 03:00:02 2017