**** BEGIN LOGGING AT Sat Jun 17 03:00:03 2017
Jun 17 14:47:22 <ravikp7> jkridner: Hi, there?
Jun 17 16:01:15 <ravikp7> thetransformerr: Hi, you got a mac? I need help in testing my usb node.js bootloader server on OSX
Jun 17 16:48:48 <pmezydlo> m_w: hi, Could you review me gpmc controller code? I has weird problem concerning 3-state logic.
Jun 17 16:48:54 <pmezydlo> https://github.com/pmezydlo/BeagleWire/blob/develop/BW_Bridge/fpga_bridge_mod/top.v
Jun 17 16:51:23 <m_w> what is happening?
Jun 17 16:51:58 <pmezydlo> fatal error: $_TBUF_ gate must drive top-level output or inout port
Jun 17 16:52:25 <pmezydlo> i'm not sure what is wrong
Jun 17 16:52:45 <m_w> first off use lower case for variables
Jun 17 16:53:03 <m_w> otherwise it is confused with parameters
Jun 17 16:54:20 <pmezydlo> ok
Jun 17 16:54:32 <m_w> the only place I see tristate is in the assign
Jun 17 16:54:35 <m_w> https://github.com/pmezydlo/BeagleWire/blob/develop/BW_Bridge/fpga_bridge_mod/top.v#L27
Jun 17 16:55:00 <pmezydlo> yes
Jun 17 16:55:41 <pmezydlo> when we read data from fpga
Jun 17 17:00:09 <m_w> https://www.reddit.com/r/yosys/comments/6apqig/trouble_with_tristate_io_on_ice40/
Jun 17 17:00:52 <m_w> that seems pretty clunky though
Jun 17 17:01:31 <pmezydlo> hmmm ok I will try
Jun 17 17:03:12 <m_w> pmezydlo: you might want to contact clifford
Jun 17 17:03:56 <m_w> join the #yosys channel and ask over there
Jun 17 17:06:24 <pmezydlo> if i still have problems i will do it
Jun 17 17:07:35 <m_w> okay
Jun 17 17:18:20 <m_w> jic23b: do you need an FPGA board for mentoring?
Jun 17 17:33:06 <m_w> pmezydlo: https://github.com/NetFPGA/netfpga/wiki/VerilogCodingGuidelines
Jun 17 17:35:29 <jic23b> M_w not really. Only backing you up anyway :).
Jun 17 17:35:38 <jic23b> Assuming ti
Jun 17 17:36:15 <jic23b> You survive the summer I will just be a nosy interested bystander!
Jun 17 17:36:18 <m_w> jic23b: okay
Jun 17 17:38:05 <jic23b> How's the pocket bone groupget stuff coming along?
Jun 17 17:38:30 <pmezydlo> it's really weird, Can I use it for whole inout port?
Jun 17 17:53:19 <m_w> jic23b: we are kind of at a crossroads
Jun 17 17:54:15 <m_w> pmezydlo: you would need a instance for each bit
Jun 17 17:55:40 <pmezydlo> ok now make is ok
Jun 17 17:56:46 <jic23> M_w crossroads?
Jun 17 17:57:21 <m_w> differt directions from different parties
Jun 17 17:57:51 <m_w> not really sure how it is all going to play out
Jun 17 17:58:46 <jic23> Fair enough. Fingers crossed then!
Jun 17 17:59:47 <pmezydlo> https://github.com/pmezydlo/BeagleWire/blob/develop/BW_Bridge/fpga_bridge_mod/top.v
Jun 17 18:00:08 <m_w> pmezydlo: but does it work?
Jun 17 18:00:20 <pmezydlo> now looks good, I'm going to test it
Jun 17 18:07:16 <pmezydlo> I managed to reconfigured gpmc setting now gpmc clock has 25MHz
Jun 17 18:22:25 <pmezydlo> m_w: I wrote something to memory and read something else
Jun 17 18:22:45 <m_w> pmezydlo: what memory?
Jun 17 18:23:36 <m_w> ah the little mem that you instantiated?
Jun 17 18:23:44 <pmezydlo> it's memory which is mapped in fpga
Jun 17 18:23:53 <m_w> can you light up the LEDs?
Jun 17 18:24:31 <pmezydlo> no
Jun 17 18:25:09 <pmezydlo> But they should light
Jun 17 18:29:07 <m_w> what does your dt overlay look like?
Jun 17 18:30:27 <pmezydlo> https://github.com/pmezydlo/BeagleWire/blob/develop/DTS/BW-ICE40Cape-00A0.dts
Jun 17 18:31:10 <pmezydlo> ok I know
Jun 17 18:31:20 <pmezydlo> burst mode is turn on
Jun 17 18:31:35 <pmezydlo> for now I don't support it
Jun 17 18:49:52 <m_w> okay
Jun 17 18:49:52 <m_w> got to go for a while, email me if you run into a dead end
**** ENDING LOGGING AT Sun Jun 18 03:00:01 2017