**** BEGIN LOGGING AT Thu Jul 04 02:59:57 2019 Jul 04 04:13:00 Have a look at https://lists.xenproject.org/archives/html/xen-devel/2017-04/msg00991.html this was an attempt to add Tegra Legacy Interrupt Controller support in Xen. Jul 04 04:14:27 You probably can reuse the logic for the crossbar. Jul 04 04:15:28 jkridner ravikp7: Yesterday I sent a mail to the Greybus-Dev Mailing list about the issues, I was subscribed to the mailing list but I didn't receive the mail I sent, I think the mailing list sends only monthly digest to subscribers and we can't expect a reply soon from there Jul 04 06:47:12 @abhishek_:matrix.org: @ds2 i had mailed the output image of signal and problem over the mail Jul 04 11:07:30 Looks like the email is rich text. These lists are plain text only. Jul 04 11:22:50 jkridner: I'll send the mail again in plain text Jul 04 14:37:48 abhishek_ zeekhuge : I did go through the docs again today. I was able to pass raw integers through the device file which the PRU writes to its SRAM in little-endian form (which is okay as the LBBO assembly instruction I use on the other also reads data in the same form.) Jul 04 14:37:56 One more thing I have observed is that while reading the written values through /dev/mem, it causes the PRU core (running rpmsg) to stop and dmesg shows "unconfigured system_events[63-0] = 0x00000000.000c0000" Jul 04 15:39:41 Hmm looks like an interrupt is getting triggered Jul 04 15:40:25 Have you seen the mail @abhishek_:matrix.org Jul 04 15:41:27 I had sent a photo of the output from the logic analyzer Jul 04 15:47:03 abhishek_: yes Jul 04 15:49:33 pranav_kumar : What's the error in the waveform? Jul 04 15:59:02 the data when uploaded to the shift register some time give false signal .For example ,If am loading the data 11100000 then the data should be updated (taking right shift mode in 74hc299) .Then as per the data sheet data output line I/O pins of IC should remain high . But some time it is returning a pulse output on the data line instead of remaining high until the Jul 04 15:59:03 bit get low. I am sending you the image of the correct output through the mail that should be encounter in the above given case. Jul 04 16:04:19 i had sent the mail abhishek_ Jul 04 16:06:29 Extra clock pulse being sent? Jul 04 16:08:36 yes as you can see the data being stored and updated per clock on the output line Jul 04 16:08:52 yes Jul 04 16:10:19 i am just asking why it is generating pulse waveform on the parallel output data line over the pin Jul 04 16:19:46 That's how a shift register works. Jul 04 16:20:14 Your 8 bits are valid only after they have all been shifted out Jul 04 16:21:51 yes , but as you can see that in the previous image that i am sending regular data bits on the DS0 pin to with the regular clock pulse . Jul 04 16:22:07 If there is some data previously loaded in the register, you must clear it? Jul 04 16:22:59 yes i have done that also as you can see that in the start of the image, all the bits are at low mode Jul 04 16:23:26 at the starting of the logic analyzer output Jul 04 16:27:50 DS0 ? I see DSR and DSL pins in the datasheet Jul 04 16:28:54 See the ti datasheet of 74hc299 Jul 04 16:33:02 http://www.ti.com/lit/ds/symlink/cd74hc299.pdf Jul 04 23:41:35 As @hendersa said earlier he will test the circuit and run it on his own bbblack after that he is planning to move with the beaglelogic design and pre requist that you want me to work with in the ean time @abhishek_:matrix.org Jul 04 23:41:57 *mean time **** ENDING LOGGING AT Fri Jul 05 02:59:56 2019