**** BEGIN LOGGING AT Mon Nov 09 03:02:03 2020 Nov 09 17:01:39 Hi all, quick question, is gpmc similar to axi? Nov 09 17:02:16 no Nov 09 17:02:18 no Nov 09 17:02:41 axi connects the cpu to the on-chip interconnect Nov 09 17:02:47 gpmc is an external interface Nov 09 17:03:06 typically used for (nand) flash memory Nov 09 17:03:58 or rather, the controller for an external bus interface (for raw NAND flash and various classic bus protocols e.g. used for NOR flash or sometimes certain external devices like FPGAs) Nov 09 17:04:09 General Purpose Memory Controller Nov 09 17:04:16 what about similarities? assuming constants set for width settings in the axi, does it appear somewhat similar to the gpmc functionalities? Nov 09 17:04:50 AXI is a protocol, GPMC is a peripheral Nov 09 17:05:27 can gpmc implement an isa interface? Nov 09 17:06:18 like, the question you should be asking is what the similarities are between AXI and the sorts of bus protocols driven by GPMC... and the answer is that they perform transfers with similar semantics (though AXI has way more metadata), but that's about where the similarities end Nov 09 17:08:26 since GPMC drives asynchronous protocols with a bidirectional data bus (typically also muxed with the address bus) while AXI is a synchronous pipelined interface Nov 09 17:08:29 hmm, so if I was to upgrade from using gpmc to talk to fpga, up to using an internal axi interface, it will take some re-writing but not too much.. That's what I am thinking nowe. Nov 09 17:09:22 you mean when making an ASIC out of a cpu + fpga design or something? Nov 09 17:09:39 nagh, not that far, using a zynq Nov 09 17:10:11 and it has an AXI interface connected directly to the FPGA fabric? Nov 09 17:10:19 sidenote: devboard are 15$ now on ali, got 2 Nov 09 17:10:26 yup Nov 09 17:10:35 a few it seems Nov 09 17:11:32 it's probably slightly more headache, depending on what you do with it, though I'm sure there are resources available for it Nov 09 17:12:17 like, the AXI interface is synchronous so your logic _must_ be clocked at the AXI interface clock speed... if your functional logic runs at a different clock speed then you'll need some kind of asynchronous fifo to move the data across clock domains Nov 09 17:13:24 yea, should be okay in this design. Thank you guys! Nov 09 17:13:41 and the write-data channel is kinda independent of the command channel Nov 09 17:15:12 so the write-data can be offered on the same cycle as the write-command (which has the address), or lag behind it, or in theory even be offered prior to it (in which case you'd most likely politely decline the data until the associated command is available) Nov 09 17:15:15 I suppose it would end up zynq cpu->/cpu-Fpga axi interface/->(axi->mem-type interface)-> mem-type peripheral Nov 09 17:16:24 I guess you could do that if you're in a hurrry and don't care about performance Nov 09 17:16:57 it all depends on what you're doing with the data I guess Nov 09 17:18:35 there's probably also prefab logic to go from AXI to a simpler bus interface like AHB or even APB Nov 09 17:18:52 which are lower performance but easier to handle Nov 09 17:19:06 opencores is where i've been looking in the past for references. Nov 09 17:22:32 AXI also allows multiple outstanding transactions, so it doesn't have to wait for a command to be acknowledged before sending the next one (though a slave is under no obligation to accept another command while it's still processing one) Nov 09 17:24:12 and later versions also support coherency Nov 09 17:32:30 but you can still talk to a different slave while waiting for the first Nov 09 17:32:45 AXI is a point-to-point interface Nov 09 17:33:14 connecting to multiple slaves requires some form of interconnect fabric Nov 09 17:34:07 and you can interleave accesses to multiple dumb slaves connected to the same interconnect Nov 09 17:34:16 provided the interconnect supports that, obviously Nov 09 17:36:05 yes, typically you'd use some kind of interconnect design tool that lets you configure the initiators and targets you want to connect to your fabric Nov 09 17:37:23 see e.g. https://developer.arm.com/documentation/ddi0475/g/introduction/about-the-corelink-nic-400-network-interconnect?lang=en Nov 09 17:41:33 https://developer.arm.com/documentation/100459/0000/introduction/about-the-corelink-nic-450-network-interconnect?lang=en Nov 09 17:41:42 https://developer.arm.com/documentation/100459/0000/system-ip-tooling/corelink-creator/about-corelink-creator Nov 09 17:44:18 this is ARM's own offering, obviously there are alternatives. There's also something called Open Core Protocol which is like a highly parameterizable bus interface that can encompass most others with little or no glue logic, where the intention is that you specify the characteristics of your module's (master or slave) interface with a formal description and then your interconnect tooling generates ... Nov 09 17:44:24 ...the appropriate logic to plug your component into the interconnect Nov 09 17:45:27 at least that's my understanding of it **** ENDING LOGGING AT Tue Nov 10 00:42:46 2020 **** BEGIN LOGGING AT Tue Nov 10 00:49:26 2020 Nov 10 00:49:50 I want to read your book and review it as a dude that knows some things at times. Does that count? Nov 10 00:49:51 Hey. Something happened. I know it. What happened? All of a sudden, this chat is no longer hosted by some person and is now hosted by another. Tell me! Nov 10 01:03:16 um it happens? Nov 10 01:06:02 Fine. But, but, but. Nov 10 01:27:37 sorry we'll have to replace that Nov 10 01:28:58 "hosted by some person" ? what are you talking about ? Nov 10 01:35:20 @zmatt now but it was kridner. Nov 10 01:35:26 What happened to that fellow? Nov 10 01:35:46 As you can tell, I am out of the loop. Nov 10 01:36:07 ehm, neither of us "host" the chat Nov 10 01:36:36 we're around when we're around Nov 10 01:36:43 Oh. Nov 10 01:36:46 Okay. Nov 10 01:36:50 I was unaware. Nov 10 01:37:06 I mean, I did see the name change. Nov 10 01:37:16 I just did not think to ask yet for some reason. Nov 10 01:37:19 also jason is generally here, just not generally active unless poked Nov 10 01:37:23 name change? Nov 10 01:37:25 Oh. Nov 10 01:37:49 what are you talking about? Nov 10 01:38:01 Yea. When one signs on to this #beagle chat on Freenode, it used to say started by kridner and now it says by @zmatt. Nov 10 01:38:27 Let me sign out real quickly to see what it exactly says. Nov 10 01:38:36 are you talking about the message stating who set topic? Nov 10 01:38:49 because that's just the last person to have modified the channel topic Nov 10 01:39:21 Set by zmatt!~zmatt@blah-blah-blah.nl on Thu blah blah blah. Nov 10 01:39:34 Except where blah is located, it shows other info. Nov 10 01:40:25 It used to say: Set by jkridner@blah-blah-blah.whatever on Fri Jun blah blah. Nov 10 01:40:42 Did you not know this? Nov 10 01:40:46 02:38 <@zmatt> because that's just the last person to have modified the channel topic Nov 10 01:40:51 Oh. Nov 10 01:40:54 Okay. Nov 10 01:40:59 It fooled me. Nov 10 01:41:03 i figured something happened. Nov 10 01:41:27 Mr. Paranoia over here...sheesh. Nov 10 01:41:38 that "something" being some minor change to the channel topic (can't even remember what, I think I swapped two things) Nov 10 01:41:53 like that Nov 10 01:41:59 Right. Okay. It still shows your IP address. Nov 10 01:42:51 It shows that but says Set by zmatt!~zmatt@ on Nov 10 01:43:15 I did not know if you knew or not. Nov 10 01:44:08 yes I know how IRC works Nov 10 01:44:32 Oh. Nov 10 01:44:34 Okay. Nov 10 01:44:43 I was just unaware of what others knew versus what i thought. Nov 10 01:45:50 I figured I would reach out. Nov 10 01:46:30 reach out, outreach. Books? Nov 10 01:48:39 ? Nov 10 01:49:39 What in sammy davonsons' britches are we doing for outreach? Nov 10 01:51:27 who is "we" and why would "we" be doing outreach? I'm just some dude who happens to use beaglebones at work Nov 10 01:52:44 Oh. Nov 10 01:52:55 I figured you were doing things as outreach for the .org. Nov 10 01:53:05 i.e. books or other things. Nov 10 01:54:07 no **** ENDING LOGGING AT Tue Nov 10 02:59:56 2020