**** BEGIN LOGGING AT Wed May 11 23:59:56 2005 **** BEGIN LOGGING AT Thu May 12 00:53:12 2005 **** ENDING LOGGING AT Thu May 12 02:57:26 2005 **** BEGIN LOGGING AT Thu May 12 02:57:26 2005 **** ENDING LOGGING AT Thu May 12 02:58:09 2005 **** BEGIN LOGGING AT Thu May 12 02:58:19 2005 May 12 07:16:19 [g2]: hey May 12 07:16:22 [g2]: you around? May 12 07:18:18 <[g2]> prpplague, hey yeah May 12 07:18:47 [g2]: http://www.dontronics.com/giga.html#io24 May 12 07:20:09 <[g2]> prpplague, Looks SWEET May 12 07:20:19 <[g2]> the ubicom is a rock'n little processor May 12 07:20:39 <[g2]> I've read a bunch about them over that last several years May 12 07:21:12 <[g2]> if it wasn't for the $10K dev setup I'd have had one a while ago May 12 07:21:53 [g2]: this board has spi on all the ports May 12 07:22:26 [g2]: thing this would be an interesting board to use for jtag? May 12 07:24:45 <[g2]> actually they uses the FTDI chips and the 2232C has the JTAG build in as an option May 12 07:25:15 <[g2]> so they could make the same usb-JTAG as ezniosusb except more general May 12 07:25:45 yea thats what i thought as well May 12 07:26:37 <[g2]> thx for pointing out the link May 12 07:29:42 [g2]: np the actual company that makes it is www.elexol.com May 12 07:30:18 <[g2]> like this one http://www.easyfpga.com/ May 12 07:31:46 oh nice May 12 07:31:54 it has the 2232 as well May 12 07:32:10 <[g2]> nod. it's good to go for the Altera May 12 07:32:19 <[g2]> the elexol board has ethernet on it May 12 07:32:52 <[g2]> the ubicom chips are really nice and would be TOTALLY cool to program May 12 07:33:25 * [g2] wonders what the status of the 48 is .... hmmm.... May 12 07:49:55 [g2]: we use alot of the atmel chips, i wonder if icould get our atmel guy to do a board like that May 12 08:17:43 <[g2]> sooner or later will actually get some hw that can talk JTAG to our DUTs May 12 08:17:52 <[g2]> Device Under Test May 12 11:48:08 [g2]: Guess what arrived today... May 12 11:49:41 What I want to know is why did they choose a pinout that is different, and incompatible, with the ARM pinout. May 12 12:00:12 jtag cable ? May 12 12:00:15 digilent? May 12 12:14:02 Yep. May 12 12:14:37 The pinout is different than the header I have. I'm working to make it match. May 12 12:17:34 How do the diligent people expect us to use their cable? Is there normally an adapter? Are there some targets that use their pinout? May 12 12:21:28 beats me, I had to make my own adaptor May 12 12:26:22 jacques: For the diligent? Or did you fabricate the whole thing? May 12 12:27:47 for the digilent. I just had some male header and soldered the wires from the slug to the correct pins, so I can plug the digilent cable into that May 12 12:28:37 Ah. I soldered my header to be a standard ARM pinout. Now, I'm wondering how best to handle this. May 12 12:29:30 just re-arrange the wires :-) May 12 12:30:25 Then, I cannot go back to another adapter if I want to use the one I built. Part of this exercise is to determine if the board I built works properlt. May 12 12:31:12 * beewoolie digs through the parts bin May 12 13:19:39 [g2] the spartan board arrived in the late afternoon May 12 13:49:33 <[g2]> beewoolie, hey! May 12 13:49:42 [g2]: peep May 12 13:49:54 <[g2]> the S3 board has a header to match iirc May 12 13:50:06 Got a diligent. Need to adapt my header to the pinout. May 12 13:50:45 <[g2]> I've tried for about 6 hours the other day to get the Avila to be happy with my other digilent cable and it was not :( May 12 13:50:52 Hmm. May 12 13:51:08 <[g2]> the two VCC connections mentioned pull-ups so I don't know what the deal is May 12 13:51:23 Is there some docs I should have? May 12 13:51:32 As there are no pullups on the slug? May 12 13:51:42 I thought that rwitby uses a diligent. May 12 13:51:46 <[g2]> Same PC that used a DOS floppy to reflash the Avila on the couldn't talk with the digilent cable May 12 13:51:57 <[g2]> no pullup on the SLUG May 12 13:52:14 <[g2]> jacques, used a digilent cable and dyoung too I think May 12 13:52:18 <[g2]> I know jacques did May 12 13:52:30 yep, I used the digilent cable dyoung sent me :-D May 12 13:52:30 Jaque says he wired a header for it. May 12 13:52:33 <[g2]> and that was to recover the one semi-bricked unit May 12 13:53:00 I'm going to see if I have another header to solder up for this. May 12 13:53:50 <[g2]> it was pretty wierd because I'm pretty sure I had the lines all connected properly May 12 13:54:16 <[g2]> I accidently had the reset pin connect on first try and the unit was held in reset :) May 12 13:54:43 <[g2]> the board booted fine, but no JTAG happiness May 12 13:55:14 openwince? May 12 13:55:57 <[g2]> nod May 12 13:57:00 beewoolie: hey d00d May 12 13:57:10 yo. May 12 13:57:30 prpplague: [g2] sent me a diligent which I'm getting hooked up. May 12 13:57:30 beewoolie: are you using rmk's amba-clcd stuff? May 12 13:57:38 beewoolie: lovely May 12 13:57:43 We'll see if it jtag board is working. May 12 13:57:47 * prpplague is working on a lcd for his 79520 board May 12 13:58:06 prpplague: yeah. I use the amba-clcd. There is a patch he put out recently to help with some gray-scale modes. May 12 13:58:29 2.4 or 2.6? May 12 13:58:51 i'm using the 2.4 series right now May 12 13:59:00 testing with 2.4.17 and 2.4.30 May 12 13:59:05 There is already a driver for the 2.4 kernel. Lineo did it. May 12 13:59:11 beewoolie: yea May 12 13:59:14 beewoolie: i've got that May 12 13:59:27 Is there an incompatibility May 12 13:59:28 beewoolie: just gotta get the lcd specs in there and working May 12 13:59:55 beewoolie: mainly that i can't find an example of a gray scale working with pl110 May 12 14:00:14 prpplague: That's the new stuff that rmk put on the list. May 12 14:00:34 Someone has a monochrome display that we needed to get working with a palette. May 12 14:00:45 There were some issues, but I haven't studied the patch. May 12 14:00:55 Supposedly its working fine now. May 12 14:36:11 The Digilent cable is a Xilinx DLC5 compatible cable and is pin compatible with most of the xilinx dev boards. And yes, there is an adapter to go from 6-pin xinlinx to 14(or was it 16) pin ARM. But its kinda pricy. May 12 15:01:55 <[g2]> dyoung, I did not get it to work yet with the 14 pin header on the Avila May 12 15:02:03 <[g2]> I made my own adapter **** ENDING LOGGING AT Thu May 12 15:28:53 2005 **** BEGIN LOGGING AT Thu May 12 15:30:10 2005 May 12 20:48:30 hi.... May 12 20:55:52 my guess is that everyone is really gone. May 12 21:19:52 <[g2]> Don't think so May 12 21:20:22 Hi there. May 12 21:21:08 <[g2]> hello May 12 21:21:17 how goes your project? May 12 21:21:53 <[g2]> I think the pad at R137 is totaly gone and I'm booting the unit to see how the other three connections are May 12 21:22:16 <[g2]> I've got to re-setup the serial because I've got APEX in there May 12 21:23:32 I'm looking forward to using APEX on my slugs. May 12 21:23:44 <[g2]> Althought this project looks like the JTAG part won't be a success, my soldering is improving tremendously May 12 21:23:59 <[g2]> APEX is nice May 12 21:24:13 cool May 12 21:30:51 <[g2]> Ok the slug is a live May 12 21:31:16 <[g2]> so I'm 3 out of 4 on the JTAG pin connections with 4 hoses May 12 21:31:18 <[g2]> hosed May 12 21:31:26 ouch May 12 21:33:15 <[g2]> Ok... Redboot is back May 12 21:34:05 <[g2]> ka6sox-away, you've got JTAG right ? May 12 21:42:41 yes. May 12 21:42:49 on the Slug?\ May 12 21:43:38 <[g2]> nod. May 12 21:44:07 ya May 12 21:44:18 <[g2]> There's just a small issue or two with the irq handler not operating properly on the slug, so Ethernet and USB aren't working properly yet on the slug May 12 21:44:28 <[g2]> the avila board is 100% with APEX May 12 21:45:15 <[g2]> well I'm pretty sure.... Maybe the PCI is still an issue. I'd have to plug in the minipci card, but the regular ethernet is 100% May 12 21:45:25 * [g2] note to self May 12 21:47:43 excellent... May 12 21:48:07 <[g2]> Ok... that's setup here goes May 12 21:52:02 <[g2]> Ok.... 64MB is working, IXP is working... PCI still has an issue which is probably the same as on the slug May 12 21:58:00 <[g2]> OK... PCI is hosed on Avila too with APEX May 12 22:00:07 [g2]: k. May 12 22:00:18 I May 12 22:00:24 m just about to do some exploration. May 12 22:00:27 <[g2]> big paste coming May 12 22:00:40 <[g2]> APEX 1.2.9_64 Meg Avila E1000 PCI issue May 12 22:00:40 <[g2]> When modprobing E1000 with APEX we get May 12 22:00:40 <[g2]> root@avila:~# modprobe e1000 May 12 22:00:40 <[g2]> Intel(R) PRO/1000 Network Driver - version 5.6.10.1-k2 May 12 22:00:40 <[g2]> Copyright (c) 1999-2004 Intel Corporation. May 12 22:00:41 <[g2]> root@avila:~# ifconfig eth2 192.168.1.79 May 12 22:00:43 <[g2]> SIOCSIFADDR: No such device May 12 22:01:10 <[g2]> Note. The PCI *doesn't* come up with APEX 1.2.9 May 12 22:01:17 <[g2]> now here's the Redboot May 12 22:01:33 <[g2]> Redboot and E1000 May 12 22:01:33 <[g2]> root@avila:~# modprobe e1000 May 12 22:01:33 <[g2]> Intel(R) PRO/1000 Network Driver - version 5.6.10.1-k2 May 12 22:01:33 <[g2]> Copyright (c) 1999-2004 Intel Corporation. May 12 22:01:33 <[g2]> PCI: enabling device 0000:00:01.0 (0140 -> 0143) May 12 22:01:34 <[g2]> e1000: eth2: e1000_probe: Intel(R) PRO/1000 Network Connection May 12 22:02:04 [g2]: Ah. That's what I was thinking was going to happen. May 12 22:02:08 The USB is also PCI. May 12 22:02:14 right? May 12 22:02:18 <[g2]> Yeah... That was the point May 12 22:02:29 <[g2]> Same issue May 12 22:02:38 That's where I was planning to start. May 12 22:02:45 Let me take a pass at the PCI registers. May 12 22:02:47 <[g2]> Most Excellent May 12 22:03:33 <[g2]> Note. you can tell because the ehci/ohci interrupts are not visible in /proc/interrupts May 12 22:04:01 There is the other thing which is, IIRC, the PCI may get timing from the GPIO stuff I thought that I was setting that correctly, but maybe not. May 12 22:04:26 Right. I looked at the USB driver and discovered that they're all PCI based. That's why I thought it was the best place to start. May 12 22:04:45 <[g2]> Well the GPIO get setup by the kernel May 12 22:04:48 The thing about PCI, IIRC, is that the devices must be 'detected' or somthing before the kernel gets going. May 12 22:05:08 Are you sure? Usually those lines are configured in the bootloader. May 12 22:05:22 Really, I'd expect PCI to be configured in the kernel, tooo. May 12 22:05:27 <[g2]> yep. I'm pretty sure May 12 22:05:35 <[g2]> I changed them for the Avila kernel May 12 22:05:54 <[g2]> and I changed them from what they were set to in the Slug May 12 22:06:10 <[g2]> I don't know if it's ALL, but most May 12 22:06:15 <[g2]> there are only 16 May 12 22:06:30 Where is that in the kernel code? May 12 22:06:31 <[g2]> it's in the patch files May 12 22:06:35 OK. May 12 22:07:24 you have a avila patchset? May 12 22:08:11 I don't. May 12 22:08:16 <[g2]> dyoung-web, I've had one for a couple months May 12 22:08:24 is it pushed someplace? May 12 22:08:27 <[g2]> ok 8 weeks May 12 22:08:37 <[g2]> nope, I'm the only one using it May 12 22:08:55 Oh. May 12 22:09:20 <[g2]> it's actually only like 200 lines total May 12 22:09:20 I was only curious about that. I'm going to focus on what redboot may be doing to get PCI going. May 12 22:09:24 k. May 12 22:09:41 <[g2]> I'll give it to any of you guys if you want it May 12 22:09:57 <[g2]> beewoolie-afk, I'm focusing on the PCI too. May 12 22:10:04 The thing is, though, now that I think about it. It is possible that the missing piece isn't part of the redboot patch, but part of redboot proper. May 12 22:10:08 np May 12 22:10:15 <[g2]> I've got the boots from both kernels and I'm gonna look at the PCI messages May 12 22:11:22 <[g2]> beewoolie-afk, Ok kernel wonder-boy... My limited understanding was that the kernel was supposed to setup everything except the memory May 12 22:11:48 OK. Then why is PCI not working? May 12 22:12:23 I think that the kernel configures everything that makes sense for itto configure. However, it is *not* responsible for ethernet MAC address, for instance. May 12 22:12:25 <[g2]> I was asking you a general kernel question because you are more familiar with this stuff in general May 12 22:12:35 There are always some things that have to be done outside of the kernel. May 12 22:12:45 I'm not sure there is a hard-and-fast rule. May 12 22:13:07 There isn't anything about PCI in the redboot patch. May 12 22:13:25 What I'll do is look at the registers themselves to see if there is something going on. May 12 22:13:37 <[g2]> I'll check the messages right now May 12 22:13:46 <[g2]> want an email copy ? May 12 22:14:21 Of the kernel message? Actually, what I'd rather see are the /proc entries for the PCI stuff. May 12 22:14:27 If there are any. May 12 22:14:43 <[g2]> I can check May 12 22:15:53 <[g2]> cat /proc/pci May 12 22:15:53 <[g2]> PCI devices found: May 12 22:15:53 <[g2]> Bus 0, device 1, function 0: May 12 22:15:53 <[g2]> Class 0200: PCI device 8086:100e (rev 2). May 12 22:15:53 <[g2]> IRQ 28. May 12 22:15:54 <[g2]> Master Capable. No bursts. Min Gnt=255. May 12 22:15:56 <[g2]> Non-prefetchable 32 bit memory at 0x48000000 [0x4801ffff]. May 12 22:15:58 <[g2]> I/O at 0x1000 [0x103f]. May 12 22:16:00 <[g2]> That's Redboot May 12 22:17:17 Interesting. The other devices don't show? Such as the USB or the ethernet. May 12 22:18:20 <[g2]> that's the avila board May 12 22:18:22 The FSCK'ing redboot protects the PCI registers, so I cannot read them from redboot. May 12 22:18:42 <[g2]> AND.... we are missing something on the PCI setup May 12 22:19:04 <[g2]> because we *don't* get the dmabounce message from APEX but we do from Redboot May 12 22:19:10 <[g2]> PCI: bus0: Fast back to back transfers disabled May 12 22:19:10 <[g2]> dmabounce: registered device 0000:00:01.0 on pci bus May 12 22:19:30 <[g2]> We get the three PCI messages before that, but not the dmabounce May 12 22:19:50 <[g2]> root@avila:~# cat /proc/pci May 12 22:19:50 <[g2]> root@avila:~# May 12 22:19:58 OK. I'll boot the slug, too, to get the info. May 12 22:23:31 <[g2]> Ok.. This routine isn't getting called or the pci_bus_type isn't right May 12 22:23:43 <[g2]> static int ixp4xx_pci_platform_notify(struct device *dev) May 12 22:23:43 <[g2]> { May 12 22:23:43 <[g2]> if(dev->bus == &pci_bus_type) { May 12 22:23:43 <[g2]> *dev->dma_mask = SZ_64M - 1; May 12 22:23:43 <[g2]> dev->coherent_dma_mask = SZ_64M - 1; May 12 22:23:44 <[g2]> dmabounce_register_dev(dev, 2048, 4096); May 12 22:23:46 <[g2]> } May 12 22:23:48 <[g2]> return 0; May 12 22:23:53 Is this in the kernel? May 12 22:23:59 <[g2]> nod. May 12 22:24:10 Hmm. I may have found the code... May 12 22:24:18 <[g2]> line 321 in pci-common.c May 12 22:24:32 It's really short. I'm talking about redboot. May 12 22:24:53 cyg_hal_plf_pci_init(void) May 12 22:25:01 <[g2]> ah... May 12 22:26:01 I was assuming that the code we needed was in the patch. That, it appears, is not the case. May 12 22:26:13 It's going to take some time to pick this all appart. May 12 22:26:25 <[g2]> that may be "standard" Redboot May 12 22:27:06 Yep. It's standard as delivered by Intel to cygnus/redhat. May 12 22:28:09 <[g2]> actually, I can't image a section of code that would be a better candidate than PCI May 12 22:28:20 It still doesn't explain the NPE problem, but, I fear, that may be deeper. Except, that the NPE works on the Avilla, right? May 12 22:28:35 <[g2]> Yup! May 12 22:28:50 OK. Well, I'm not going to fret that yet. May 12 22:28:59 <[g2]> me either... May 12 22:29:03 If we can get USB working, then we're at least making progress. May 12 22:29:24 <[g2]> and that'll round out the Avila most likely May 12 22:30:15 Dont Fret. May 12 22:30:31 <[g2]> I'm not Frett'n at ALL May 12 22:30:43 <[g2]> we are tremendously close May 12 22:30:54 I wish I could help. May 12 22:31:09 <[g2]> after USB on the slug, APEX well boot to usb-ethernet May 12 22:31:21 <[g2]> and we'll have disk access again May 12 22:31:21 I've been occupied hacking/whacking on this packet communication protocol. May 12 22:32:22 I should take a picture of this board actually... May 12 22:32:31 its a very good example how how you dont want to hack a chip in. May 12 22:33:41 Heh. I need to look at my own wiki to remember how to put apex on this board. May 12 22:33:56 <[g2]> dd May 12 22:34:14 <[g2]> dd if=apex.bin of=/dev/mdtblock0 May 12 22:34:15 Hmm. That's a though. May 12 22:34:25 I don't want to clobber all of redboot, though. May 12 22:34:27 <[g2]> THAT's EXACTLY how I do it May 12 22:34:36 <[g2]> before you do... May 12 22:34:47 <[g2]> dd if=/dev/mtdblock0 of=redboot.bin May 12 22:34:54 But if I do that, I'll have to use JTAG to rewrite redboot, now? May 12 22:34:58 s/now/no/ May 12 22:35:04 <[g2]> actually you only need the last 144 btyes (less actually) May 12 22:35:13 Huh? May 12 22:35:14 <[g2]> nope... May 12 22:35:22 <[g2]> You've got serial right ? May 12 22:35:26 Yeah. May 12 22:35:41 <[g2]> APEX boots the linux kernel to and rootfs May 12 22:35:45 I don't have an ethernet cable at the moment. May 12 22:35:46 <[g2]> but only serial works May 12 22:35:50 right. May 12 22:36:02 <[g2]> so login in and dd back to redboto May 12 22:36:03 Is there a serial receive function in the slug rootfs/ May 12 22:36:16 rz? May 12 22:36:23 <[g2]> don't need it May 12 22:36:29 Hmm? May 12 22:36:42 where is redboot? May 12 22:36:44 <[g2]> You're running jffs2 righit ? May 12 22:36:49 Stock. May 12 22:36:59 <[g2]> Oh... Run OpenSlug May 12 22:37:19 Of course. May 12 22:37:53 <[g2]> the first 256K will be the same as everyone elses May 12 22:38:04 Wait...I've got another idea. I think this one is better... May 12 22:38:49 what I really want to do is look at the redboot registers. May 12 22:39:05 err. I want to look at the PCI registers as redboot has set them up. May 12 22:39:55 <[g2]> Can I distract you for a couple minutes ? May 12 22:40:00 You can try. May 12 22:40:18 <[g2]> Ok. That routine only gets call from 1 line in pci-common.c May 12 22:40:56 <[g2]> That routine in turn is called by ixp4xx_setup May 12 22:40:58 You are back to the kernel, right? May 12 22:41:03 <[g2]> nod. May 12 22:41:24 dont forget about the MAC address. that will be the only differnt part. May 12 22:41:25 <[g2]> Like I said earlier, Only 1 of 2 things can be happening May 12 22:41:43 <[g2]> it's less than the last 144 bytes May 12 22:41:45 dyoung: Do you mean to me/ May 12 22:41:52 I saved redboot, first thing. May 12 22:42:04 It's also printed on the board. May 12 22:43:15 ok cool. I wouldnt want you wasting time like I did wondering where my mac address was. May 12 22:45:33 I might be wrong about it being printed on the board. May 12 22:45:50 <[g2]> no there's a sticker on the bottom May 12 22:46:49 Bastards. May 12 22:47:02 good luck gentlemen. I'm hungry. May 12 22:47:02 Usually, those numbers are printed somewhere on the package. May 12 22:47:14 <[g2]> that too May 12 22:48:20 Actually, it is on the packages. May 12 22:48:28 dyoung-web: happy eating. May 12 22:48:37 <[g2]> it's both places May 12 22:48:39 The first part of the number is LKG. May 12 22:49:17 OK. I'm in the money. I've got APEX letting me read the PCI registers. May 12 22:51:11 ... And now its Payback Time. :-) May 12 22:51:29 <[g2]> Got it ! May 12 22:51:34 Hells yeah! May 12 22:51:58 <[g2]> Redboot May 12 22:52:02 <[g2]> PCI: IXP4xx Using indirect access for memory space May 12 22:52:02 <[g2]> PCI: bus0: Fast back to back transfers disabled May 12 22:52:02 <[g2]> dmabounce: registered device 0000:00:01.0 on pci bus May 12 22:52:06 <[g2]> APEX May 12 22:52:24 <[g2]> PCI: IXP4xx is host May 12 22:52:24 <[g2]> PCI: IXP4xx Using indirect access for memory space May 12 22:52:24 <[g2]> PCI: bus0: Fast back to back transfers enabled May 12 22:52:45 <[g2]> besides the dmabounce notice any difference ? May 12 22:53:02 s/dis/en May 12 22:53:11 <[g2]> ding ding ding May 12 22:53:48 Honestly, I'm not following closely enought to see what you are seeing. May 12 22:54:10 <[g2]> honesty is important May 12 22:54:34 <[g2]> PCI: bus0: Fast back to back transfers *disabled* in Redboot May 12 22:54:47 <[g2]> PCI: bus0: Fast back to back transfers *enabled* in APEX May 12 22:54:49 Wanna give me a hint. I'll be clear. My plan is to init the PCI registers and see if that's enough, May 12 22:55:02 Hmm. Interesting default difference. May 12 22:55:21 <[g2]> well the bus doesn't get recognized May 12 22:55:47 <[g2]> well registered is probably a better way of saying it May 12 23:00:37 <[g2]> pci_read_config_word(dev, PCI_STATUS, &status); May 12 23:00:44 <[g2]> I think it's defined in there May 12 23:00:56 <[g2]> if (!(status & PCI_STATUS_FAST_BACK)) May 12 23:00:56 <[g2]> features &= ~PCI_COMMAND_FAST_BACK; May 12 23:04:47 Hmm. Guess what. An uninitialize PCI bus is in big endian mode. May 12 23:04:52 I mean little endian mode. May 12 23:05:50 <[g2]> do we come up in the wrong endian mode get bad config mojo an the bus don't run :) May 12 23:05:59 <[g2]> s/do we/so w/ May 12 23:06:48 <[g2]> The pullups on the expansion bus determine some stuff about the processor May 12 23:07:07 <[g2]> I'm wondering if they are not set properly for the NSLU2 May 12 23:07:54 <[g2]> Although.... it's both Avila and NSLU2 so it's just a non-default config item we need to set May 12 23:07:56 <[g2]> correct ? May 12 23:13:51 Don't know. I'm looking at the default config as described in the documentation. I haven't reflashed yet. May 12 23:13:57 Still coding. May 12 23:27:15 ka6sox: morning. May 12 23:27:26 ka6sox: read the logs? May 12 23:27:52 um...not yet...wazzup? May 12 23:28:11 I think we're onto part of our slug boot problem with APEX. PCI needs to be configured. May 12 23:28:23 I'm almost ready to test some new code. May 12 23:28:31 sweet. May 12 23:28:41 memory is fine? May 12 23:28:53 <[g2]> memory is fine May 12 23:28:59 <[g2]> both 32MB and 64MB May 12 23:29:03 excellent May 12 23:29:11 <[g2]> 64MB on the Avila May 12 23:29:13 AFAIK, memory has been fine for some time, no [g2] ? May 12 23:29:18 good. May 12 23:29:23 so now onto the PCI issues. May 12 23:29:33 <[g2]> go dog go :) May 12 23:29:37 I'm not sure if this is what is in the way of NPE, tho. May 12 23:29:51 <[g2]> that's OK! May 12 23:29:55 <[g2]> One at a time May 12 23:30:16 <[g2]> if it turns out to be a bonus two-for-one we'll take it right ? May 12 23:31:50 what do you guys want/need in a JTAG dongle/debugging tool? May 12 23:32:45 now that I'm done with Dyoung's board I want to get going on the Juice Board. May 12 23:48:12 ka6sox: Um, can I get back to you on that? May 12 23:48:26 sure! May 12 23:55:03 <[g2]> beewoolie-afk, I'm gonna have to bail May 12 23:55:15 <[g2]> THX for all the help tonight May 12 23:55:15 nite [g2] May 12 23:55:16 and I'm just about to test. May 12 23:55:20 Nite. May 12 23:55:41 <[g2]> How long do you think it'll be ? 5-10 minutes ? May 12 23:56:02 While I'm not teasing, I cannot really say. May 12 23:56:17 I'm a pretty carefule fellow with the flashing stuff. May 12 23:56:44 <[g2]> :) May 12 23:57:00 Hmm. Well, the code loads. May 12 23:57:16 <[g2]> what did the PCI messages say ? May 12 23:57:22 Hmm. May 12 23:57:27 <[g2]> is Fast back to back enabled ? May 12 23:57:35 Not good. It didn't boot properly from RAM. May 12 23:57:41 I need to go back and check some things. May 12 23:58:42 No. I set things up the same way as it was being done. The fast back-to-back setting is cleared by default. May 12 23:59:38 <[g2]> so it needs to be disabled **** ENDING LOGGING AT Thu May 12 23:59:56 2005