**** BEGIN LOGGING AT Sun Jun 05 23:59:56 2005 Jun 06 11:54:28 Hello! Jun 06 11:54:59 <[g2]> howdy ! Jun 06 11:55:24 <[g2]> jacques, welcome and check out and check out http://www.openjtag.net Jun 06 11:57:09 <[g2]> jamie out task here is to workout an OpenJTAG mechanism to allow for flash programming and CPU debugging Jun 06 11:57:28 Mmm, HostInterfaces doesn't mention a plain parallel port ;-0 Jun 06 11:57:48 <[g2]> We've been using that now Jun 06 11:58:01 <[g2]> digilentinc sell the $19 parallel cable Jun 06 11:58:26 <[g2]> it currently takes 40-50 minutes with that to reflash the 256K redboot in the NSLU2 Jun 06 11:58:43 Btw, the EZUSB is very nice to work with, and AFAIR doesn't need a dev kit. Jun 06 11:59:02 <[g2]> funny you should mention that :) Jun 06 11:59:14 <[g2]> ep1220, has the FTDI working for both serial and JTAG Jun 06 11:59:45 <[g2]> we'll soon be trying to load the mini-I cache of the IXP420 on the NSLU2 directly with it Jun 06 12:00:16 <[g2]> He was going to be doing some testing this past weekend Jun 06 12:00:38 Does the IXP BSR not have "short cut" switches, to reduce the length for common operations? Jun 06 12:00:53 <[g2]> :) basically there's a special line for loading the i-cache up Jun 06 12:01:02 <[g2]> ep1220, found it in the development manual Jun 06 12:01:26 <[g2]> the mini I cache is only 33bits a word versus 498 for the BSR Jun 06 12:01:51 <[g2]> the test this past weekend was to verify that it could actually be loaded Jun 06 12:04:26 Are you really only targetting the one device so far? I thought openjtag was further along that that, or maybe I'm confusing it with the thing from gEDA. Jun 06 12:07:14 g2: anyway, you asked about FPGA... I'm curious what have you in mind? Jun 06 12:08:00 <[g2]> I think there are two things Jun 06 12:08:43 <[g2]> Ideally we wanted to use an Spartan 3 as our intelligent front-end to the Device-Under-Test Jun 06 12:09:03 (btw, what's your relationship with jtagtools?) Jun 06 12:09:08 Makes sense. Jun 06 12:09:09 <[g2]> however, since we're mostly a bunch of firmware ppl we didn't get to far :( Jun 06 12:09:17 Why, it's just firmware :) Jun 06 12:09:26 <[g2]> speed Jun 06 12:09:50 I mean, what was the problem with the Spartan 3? Jun 06 12:09:55 <[g2]> We currently use jtagtools for re-flashing Jun 06 12:10:25 <[g2]> nothing is wrong with the S3, our FPGA programming skills are what's lacking :) Jun 06 12:10:34 Is openjtag a separate project, and if so why? Or are you the same folks, doing something a bit different? Jun 06 12:11:07 <[g2]> openjtag on sf ? Jun 06 12:11:54 <[g2]> openjtag on SF and this project are one in the same Jun 06 12:12:14 I mean: is openjtag.net a separate project from jtagtools.sf.net, and if so why (since they seem very similar in goals). Jun 06 12:12:51 <[g2]> jtagtools is all sw based with a couple wigglers Jun 06 12:13:16 So you're building better hardware-assisted wigglers? Jun 06 12:13:19 <[g2]> we are looking to do both flashing and JTAG debugging and at high-speed Jun 06 12:13:31 <[g2]> that's the plan Jun 06 12:13:48 So exactly the same as jtagtools' goals, but with hardware-assist to make it faster? Jun 06 12:13:48 <[g2]> but like Mike Dell says "Ideas are easy, execution is hard" :) Jun 06 12:13:54 yeah, i know :) Jun 06 12:13:56 <[g2]> nod. Jun 06 12:14:09 <[g2]> I don't think jtagtools does debugging though Jun 06 12:14:49 I guess the key thing for the _long_ time would be to find the right abstactions for a jtag library, so that debugging/loading flash/connectivity/anything else can go on one side of those abstractions, and simple wigglers/fancy clever wigglers can go on the other side. Jun 06 12:15:33 <[g2]> right. The current design has a CPLD to allow for various voltage levels and connections for different devices Jun 06 12:15:41 <[g2]> there are really two things in play right now Jun 06 12:16:15 <[g2]> 1) A generic device that can adapt to multiple difference voltage levels and pinouts Jun 06 12:16:25 <[g2]> 2) A specific device for the NSLU2 Jun 06 12:16:51 <[g2]> the NSLU2 really being the Xscale IXP4xx line Jun 06 12:17:19 <[g2]> I'm ready to sell reworked units that have a serial and JTAG connection Jun 06 12:17:56 <[g2]> I'm starting with a level shifter for the serial and a parallel for the JTAG but I'd like to switch quickly to a USB device that does both Jun 06 12:18:08 <[g2]> ep1220, may be able to provide such a device Jun 06 12:18:38 What's the USB device made of? Jun 06 12:18:48 <[g2]> and FTDI chip Jun 06 12:18:52 <[g2]> an FTDI chip Jun 06 12:19:31 Ah, EZUSB looks infinitely more versatile than FTDI... am I mistaken? Jun 06 12:20:21 <[g2]> EZUSB uses and FTDI chip last I checked Jun 06 12:20:27 <[g2]> EZUSB uses a FTDI chip last I checked Jun 06 12:20:32 * [g2] is typing way too fast Jun 06 12:20:53 EZUSB is a single chip from Cypress. Do you mean FTDI use an EZUSB? That would be quite nice and reprogrammable :) Jun 06 12:21:28 <[g2]> Ok... I'm wrong about the EZUSB... That's the CY68C013 right ? Jun 06 12:21:32 <[g2]> for $149 ? Jun 06 12:22:10 <[g2]> I confused that with the EZNIOSUSB or EZUSBNIOS which is $99 and uses the FTDI chip Jun 06 12:22:16 it's nothing like that expensive - it's used in cheap consumer parts. Jun 06 12:22:40 <[g2]> The S3 development board from digilent is $99 + $49 for a USB2.0 with a CY68C013 on it Jun 06 12:22:51 AN21XX or CY7C646XX... Jun 06 12:22:55 <[g2]> so the S3 dev kit is a much better deal than the EZUSB Jun 06 12:23:17 <[g2]> ep1220, has reporgrammed the CY68C013 on the USB daughterboard already Jun 06 12:23:30 <[g2]> as he's got the developers kit for that part iirc Jun 06 12:26:21 I was thinking of something like http://www.devasys.com/usbi2cio.htm Jun 06 12:26:30 But yeah, if he's got the dev kit why not? Jun 06 12:27:18 <[g2]> there's a big difference between 12Mbs and 480Mbs Jun 06 12:28:45 Depend how fast your JTAG is going to be. But yes of course; I'm merely illustrating that the EZUSB chips themselves aren't expensive, and from having programmed one they're quite versatile (C programmable). Jun 06 12:29:14 <[g2]> nod. We've talked about lots of different options Jun 06 12:29:25 Looking at FTDI's knowledgebase I see their driver already provides JTAG functions. Well, I guess we can all go home then :) Jun 06 12:29:29 <[g2]> currently there are 3 options on the table Jun 06 12:29:47 <[g2]> 1) the cheap / slow / non-debugging enabled parallel devices Jun 06 12:29:59 <[g2]> 2) The FTDI based device ep1220 is working on Jun 06 12:30:15 <[g2]> 3) The S3 which can be fast but is non-working :) Jun 06 12:30:26 <[g2]> due to lack of FPGA programming Jun 06 12:30:34 <[g2]> not any real HW issues Jun 06 12:31:06 Why can't you debug with (1)? I've certainly debugged boards with a parallel device... Jun 06 12:31:20 <[g2]> We may be able to Jun 06 12:31:34 <[g2]> I haven't looked deeply in the JTAG tools Jun 06 12:32:10 <[g2]> I'm sure the response will be slower than an FPGA Jun 06 12:32:31 <[g2]> I don't know the JTAG interface well enough to know how much it matters Jun 06 12:32:50 Of course, a lot slower. But it makes sense to build sw which has all the same features, but slower, when using the most basic kit. Jun 06 12:33:09 <[g2]> well I think there are 2 worlds Jun 06 12:33:11 With JTAG you pretty much can just write/read the BSL register. Jun 06 12:33:49 (There's a few other kinds, like reading ID, and flipping switches to effectively address a different BSL register) Jun 06 12:33:54 <[g2]> world 1 is generic open source where budget is a huge factor and time is as available Jun 06 12:34:09 <[g2]> BSL or BSR Jun 06 12:34:17 er, yes :) Jun 06 12:34:31 are you in world 1 or 2? Jun 06 12:34:38 <[g2]> world 2 is the professional or semi-professional development world Jun 06 12:34:55 <[g2]> I'm in 2 Jun 06 12:35:15 <[g2]> I've been doing 1 and enjoy it a bunch Jun 06 12:35:20 I'd say that good sw tools can make a big difference. I did some connectivity testing on a large board (the one with 36 FPGAs), where 5/8 of the boards had connectivity problems Jun 06 12:35:22 <[g2]> but it needs a lot more rigor Jun 06 12:35:43 <[g2]> right Jun 06 12:35:44 We had only the most basic parallel port JTAG interface (Altera's design), and I had to write the sw tool. Jun 06 12:36:00 <[g2]> there are lots of ways to slice the pie Jun 06 12:36:06 But I did find some nice ways to optimise the test patterns to converge on the board errors, which we then confirmed with a microscope and fixed... Jun 06 12:36:21 <[g2]> nod. Jun 06 12:36:31 <[g2]> That's what good process is all about Jun 06 12:37:31 <[g2]> I'd like to incorporate JTAG testing in the manufacture / rework of the boards I'll be doing Jun 06 12:38:07 Point being that optimisation of the JTAG sequencing is sometimes possible. I'd like to see/write a nice generic optimisation tool that, given descriptions of the target, and a set of actions to be performed, finds the shortest sequences to do it. Jun 06 12:38:34 <[g2]> I think that's way out Jun 06 12:38:56 Way out stupid or way out in the radical? Jun 06 12:39:08 <[g2]> now way-out in the time horizon Jun 06 12:39:16 <[g2]> it's a good choice Jun 06 12:39:22 <[g2]> but it's a little like talking about AI Jun 06 12:39:35 No, it's more like low-level compiler optimisation. Jun 06 12:39:59 <[g2]> I fully understand. I built compilers for several years Jun 06 12:40:36 <[g2]> I'm just saying that the state-of-the-art at the price/performance level is a long way out Jun 06 12:40:44 Simple stuff, like "I need to output these values on lines A,B,C,D,E,F of chip X and don't care what bits are set for lines G, H and I (so the BSR doesn't have to be fully shifted each time round)" Jun 06 12:41:21 <[g2]> we're coming at the problem from opposite sides Jun 06 12:41:58 <[g2]> you're coming at it from attempting to optimize the operation to a given device which will take lots of device specific knowledge and programming Jun 06 12:42:28 Obviously the most useful bit of hw kit would be something with a chip which can be bought once and reprogrammed as the sw tools advance and new programming strategies become apparent. Jun 06 12:42:34 <[g2]> I'm coming at it from the intelligent device where shifting 498 bits on an FPGA running 50 or 100Mhz isn't a big operation Jun 06 12:43:04 <[g2]> and that reprogramming per device is exactly the reason for using the FPGA approach Jun 06 12:43:48 <[g2]> it's a big performance envelope so for the next year or so makes a decent investement Jun 06 12:43:53 I think it's rare that you need to shift in 498 bits (or the equivalent) on any device that needs a lot of Flash words to be written. Surely every chip would have a short cut for bulk programming. Jun 06 12:44:10 I agree the FPGA approach would be fastest. Jun 06 12:44:32 Ideally, you want to pump bytes at it from the computer, and it has the programming algorithm (or at least some good primitives). Jun 06 12:44:34 <[g2]> which brings us back to the need for the FPGA programmer :) Jun 06 12:44:50 yeah. any money in it? ;) Jun 06 12:44:55 <[g2]> not yet Jun 06 12:45:02 doh, so often the way ) Jun 06 12:45:03 :) Jun 06 12:45:20 <[g2]> I'm just launching the hw company Jun 06 12:45:32 What sort of kit are you selling? Jun 06 12:45:44 <[g2]> I'll be selling a re-worked NSLU2 Jun 06 12:46:40 That think which looks like a miniature air-con unit? :) Jun 06 12:47:13 <[g2]> are you familiar with the NSLU2 at all ? Jun 06 12:47:24 No, not at all, I'm looking at linksys.com now... Jun 06 12:47:55 <[g2]> http://www.nslu2-linux.org/wiki/Info/PhotosOfTheInternals Jun 06 12:48:14 <[g2]> we should add dimensions to that page Jun 06 12:48:16 The stuff about "share music, video files..." reminds me of what I'm working on, which is a media player which _plays_ music and video files over a LAN and doesn't have any storage itself... Jun 06 12:48:37 <[g2]> it's all done with the nslu2 Jun 06 12:48:54 <[g2]> ppl are using it for a video server front-end Jun 06 12:48:58 (based on a sigma designs chip) Jun 06 12:49:25 Does it have audio output? Jun 06 12:49:27 <[g2]> Twonky vision gives away the streaming music and sells the video streaming version for $19 Jun 06 12:49:41 <[g2]> no but it has 2 USB 2.0 ports Jun 06 12:49:58 <[g2]> and 100Mbs ethernet Jun 06 12:50:23 So Twonky's "streaming music" and "streaming video" is intended to stream to...? A PC? A "media adaptor" thingy? Jun 06 12:50:23 <[g2]> ppl have plugged in the USB Sound blaster and other audio usb devices iirc Jun 06 12:50:37 <[g2]> to a media adaptor thingy Jun 06 12:51:05 <[g2]> no pc needed as the nslu2 (slug is our pet name) provides both storage via the external USB 2.0 disk and the streaming capability Jun 06 12:51:09 I ask because some media adaptors are quite capable of USB storage themselves. Jun 06 12:51:22 <[g2]> like the TIVO :0 Jun 06 12:51:23 <[g2]> :) Jun 06 12:51:28 Cheaper stuff than that. Jun 06 12:51:43 There's a "USB hard drive" which happens to have a video output, for example... Jun 06 12:51:56 <[g2]> nod. Jun 06 12:52:03 <[g2]> there's tons of stuff out there Jun 06 12:52:32 Then there's the kit I'm working on which is for commercial displays, and costs about $145/board. Jun 06 12:52:32 <[g2]> this is basically in the <$100 server market Jun 06 12:53:00 Certainly, there should be a market for _generic_ USB/ethernet connecting devices... Jun 06 12:53:14 <[g2]> If I were you, I'd probably use the slug with a usb-vga/tv adapter Jun 06 12:53:26 I.e. something that can go on a LAN where you can put any old USB device on the other side. Jun 06 12:54:25 <[g2]> if there was a usb-vga adapter then slug could act as a thin-client Jun 06 12:54:30 (such as USB printers etc.) Jun 06 12:54:47 <[g2]> ppl already run CUPS on the device Jun 06 12:55:16 <[g2]> our community has more than 3500+ ppl in it Jun 06 12:55:20 <[g2]> it's a pretty active bunch Jun 06 12:55:36 <[g2]> our community web site is http://www.nslu2-linux.org Jun 06 12:55:37 Ah, nice :) Jun 06 12:55:58 <[g2]> I think we've got more developers on the nslu2 than Linksys has employees Jun 06 12:56:02 <[g2]> literally Jun 06 12:56:04 :) Jun 06 12:56:24 Does it have enough RAM to be a thin client? Jun 06 12:56:33 <[g2]> not yet :) Jun 06 12:57:59 Well, unless it's _very_ thin :) Jun 06 12:58:15 So you're thinking of selling h/w programmers to program this device, yes? Jun 06 12:58:43 <[g2]> actual device + programmers dev tools Jun 06 12:58:52 <[g2]> complete development kit Jun 06 12:58:59 <[g2]> it's all ready to go Jun 06 12:59:13 <[g2]> just some final tweaks Jun 06 12:59:27 Now, if only your h/w programmer had both ethernet and a USB port... wouldn't that be handy? :) Jun 06 12:59:57 <[g2]> actually, the NSLU2 can be a front-end for a USB host device Jun 06 13:00:23 <[g2]> so really you can have a full web-serving device controlling the programmer for $80 Jun 06 13:00:38 Does the NSLU2 have enough GPIOs that it could be the programmer itself (with a level converter or so?) Jun 06 13:00:47 I.e. one NSLU2 programming the other... Jun 06 13:00:57 <[g2]> we talked about that Jun 06 13:01:10 It would certainly be very versatile. Jun 06 13:01:32 <[g2]> they could be scraped up, but the bit banging would be relatively slow Jun 06 13:01:49 How slow is it? Jun 06 13:01:56 <[g2]> it's only 266Mhz Jun 06 13:02:15 <[g2]> 32K I-cache and 32K D-cache Jun 06 13:02:18 More importantly: how fast is it safe to bit-bang the JTAG on it? Jun 06 13:02:35 And can the other one approach that speed? Jun 06 13:02:36 <[g2]> 6 to 10 Mhz Jun 06 13:03:12 Next question: does it have any accessible GPIOs that are fast? Jun 06 13:03:38 <[g2]> so at 266Mhz you've go 26 instructions Jun 06 13:03:40 I.e. where writing a memory location or two on the CPU is all it needs... Jun 06 13:03:40 (As opposed to the slow sort of GPIO where I2C or something is needed) Jun 06 13:04:12 <[g2]> I think it sits on the North-side of the amba bus which runs at 133 Jun 06 13:04:18 26 instructions sounds like a lot, if there are usable memory-mapped GPIOs... I don't know much about the chip. Jun 06 13:04:37 <[g2]> I'm saying 266/10Mhz = 26.6 Jun 06 13:04:44 (Bear in mind most of the big-banging is writing, so not delayed the way reading is) Jun 06 13:04:56 jamie: have a look at http://sourceforge.net/projects/jtagpack/ Jun 06 13:05:08 yet another jtag software, hah Jun 06 13:05:42 gee, someone should have a web page listing all the free jtag software :) Jun 06 13:05:55 <[g2]> JMunakra, you've do the debugging for the ARM7 right ? Jun 06 13:06:02 yeah Jun 06 13:06:07 <[g2]> was that via the parallel adapter ? Jun 06 13:06:27 Parallel, and also RS232 direct Jun 06 13:06:44 <[g2]> is speed an issue at all ? Jun 06 13:06:45 but the rs232 module isn't included yet Jun 06 13:07:14 <[g2]> there'd be a monitor program running with the RS232 local to the target under test Jun 06 13:07:33 parallel it's decent, not as fast as the ARM parallel box tho Jun 06 13:07:35 <[g2]> kinda like serial or ethernet GDB Jun 06 13:07:45 but it's not optimized very much Jun 06 13:08:04 no, all the debug logic is on the host Jun 06 13:08:30 the RS232 I was using had just the RS232 wires attached to the JTAG pins, through a level changer Jun 06 13:09:02 <[g2]> so the on-board debugging logic holds up the target processor and if the host takes awhile to respond it's patient Jun 06 13:09:14 <[g2]> it's just that x-fers between the host and target are slower Jun 06 13:09:16 jamie: they should also rate the usability of each of them. Jun 06 13:09:23 <[g2]> like trying to dump 16MB of memory out Jun 06 13:09:41 g2, yes Jun 06 13:10:02 the ARM debug core is totally stable, no matter how slow you clock it :) Jun 06 13:10:22 <[g2]> JMunakra, ah... so you just use RX/TX and the hw flow lines for the jtag connections :) smart. Jun 06 13:10:52 Right. Jun 06 13:11:09 <[g2]> "I love it when a plan comes together" :) Jun 06 13:11:25 I use it with a USB to serial adapter tho, and that makes read operations REALLY slow since you have to wait for the USB, Jun 06 13:11:41 Haven't tried with a "real" serial port. Jun 06 13:11:57 I'm looking at the IXP420's GPIOs and thinking that several of the on-chip ones could be "repurposed" - LEDs and buttons. Jun 06 13:12:02 <[g2]> hmmm... is that a 1.1 adapter ? Jun 06 13:12:09 g2, yes Jun 06 13:12:19 2.0 could be 8 times faster Jun 06 13:12:44 <[g2]> jamie, yes they could be Jun 06 13:12:55 but it's not worth bothering, it will always be dead slow Jun 06 13:13:07 I just didn't have an alternative on my powerbook Jun 06 13:13:25 so I'm awaiting the USB stuff you're working on Jun 06 13:13:38 <[g2]> ep1220, is the man Jun 06 13:13:42 Well, I don't know the chip well enough to know if it's realistic to do a clock in 26 instructions. It _is_ realistic on, say, an 8051 and some other ARM devices. Jun 06 13:13:44 <[g2]> he's got stuff running already Jun 06 13:15:35 with FTDI? Jun 06 13:15:39 <[g2]> nod Jun 06 13:15:48 <[g2]> and with cypress and the S3 Jun 06 13:15:58 <[g2]> the USB portion anyway Jun 06 13:16:04 What's that S3 thing? Jun 06 13:23:24 <[g2]> it's the Spartan 3 FPGA Jun 06 13:23:55 <[g2]> http://www.digilentinc.com/info/S3Board.cfm Jun 06 13:27:58 oh yeah Jun 06 13:29:44 ep1220 has the JTAG programming working with the S3? Jun 06 13:30:28 <[g2]> jamie, he has the USB 2.0 adapter working with the S3 board Jun 06 13:31:41 As in, USB->FTDI->RS232, RS232->S3? Jun 06 13:31:44 Ah. Jun 06 13:31:49 <[g2]> there site got re-org'd and isn't fully right... but look for usb2 on this page http://www.digilentinc.com/products/Accessory.cfm Jun 06 13:32:24 <[g2]> jamie, no.. usb 2.0... S3 FPGA -> Device under test (DUT) Jun 06 13:32:47 I don't see a USB interface on the S3 dev board you mentioned... Jun 06 13:33:14 <[g2]> jamie, the link from 1 minute ago has the USB 2.0 adapter on the page Jun 06 13:33:19 <[g2]> it's $49 is Jun 06 13:33:21 <[g2]> ish Jun 06 13:34:11 Yeah, I see where your leading. The link to the USB 2.0 adapter is broken. Jun 06 13:34:53 <[g2]> it's the cypress CY68C013 iirc Jun 06 13:35:02 yes, it does say that much. Jun 06 13:35:19 It's an EZUSB. Sound like the "accessory" could be quite useful by itself :) Jun 06 13:35:24 <[g2]> so ep1220 has reprogrammed that Jun 06 13:35:43 <[g2]> right at $49 it's no bad :) Jun 06 13:36:18 <[g2]> there's actually a newer dev kit too that as a 500K part, ethernet, and 16MB ram Jun 06 13:36:22 Not bad at all... Jun 06 13:36:26 <[g2]> at $149 to Jun 06 13:36:29 <[g2]> at $149 too Jun 06 13:37:08 An EZUSB should get you some nice JTAG programming optimisations; I forget how fast it is though, and it can't do the USB transfers at the same time as bit-banging. Jun 06 13:37:29 (It's like IDE PIO in that respect) Jun 06 13:38:16 <[g2]> http://www.xilinx.com/products/spartan3e/s3eboards.htm Jun 06 13:38:29 (Correction: it can, but some processing by the 8051 is required) Jun 06 13:39:23 That has a "3-bit, 8-color VGA display port". You have your thin client!! :) Jun 06 13:39:49 <[g2]> the soft-core would be too slow Jun 06 13:39:55 But yes, that kit looks like just the job for.... almost every job! Jun 06 13:41:15 <[g2]> well for a little over $100 I can buy a Soekris 4501 and plug a PCI VGA into is for < $150 is Jun 06 13:41:16 Which soft-core are you referring to? Jun 06 13:41:17 <[g2]> well for a little over $100 I can buy a Soekris 4501 and plug a PCI VGA into is for < $150 ish Jun 06 13:41:36 <[g2]> but it'd be to slow :) Jun 06 13:41:59 <[g2]> I guess you're not aware of the micro-blaze stuff Jun 06 13:42:18 A 500k gate Spartan-3e is fast enough for a lot of things. Yes, I have heard of the Microblaze, I looked into it for an MPEG decoding project. Jun 06 13:42:42 There's a company using Microblaze Linux + their own MPEG-2/4 decoder on a Xilinx, to make a nice video player. Jun 06 13:42:43 <[g2]> they've been running uClinux on it for at least 8-9 months Jun 06 13:43:26 <[g2]> From what I've seen the Sigma chips are quite popular Jun 06 13:43:38 I'm working on a Sigma chip job now. Jun 06 13:43:41 <[g2]> I've been looking for some device running Linux Jun 06 13:43:47 They're not very good about giving out information :( Jun 06 13:43:50 <[g2]> because we'd reflash em Jun 06 13:44:07 <[g2]> I heard they had a Linux port Jun 06 13:44:13 Do you want to buy some boards with Sigma chips on? I know someone who might sell them :) Jun 06 13:44:50 Yes, they do. I think (but am not sure) that maybe they _only_ run Linux on their current chips. Jun 06 13:44:51 <[g2]> I think a Linux kit would make lots of sense Jun 06 13:45:01 There are proprietary drivers for some of the video bits, though. Jun 06 13:45:38 <[g2]> Depending on the proprietary drivers there may be lots of ppl interested Jun 06 13:45:55 Linux version 2.4.26-em86xx-uc0-sigma (s970404@sr2s2.kinposh.com.cn) (gcc version 2.95.3 20010315 (release)) #1 .» 4.. 11 13:40:51 CST 2005 Jun 06 13:46:02 <[g2]> IMHO the whole myth TV thing is technical wanking Jun 06 13:46:40 <[g2]> Somebody should be making a sigma design for like $250 that'd kick Myth-TV's ass Jun 06 13:46:42 I'm on a job which was using a VIA-based PC, but we dropped it after deciding it was too expensive, and are now working out a custom board using the sigma chip. Jun 06 13:46:56 <[g2]> Nod. Jun 06 13:47:04 <[g2]> the C7 looks real interesting though Jun 06 13:47:25 * [g2] has a wait-and-see attitude or a "show-me" with new hw Jun 06 13:47:40 I think the VIA stuff is technically very good in general, but it's let down by their software support. Jun 06 13:48:34 The poor folks over at unichrome.sf.net are producing video drivers for it, and they have no end of hassle. Jun 06 13:48:35 <[g2]> I've heard that the release the CN400 stuff Jun 06 13:48:37 <[g2]> lately Jun 06 13:48:48 <[g2]> It'll be interesting to see how things play out Jun 06 13:49:27 <[g2]> My take on the market is there following: Jun 06 13:49:30 Yes. It's not the most stable stuff, but it can do HDTV and apparently is good at it when it works. (And the opensource stuff outperferms VIAs own code despite depending on reverse-engineering and a bad attitude from VIA) Jun 06 13:49:37 <[g2]> 1) <$150 US devices Jun 06 13:49:44 <[g2]> 2) 150-350 Jun 06 13:49:46 In the end, though, we went with sigma because of power consumption too... Jun 06 13:49:58 Price, and lack of a fan. Both good things. Jun 06 13:49:59 <[g2]> 3) 350-550 (mini-itx) Jun 06 13:50:03 <[g2]> 4) PCs Jun 06 13:50:06 <[g2]> 5) Custom Jun 06 13:50:09 Depends on the mini-itx. Some are <$200. Jun 06 13:50:27 <[g2]> exactly Jun 06 13:50:41 With sigma we've ended up with a board that's just about <$150, and I'm quite happy with the peripheral bits crammed onto the board. Jun 06 13:50:59 <[g2]> It's running Linux ? Jun 06 13:51:04 yes Jun 06 13:51:39 It's a bit dismaying to ask "can you run it in _this_ video mode please..." and get back a response from our SDK supplier saying "sorry, we don't have the manual for the chip and the driver from sigma has modes limited to the following table..." Jun 06 13:51:54 So a mixed bag software development wise. Jun 06 13:52:33 <[g2]> this is where the open-source army would just reverse or figure out a bunch of stuff Jun 06 13:52:38 But we have a very friendly supplier, and that's worth a million small problems. Jun 06 13:52:49 Yes, maybe that will happen ;-) Jun 06 13:53:12 hmm? Jun 06 13:53:21 <[g2]> morning sunshine :) Jun 06 13:53:21 We tried to get a sigma dev kit... but their sales person in EU didn't answer any of our calls :( Jun 06 13:53:27 someone said army and reverse engineer..... Jun 06 13:53:41 <[g2]> dyoung, say hi to Jacmet Jun 06 13:53:46 <[g2]> dyoung, say hi to jacques Jun 06 13:53:52 <[g2]> dyoung, say hi to jamie Jun 06 13:53:55 <[g2]> DOH! Jun 06 13:54:03 <[g2]> damn tab completion Jun 06 13:54:04 :-) Jun 06 13:54:11 Hi jamie. Jun 06 13:54:19 so we're lucky to have found an intermediary who can get the chips and make the board. Jun 06 13:54:29 Hi dyoung :) Jun 06 13:55:25 <[g2]> dyoung is one of the very early core dev's on the nslu2-linux project Jun 06 13:55:46 pleased to meet you Jun 06 13:56:03 <[g2]> jamie is developing a sigma chip based media player, right ? Jun 06 13:56:13 I'm an alien that g2 is trying to recruit for some poorly specified and underpaid task ;) Jun 06 13:56:15 <[g2]> we were talking OpenJTAG Jun 06 13:56:42 Cool! Jun 06 13:56:51 that's right. Jun 06 13:56:53 I basically dont know what the hell I'm doing. Jun 06 13:56:54 <[g2]> ahh... but the the rewards from working code and first tracks are "priceless" :) Jun 06 13:57:29 Well, g2, I'm happy for you to be my agent for speaking to the bank then :) Jun 06 13:57:31 <[g2]> dyoung, what's that quote ? "Beaten paths are for beaten men" ? Jun 06 13:57:59 well, what landed my in this space was mentioning that I'd like to make opensource hw.... I really meant silicon, mind you. Jun 06 13:58:15 I'm all for opensource hardware. Jun 06 13:58:15 Mainly because it's an unbeaten path that's positively desparate to be beaten... Jun 06 13:58:30 sw is so 1990s. Jun 06 13:58:38 exactly! Jun 06 13:58:53 besides, after the first 20 years coding, you start to want something a bit different ;) Jun 06 13:59:24 the future is in open hardware that can be synthesized on FPGA or Hard Silicon; IMHO. Jun 06 13:59:52 I notice a lot of talk about this board and that board from various web sites... is nobody able to assemble own boards yet? Jun 06 14:00:34 <[g2]> jamie, my path is the following Jun 06 14:00:39 dyoung: I agree very much, except that I'm not sure if we'll be making hard silicon first, or if some other tech will arrive which is better, such as the plastic electronics being prototyped or something else Jun 06 14:00:43 <[g2]> 1) re-work and dev kits Jun 06 14:00:50 <[g2]> 2) build custom boards Jun 06 14:00:57 <[g2]> 3) build custom chips Jun 06 14:01:03 ah, a business plan :) Jun 06 14:01:15 <[g2]> I think the future is on the integration of the system Jun 06 14:01:17 [g2] thanks for that, I feel a sense of communion with you now. Jun 06 14:01:33 <[g2]> I've got to execute on 1) first :) Jun 06 14:01:37 I feel like I want to cut the crap and go to step 4) manufacture the chips ourselves Jun 06 14:02:06 <[g2]> last I checked that was a $1-2M deal to start with Jun 06 14:02:19 clearly, step 4a is "find a cheaper way" Jun 06 14:03:04 <[g2]> I think dreaming is great and actually doing something is even better Jun 06 14:03:08 yes, I agree. Jun 06 14:03:53 <[g2]> jamie do you do a lot of board layout ? Jun 06 14:04:23 <[g2]> and do you following the opencores stuff seriously ? Jun 06 14:04:26 no, I've never done a board layout (though I've worked on large schematics, and left someone else to go insane doing the layout ;-) Jun 06 14:04:39 for (4a), I think we need some alien technology. Jun 06 14:04:44 <[g2]> jamie, I meant design, not PCB layout Jun 06 14:05:02 So you mean schematics, yes? Jun 06 14:05:13 No, I don't, but I have done. Jun 06 14:05:24 some, not a lot. Jun 06 14:05:45 <[g2]> ok, thx! Jun 06 14:07:36 dyoung: It sounds like a dream but I'm serious, and I think (4a) is crackable in the next 5 years. Jun 06 14:08:08 if we decide to crack it... Jun 06 14:08:17 I find myself unable to predict future technologies anymore, so youre probably right. Jun 06 14:08:34 But dammit, I want my flying car. we were su pposed to have them my now! Jun 06 14:18:15 dyoung: imho we need the political change that's accompanying open source more than we need the tech... Jun 06 16:37:24 <[g2]> jamie, are you around ? Jun 06 16:37:47 yes Jun 06 16:38:16 but not for much longer Jun 06 16:38:19 <[g2]> just one comment, I know a guy designing a chip right now Jun 06 16:38:36 <[g2]> so if you wait 5 years you might be 4 years too late Jun 06 16:38:43 <[g2]> and it's not me Jun 06 16:38:53 <[g2]> I'm doing the board thing now Jun 06 16:39:00 <[g2]> just FYI Jun 06 16:40:15 <[g2]> jamie, nice chatting hope to see you around :) Jun 06 16:40:37 Hmm. I know quite a few chips get designed and fabbed through academic connections (on small qtys), that there's folks designing a 3d graphics core to be fabbed and sold.. are you referring to one of the publicised projects? Jun 06 16:41:06 <[g2]> no Jun 06 16:41:22 ok, you'll have to fill me in on the mystery sometime... Jun 06 16:41:29 cheerio! Jun 06 16:41:34 <[g2]> cheers Jun 06 16:42:45 (btw i'd be _very_ keen to do a chip design myself if I knew a way to get it fabbed..., should you have any ideas or info in that direction) Jun 06 16:43:20 <[g2]> I don't. I wanted to do some SOC and I couldn't figure out how to get it done Jun 06 16:43:21 <[g2]> :( Jun 06 16:43:57 Right now, small scale SOC is best done with FPGAs. But it's not cheap for a big S. **** ENDING LOGGING AT Mon Jun 06 23:59:56 2005