**** BEGIN LOGGING AT Fri Oct 21 03:00:00 2005 Oct 21 06:03:37 <[g2]> prpplague hey CONGRATS! Hack-a-day ! Oct 21 06:04:38 <[g2]> http://www.hackaday.com/entry/1234000420064224/ Oct 21 06:18:13 [g2]: yea thanks, i appreciate it Oct 21 06:18:30 [g2]: :) Oct 21 06:49:57 <[g2]> prpplague that's cool, I know you've been hacking on that for awhile ! I'm glad to see someone recognized the value Oct 21 06:52:03 whee, my uart works. kind of. Oct 21 06:56:04 [g2]: thanks, it was mainly done as a learning excercise Oct 21 06:56:12 [g2]: but it turnout pretty cool Oct 21 06:56:25 [g2]: my son was watching videos with it last night Oct 21 06:56:46 [g2]: hehe, now if i could get this s3c2410 board booting......... Oct 21 06:58:36 prpplague: what board? Oct 21 07:12:22 lennert_: new custom board Oct 21 07:13:15 ah Oct 21 07:13:24 kyllikki and fluffy are the s3c2410 experts Oct 21 07:13:44 not sure if fluffy is on freenode, but kyllikki should be Oct 21 07:15:06 lennert_: yea fluffy is on #mtd Oct 21 07:15:31 lennert_: kyllikki usualy hangs on #debian-arm Oct 21 07:15:40 yeah Oct 21 07:16:52 hehe Oct 21 07:17:00 ./me has been on irc for a long time Oct 21 07:17:03 * prpplague has been on irc for a long time Oct 21 07:17:06 ek Oct 21 07:17:09 can't type Oct 21 07:17:37 me.. since 1999 but i only started using it for tech stuff round 2003 Oct 21 07:17:42 i met my wife on irc :) Oct 21 07:17:53 lennert_: hehe cute Oct 21 07:18:59 crappy connection today Oct 21 07:19:01 lots of rain Oct 21 07:19:05 16:18 -!- prpplague [n=billybob@216.110.117.19] has quit ["Client Exiting"] Oct 21 07:19:12 you seem to have quit yourself? Oct 21 07:19:37 lennert_: yea had to restart was getting lag Oct 21 07:19:47 lennert_: my adsl has been crappy this morning Oct 21 07:20:22 more to hit in about an hour Oct 21 07:50:52 <[g2]> wilma troubles ? Oct 21 08:17:08 [g2]: naw, tropical wave coming through Oct 21 08:17:24 [g2]: http://image.weather.com/images/sat/caribsat_720x486.jpg Oct 21 08:18:14 [g2]: if you follow the left side of the weather channel logo straight up you will see barbados Oct 21 08:18:17 [g2]: right between the two storms Oct 21 08:18:43 prpplague, as in Tsunami? Storm Surge? Cosmic Rays? Oct 21 08:19:58 ka6sox: hehe i didn't make up the names, tropical wave is a description of a heavy rain that moves through an area like a waves Oct 21 08:21:43 ka6sox: http://www.weatherquests.com/services/knowledge/glossary/?code=t Oct 21 08:23:50 i had doing sdram calcs because every proc has different nomenclature for the options Oct 21 08:23:56 s/had/hate Oct 21 08:25:40 prpplague, ah... Oct 21 08:51:20 gotta love ftdi: i told them about a deadlock problem, and they told me to add an extra delay :/ Oct 21 13:27:25 okay, i want to shift a 8-bit register 1 bit to the right Oct 21 13:27:30 i did: Oct 21 13:27:36 blah(6 downto 0) <= blah(7 downto 1); Oct 21 13:27:42 blay(7) <= '0'; Oct 21 13:27:45 is there any better way? Oct 21 13:28:07 that's what i found on various sites when looking for an example on how to do this Oct 21 13:28:24 a different example used a 'for' construct, iirc Oct 21 13:28:45 'for' will just turn into something like: Oct 21 13:28:49 blah(6) <= blah(7); Oct 21 13:28:57 blah(5) <= blah(6); Oct 21 13:28:58 etc Oct 21 13:29:02 so, that's basically the same Oct 21 13:29:05 yep Oct 21 13:29:13 okay, thanks for your help Oct 21 13:31:43 <[g2]> vmaster in VHDL and Verilog all the statements in a block could happen in parallel right ? Oct 21 13:32:16 [g2]: yeah, and they would Oct 21 13:32:43 [g2]: so writing "a <= b; c <= a;" will load the old value of a into c Oct 21 13:33:04 [g2]: assuming you've clocked it Oct 21 13:33:10 <[g2]> yeah my qustion was about the latching of the values Oct 21 13:33:43 <[g2]> and if it's clocked or fully asynchronous Oct 21 13:34:06 if you write "if clock='1' and clock'event then a <= b; end if;" then it'll be clocked Oct 21 13:34:22 what helped me understanding this is: what could the hardware look like Oct 21 13:34:56 if you clock something, there'll be a flip-flop Oct 21 13:35:24 yeah Oct 21 13:35:47 if you clock something and check for some other condition, it can write the flipflop's enable input with that condition Oct 21 13:35:56 s/write/wire/ Oct 21 13:36:05 heh, yeah Oct 21 13:36:23 i learned that lesson when my gated-clock (which seemed natural to me) just broke every timing :) Oct 21 13:37:03 my first clock divider had two processes: one process to count to 1000, and another process to output '1' if the counter was < 500 and '0' otherwise Oct 21 13:37:18 since the < 500 comparison wasn't clocked, it broke horribly Oct 21 13:37:44 i.e. when the counter would go from 511 to 512, it would temporarily appear as 0, and the output would go 1 even though it shouldn't have Oct 21 13:37:52 heh Oct 21 13:38:18 i love that vhdl/verilog programming forces you to think about such issues Oct 21 13:39:29 yep, unfortunately, i have only little time now... Oct 21 13:39:57 master study is taking more time than i expected Oct 21 13:40:45 what do you study? Oct 21 13:41:23 computer science, i've finished by diploma (4 years, between bachelor and master) a few months ago, now i'm doing a 1-year add-on for a masters degree Oct 21 13:43:00 i'm enrolling into EE Oct 21 13:45:59 is there any way of building a reset generator? Oct 21 13:46:08 is there maybe some system reset line that one can tap in some way? Oct 21 13:46:48 (i can just assume that flipflops always initialise as zero and build a reset generator that way, but that's ugly.) Oct 21 13:47:46 on xilinx devices there's a global buffer for reset Oct 21 13:48:00 okay, what's that called? Oct 21 13:48:10 (if you happen to know) Oct 21 13:49:18 BUFGSR Oct 21 13:49:23 but it's no available on all devices Oct 21 13:49:29 not sure on which, the libraries guide should have it Oct 21 13:49:39 thanks much Oct 21 13:57:24 hey Oct 21 13:57:30 shreg <= shref (6 downto 0) & SI; Oct 21 13:57:36 that's a shift register Oct 21 13:57:42 (from the xilinx xst docs) Oct 21 13:57:48 so apparently, & is bitwise concatentation Oct 21 13:57:51 concatenation Oct 21 13:57:54 ah, nice Oct 21 14:02:45 the 'sll' operator is apparently shift logical left Oct 21 14:02:48 DI <= DI sll 1; Oct 21 14:03:01 there's also srl and rol Oct 21 14:03:26 reading the docs is actually paying off for once :P Oct 21 14:05:04 mhh, the sxx operators wouldn't work for me Oct 21 14:05:15 not sure if i made syntax mistakes Oct 21 14:05:20 weird Oct 21 14:05:44 <[g2]> test vectors are your friend right ? :) Oct 21 14:05:53 <[g2]> rofl Oct 21 14:06:13 gaaaaah Oct 21 14:06:18 elsif state = 12 and state <= 19 then Oct 21 14:06:22 of course it doesn't work Oct 21 14:06:42 * lennert_ does s/=/>=/ and tries again Oct 21 14:15:56 okay, i'm out - cya Oct 21 14:19:48 cya Oct 21 14:33:15 what is a 'registered' output? a buffered output? Oct 21 14:35:45 usually. **** ENDING LOGGING AT Sat Oct 22 02:59:56 2005