**** BEGIN LOGGING AT Wed Dec 07 02:59:56 2005
Dec 07 05:55:24 <[g2]> ep1220 png
Dec 07 05:55:38 <ep1220> [g2]: morning
Dec 07 05:55:46 <[g2]> yes it is :)
Dec 07 05:56:10 <[g2]> so the hardware boads are ready to go ?
Dec 07 05:56:13 <[g2]> boards
Dec 07 05:56:20 <ep1220> yes
Dec 07 05:56:48 <[g2]> they do both serial and JTAG ?
Dec 07 05:56:58 <ep1220> yes
Dec 07 05:57:22 <[g2]> from Windows, Linux, both ?
Dec 07 05:57:39 <ep1220> Windows: both no problem
Dec 07 05:57:51 <ep1220> Linux: needs some tinkering to get both at the same time
Dec 07 05:58:11 <ep1220> when the serial driver is installed it allocs both channels
Dec 07 05:58:23 <ep1220> so the JTAG soft can not access
Dec 07 05:58:30 <[g2]> this is all USB 1.1 stuff right ?
Dec 07 05:58:46 <ep1220> full speed only
Dec 07 05:58:56 <[g2]> 12mbs
Dec 07 05:58:59 <ep1220> EEPROM decides if the device detects as 1.1 or 2.0
Dec 07 05:59:18 <[g2]> nod
Dec 07 05:59:21 <ep1220> yes 12mb, on the JTAG theoretical max is 6Mbps
Dec 07 05:59:42 <[g2]> I'm thinking about the logging speed of the USB transactions in Linux
Dec 07 05:59:54 <[g2]> I think USB debug will dump them out
Dec 07 06:00:17 <ep1220> logging speed ?
Dec 07 06:00:30 <[g2]> so for debugging the driver I think we can capture all the transactions
Dec 07 06:00:38 <[g2]> that makes for simple debugging
Dec 07 06:00:47 <ep1220> on windows this was no problem
Dec 07 06:00:52 <[g2]> possibly even play back
Dec 07 06:01:27 <ep1220> i do not think there is much need for debugging at the USB packet level
Dec 07 06:02:08 <ep1220> The serial + JTAG problem is more a VID/PID issue + what the driver uses.
Dec 07 06:02:34 <ep1220> The EEPROM has fields to tell the OS which channel to use for serial and which for parallel/JTAG
Dec 07 06:02:44 <ep1220> seems ftdisio does not care ...
Dec 07 06:03:33 <ep1220> but that one is OS (iirc)
Dec 07 06:03:46 <[g2]> Ok what are you planning on selling your board for ?
Dec 07 06:04:46 <[g2]> to  end users
Dec 07 06:05:07 <ep1220> I can sell the PCB alone at 14EUR
Dec 07 06:05:21 <[g2]> I'm looking for a JTAG solution for Loft users
Dec 07 06:05:30 <ep1220> for complete boards I have not decided on an enduser price
Dec 07 06:05:34 <[g2]> how big is it ?
Dec 07 06:05:42 <ep1220> 80 x100 mm
Dec 07 06:05:52 * [g2] runs for the meter stick
Dec 07 06:06:08 <ep1220> divide by 25,4 to get inches
Dec 07 06:06:44 <ep1220> if volume is OK, it might make a SMD only board
Dec 07 06:07:03 <ep1220> s/it/I/
Dec 07 06:07:39 <[g2]> well you've got the design right ?
Dec 07 06:07:46 <ep1220> my reasoning. without software there will not be many customers ;-)
Dec 07 06:07:55 <ep1220> so i made this kit first
Dec 07 06:07:55 <[g2]> it'd just be a BOM and PCB change
Dec 07 06:08:26 <ep1220> I must add the parts from the module to the PCB
Dec 07 06:08:45 <ep1220> so it is not totally trivial
Dec 07 06:09:05 <ep1220> also can not be soldered by hand
Dec 07 06:09:39 <bullet> well, it can, but you sure don't want to ;)
Dec 07 06:10:17 <[g2]> it doesn't make much sense except for POC or debugging
Dec 07 06:10:28 <ep1220> POC ?
Dec 07 06:10:35 <[g2]> Proof-of-Concept
Dec 07 06:10:43 <[g2]> sorry
Dec 07 06:10:49 <ep1220> you mean te handsoldering ?
Dec 07 06:10:53 <[g2]> yeah
Dec 07 06:11:04 <[g2]> I was replying to bullet's comment
Dec 07 06:11:19 <ep1220> in my experience one edns up debugging the soldering joints ;-)
Dec 07 06:11:23 <ep1220> ends up
Dec 07 06:11:32 <[g2]> :)
Dec 07 06:12:53 <ep1220> If one commits to approx. 100 units, it is no problem to first get a few manufactured professionally to start with
Dec 07 06:16:54 <prpplague> getting assembly for something with that level of complexity is pretty cheap and easy
Dec 07 06:17:39 <[g2]> hey prpplague 
Dec 07 06:18:01 <ep1220> prpplague: we are talking about directly soldering the FTDI to a PCB, that one is 0.5 fine-pitch
Dec 07 06:18:06 <ep1220> 0.5mm
Dec 07 06:18:38 <prpplague> yea, doing that by hand would be tricky to do with that kind of qty
Dec 07 06:18:56 <prpplague> ep1220: could try using a toaster oven technique
Dec 07 06:18:57 <vmaster_> regarding jtag and serial at the same time: linux > 2.6.13 allows you to unregister drivers from userland
Dec 07 06:19:16 <vmaster_> so you just let ftdi_sio take both endpoints, and then unregister it from the jtag endpoint
Dec 07 06:20:17 <[g2]> vmaster unregister the second endpoint so it could be used for serial ?
Dec 07 06:21:25 <vmaster> mhh, well, if you want don't want to mess around with a vid/pid of your own you could just use ftdi's default. in that case, ftdi_sio would use both for serial, so you unregister ftdi_sio from the endpoint you want to use as jtag
Dec 07 06:21:54 <vmaster> with linux 2.6.15 or possibly .16, it's going to be possible to assign drivers to vid/pid from userspace
Dec 07 06:22:45 <[g2]> hotplug ?
Dec 07 06:23:01 <vmaster> hotplugging uses the vid/pid entries from the driver
Dec 07 06:23:09 <ep1220> another option: add code to ftdi_sio so it checks what the EEPROM says ..
Dec 07 06:23:16 <ep1220>  but just unregistering to me seems easier
Dec 07 06:23:30 <vmaster> heh, yeah, good luck getting a change for your jtag interface upstream ;)
Dec 07 06:24:21 <[g2]> if I understand you guys, the ftdi serial driver takes both channels and one would need to be unregistered to be used as JTAG
Dec 07 06:24:29 <ep1220> nod
Dec 07 06:24:51 <vmaster> but that only works with linux >= 2.6.13
Dec 07 06:24:52 <ep1220> at the moment i unload the entire ftdi_sio module
Dec 07 06:26:28 <[g2]> so are you guys more interested in this known working solution or a FPGA based one ?
Dec 07 06:27:22 <vmaster> i couldn't get more than an effective tck rate of ~1mhz from the ft2232c
Dec 07 06:27:41 <vmaster> so a fpga based solution is still on my list
Dec 07 06:28:10 <vmaster> but for now, i'm happy with the ft2232c
Dec 07 06:28:24 <[g2]> vmaster do you program verilog/vhdl ?
Dec 07 06:29:02 <vmaster> heh, i tried it, but due to a lack of time didn't finish my initial design for the parallel port
Dec 07 06:29:25 <[g2]> I've got a Black Dog that is cool
Dec 07 06:29:54 <[g2]> I think it's got most everything we need on it except a MMC to JTAG Header converter
Dec 07 06:30:37 <[g2]> They cost $199 for the 256MB flash and 64MB ram on board, run Debian Sarge in the PPC hardcore on the Xilinx inside
Dec 07 06:30:49 <[g2]> and have USB 2.0
Dec 07 06:31:31 <[g2]> So I'm weight cost/schedule against building ep1220's device, or getting devices for members here and just moving to something like that
Dec 07 06:32:22 <[g2]> I've talked to the company that makes them and later in 2006 is may be possible to OEM them
Dec 07 06:33:12 <[g2]> I think ep1220 has done tremendous work and is the leader of getting things done
Dec 07 06:33:17 <[g2]> and working
Dec 07 06:33:51 <ep1220> [g2):  I  want a JTAG with level-shifters and protected outputs
Dec 07 06:33:51 <[g2]> I'm ready for JTAG and in a couple months my board users will be ready too
Dec 07 06:34:15 <prpplague> "board users" ?
Dec 07 06:34:23 <vmaster> those that buy his loft, i guess
Dec 07 06:34:24 <[g2]> ep1220 a dongle can have that
Dec 07 06:34:27 <ep1220> so would have to add a similar board like mine, except with an FPGA in place of the FTDI
Dec 07 06:34:34 <[g2]> yes Loft's are shipping
Dec 07 06:34:54 <ep1220> But then You pay 199$ for the USB IF.
Dec 07 06:35:13 <vmaster> the blackdog seems a bit over-sized
Dec 07 06:35:19 <ep1220> For that price You can an ARM + network module easily.
Dec 07 06:35:29 <ep1220> yu can *add*
Dec 07 06:35:31 <prpplague> [g2]: Loft ? 
Dec 07 06:35:41 * prpplague is out of it
Dec 07 06:35:44 <[g2]> ep1220 $199 is for the USB IF, a Hardcore, FPGA, Fingerprint scanner, dev kit ....
Dec 07 06:35:52 <[g2]> yeah
Dec 07 06:35:56 <[g2]> prpplague 
Dec 07 06:36:10 <[g2]> http://www.giantshoulderinc.com/hw-4533
Dec 07 06:36:14 <vmaster> mhh, i wonder how they can sell the blackdog for so little money
Dec 07 06:36:32 <[g2]> http://www.giantshoulderinc.com/ab3/case.jgp
Dec 07 06:36:38 <[g2]> doh! that jpg
Dec 07 06:36:51 * prpplague looks
Dec 07 06:36:54 <ep1220> [g2]: but what use is this other stuff in a JTAG IF ?
Dec 07 06:36:55 <[g2]> vmaster $20 in venture funding
Dec 07 06:37:00 <[g2]> $20M
Dec 07 06:37:26 <[g2]> they are going after the enterprise market this is just reducing their development costs
Dec 07 06:37:40 <bullet> [g2]: how much will your loft cost?
Dec 07 06:38:03 <[g2]> dev kits are selling for $325 board and PS, and $349 with case
Dec 07 06:38:19 <[g2]> that's a 533Mhz industrial temp board
Dec 07 06:38:49 <bullet> ui, 4x mini-pci? quite a lot
Dec 07 06:39:00 <[g2]> ui ?
Dec 07 06:39:05 <prpplague> interesting board
Dec 07 06:39:13 <[g2]> actually 3 miniPCI
Dec 07 06:39:15 <bullet> ui! :) that's german for, wow
Dec 07 06:39:24 <[g2]> :)
Dec 07 06:39:39 <[g2]> you can also get a 4 MiniPCI no USB version
Dec 07 06:39:48 <[g2]> it'll be a little cheaper
Dec 07 06:40:23 <[g2]> bullet it also does passive POE and can handle 4 radio cards for full duplex dual channel wifi
Dec 07 06:40:32 <[g2]> in multiple bands or not
Dec 07 06:40:37 <[g2]> all run from the POE
Dec 07 06:40:52 <bullet> nice nice
Dec 07 06:40:58 * [g2] is going to target the backhaul space with full distro
Dec 07 06:41:15 <[g2]> I'm bringing up the Aetheros and IPW2200 cards now
Dec 07 06:45:06 <[g2]> well trying anyway :)
Dec 07 07:25:56 <prpplague> [g2]: since you have $20M can i borrow about $50? hehe
Dec 07 07:27:12 <lennert> oooh.. we get to submit our wishlists to [g2] ? :)
Dec 07 07:28:52 <prpplague> "dear santa, please bring me a 4 channel digital oscope, weller reflow over, and last but not least a bdi2000 , thanks, davey"
Dec 07 07:29:11 <vmaster> mhh, the blackdog guys have the 20m, right?
Dec 07 07:30:50 <lennert> i want a scope like that, a good fluke, a good lab power supply, a v2p board with gige, and a ton of other crap
Dec 07 07:43:29 <prpplague> hehe, i've had the money for a good oscope a couple times, hehe, then i went to the nudie bar
Dec 07 07:43:40 <lennert> hmmmmm :)
Dec 07 07:43:44 <lennert> such a waste!
Dec 07 07:43:51 <prpplague> hehe
Dec 07 07:44:53 <lennert> i'm thinking about buying a heap of stuff for myself as 'investment'
Dec 07 07:47:13 <prpplague> yea, me too
Dec 07 07:47:26 * prpplague just crawling out of debt due to a nasty divorce
Dec 07 08:07:51 <[g2]> prpplague I don't have $20M
Dec 07 08:08:07 <[g2]> if I had $20M all you guys would have more hw than you'd know what to do with
Dec 07 08:08:43 <[g2]> Realm Systems got like $20M in two rounds of VC financing (actually I think it's 17)
Dec 07 08:10:20 <[g2]> You know we should just make an apdapter that plugs into the CF slot on the Loft
Dec 07 08:10:35 <[g2]> then we could just drive stuff over the Expansion Bus
Dec 07 09:01:12 <[g2]> lennert you've still got your S3 ?
Dec 07 09:54:06 <ka6sox> Vulture Capitalists
Dec 07 11:00:18 <prpplague> ~seen beewoolie
Dec 07 11:00:24 <purl> beewoolie <n=beewooli@florence.buici.com> was last seen on IRC in channel #openjtag, 69d 23h 55m 6s ago, saying: 'Right.  I get that part.  My block flashing code is way faster than the byte flashing.'.
Dec 07 11:00:33 <prpplague> ~seen beewoolie-afk
Dec 07 11:00:34 <purl> beewoolie-afk <n=beewooli@206.124.142.26> was last seen on IRC in channel #openjtag, 14d 20h 28m 57s ago, saying: 'prpplague: I found the problem...'.
Dec 07 11:00:44 <prpplague> ~seen beewoolie-oncrack
Dec 07 11:00:45 <purl> i haven't seen 'beewoolie-oncrack', prpplague
Dec 07 11:01:03 <prpplague> feel lucky
Dec 07 11:23:57 <lennert> [g2]: yeah, i still have my s3
Dec 07 11:24:10 <lennert> prpplague: so you _have_ seen him on crack before?
Dec 07 11:24:30 <prpplague> lennert: hehe 
Dec 07 11:24:36 <prpplague> lennert: no, just being silly
Dec 07 11:24:46 <lennert> :)
Dec 07 12:19:54 <[g2]> ep1220 vmaster lennert are you guys interested in doing JTAG for the GESBC-9312-sx boards ?
Dec 07 12:20:05 <[g2]> http://www.glomationinc.com 
Dec 07 12:20:23 <[g2]> I think I might have a sponsor that will support our efforts with hw
Dec 07 12:21:49 <[g2]> ep1220 I think that board would work with your device and 20-pin arm
Dec 07 12:58:34 <vmaster> [g2]: i already have a arm7/arm9 debugger that works with wigglers and ft2232c
Dec 07 12:58:43 <vmaster> it just needs those finishing touches i never find time for
Dec 07 12:59:45 <[g2]> vmaster Ok will the debugger work with ep1220 device ?
Dec 07 13:00:09 <vmaster> yeah, all the logic is inside the ft2232c
Dec 07 13:02:04 <[g2]> vmaster there's a usb driver and then some stuff on the ft2232c for the JTAG translation
Dec 07 13:05:30 <lennert> [g2]: i'm always interested in more hardware =p
Dec 07 13:05:57 <lennert> [g2]: this board actually looks pretty cool.  do you have one of them, do you know what the max gpio clock frequency is?
Dec 07 13:07:52 <[g2]> lennert dunno about the max gpio
Dec 07 13:08:03 <[g2]> I know the chip family is the Cirrus 93xx
Dec 07 13:10:09 <[g2]> lennert I don't have one but I will soon :)
Dec 07 13:10:48 <lennert> okay
Dec 07 13:11:02 <lennert> i'll send you a test proggy to try out what max clock rate you can get
Dec 07 13:12:49 <[g2]> lennert how are you going to measure ?
Dec 07 13:13:02 <[g2]> I think I've got a 200Mhz 9302 around somewhere
Dec 07 13:14:06 <[g2]> or are your FPGA skillz so great that I can hookup a couple wires and just see the output on the VGA screeen ?
Dec 07 13:14:18 * [g2] would bow down to the MAN!
Dec 07 13:14:51 <lennert> no, you just check how long an MMIO write takes
Dec 07 13:15:04 <lennert> do a couple million in a loop
Dec 07 13:15:39 <[g2]> ok, you're saying that the CPU will stall on the write and you know the timing
Dec 07 13:15:42 <lennert> btw, writing a frequency counter for the sp3 with vga output wouldn't even be all that hard, i think...
Dec 07 13:15:52 <lennert> indeed, if you do the mapping uncached
Dec 07 13:16:14 <lennert> once the 'gpio unit' (or whatever unit it is) has received the write, it'll toggle the gpio pretty quickly
Dec 07 13:16:23 <lennert> it's the path to the 'gpio unit' that takes the most time
Dec 07 13:16:23 <[g2]> lennert that wasn't a total joke
Dec 07 13:16:52 <lennert> the frequency counter, you mean?  in fact, i think i can whip one up pretty quickly ;)
Dec 07 13:17:25 <[g2]> can you do colored DIOs too ?
Dec 07 13:17:33 <lennert> DIO ?
Dec 07 13:17:38 <[g2]> Digital I/O
Dec 07 13:17:44 <lennert> how do you mean, colored?
Dec 07 13:17:58 <[g2]> Green = 0, Red = 1, Yellow = float
Dec 07 13:18:17 <lennert> i'm not sure whether you can detect high-impedance state
Dec 07 13:18:44 <[g2]> it'd probably be a driven line
Dec 07 13:18:47 <lennert> you _could_ partial reconfig the fpga 20 times a second to toggle between pullup and pulldown, and then detect a 10Hz square wave as high impedance..
Dec 07 13:19:07 <lennert> but that has issues of itself :)
Dec 07 13:19:22 <[g2]> no, I'm thinking simple feed back for GPIOs
Dec 07 13:19:53 <lennert> making a simple vga output saying which line is high and which is low, that should be not very hard
Dec 07 13:20:02 <[g2]> I know
Dec 07 13:20:24 <[g2]> not for the FPGA Master :)
Dec 07 13:20:38 <lennert> [g2]: how's your vhdl foo, then?
Dec 07 13:20:52 <[g2]> non-existant
Dec 07 13:20:59 <lennert> any plans?
Dec 07 13:21:20 <lennert> or ambitions?
Dec 07 13:21:38 <[g2]> I've had plans for a couple years but kernel hacking, toolchains, board building etc has gotten in the way
Dec 07 13:21:46 <lennert> i see..
Dec 07 13:21:50 <lennert> yeah, too many plans, i know that..
Dec 07 13:21:59 <[g2]> I've followed the uBlaze ML for the last couple years
Dec 07 13:22:11 <lennert> oh
Dec 07 13:22:16 <[g2]> but now Hardcores are relatively cheap
Dec 07 13:22:24 <lennert> any posts from a guy @liacs.nl ?  he's a nut.
Dec 07 13:22:33 <[g2]> i.e. blackdog
Dec 07 13:23:03 <lennert> blackdog is $199, right?
Dec 07 13:23:07 <[g2]> yeah
Dec 07 13:23:21 <lennert> so what does it have, again?  sdram?
Dec 07 13:23:34 <vmaster> lennert: why is the gpio frequency important for you?
Dec 07 13:23:42 <vmaster> philips lpc's are nice in that regard
Dec 07 13:23:45 <[g2]> 64MB SDRAM, 256MB flash, PPC, MMC slot, fingerprint scanner
Dec 07 13:23:53 <[g2]> hardcore
Dec 07 13:23:56 <[g2]> runs sarge
Dec 07 13:24:06 <lennert> all vhdl available?
Dec 07 13:24:10 <[g2]> yeah
Dec 07 13:24:14 <[g2]> well most
Dec 07 13:24:26 <[g2]> I haven't really looked at the package
Dec 07 13:24:46 <[g2]> they have that 50K grand prize
Dec 07 16:50:19 <[g2]> vmaster around ?
**** ENDING LOGGING AT Thu Dec 08 02:59:59 2005