**** BEGIN LOGGING AT Wed Jan 04 02:59:57 2006 Jan 04 14:14:17 doodz Jan 04 14:15:07 yo Jan 04 14:15:08 d00dz Jan 04 14:15:13 wh4t'5 up Jan 04 14:15:16 y0 Jan 04 14:15:34 I've been reading about BSDL and such. Jan 04 14:15:48 I've written a parser for bsdl that works, but I'm sad to realize that it is of littl euse. Jan 04 14:16:12 It is handy, tho, for getting IDCODES for different CPUs. Jan 04 14:17:46 the latest word on the website is february now for the S3e Jan 04 14:18:05 BSDL, well.. i mostly just read BSDL myself Jan 04 14:18:25 is that like reading sanskrit? Jan 04 14:18:52 sanskrit is harder because it isn't machine parseable. Jan 04 14:20:38 :) Jan 04 14:27:27 lithuanian is in the same family as sanskrit, apparently Jan 04 14:27:52 interesting Jan 04 14:33:36 http://direct.xilinx.com/bvdocs/appnotes/xapp476.pdf <<< BSDL file information for S3 Jan 04 14:33:50 * beewoolie is checking Jan 04 14:36:56 Access to their bsdl files requires a login and I'm feeling lazy. Jan 04 14:37:17 I think that lennert might have some of them. Jan 04 14:38:59 I have plenty to work on in the mean time. It looks like no one uses the boundary scan for debug or flash programming. Instead, there are alternative interfaces on each core to make things more efficient. Jan 04 14:39:34 what cores are you talking about? Jan 04 14:39:50 So far, the arm7/9 and the xscale. Jan 04 14:40:23 You've used the ixp stuff, so you know what I'm talking about. Jan 04 14:41:00 mhh, i have only arm7/arm9s Jan 04 14:41:10 but of course, you're right Jan 04 14:41:31 Really? I thought that you were loading programs into the xscale icache. Jan 04 14:41:45 ep1220 did, iirc Jan 04 14:41:51 Ah. Jan 04 14:42:42 if you're interested in arm7/9 debugging have a look at openocd.berlios.de ;) Jan 04 14:42:53 k. Jan 04 14:43:53 Is that your project? Jan 04 14:44:10 yeah Jan 04 14:45:15 Cool. I'll take a whack at it when I get the 2232 running. Jan 04 14:46:38 I received confirmation that the parts have shipped. Jan 04 14:47:17 vmaster: btw, what parts do you have? I'm wondering about the specific manufacturer's part numbers. Jan 04 14:48:52 mhh, i had someone build the device for me, i'm not so much a hardware guy Jan 04 14:49:07 I mean, what CPUs are you using to test the JTAG software. Jan 04 14:49:13 ah Jan 04 14:49:31 a philips lpc2294, a atmel at91rm9200 and a hynix hms30c7202 Jan 04 14:49:39 K. thanks. Jan 04 14:49:43 arm7tdmi-s, arm920t and arm720t Jan 04 15:12:14 the bsdl files come with ise, and i have a copy of ise 7.1i Jan 04 15:12:38 i can tar up all the bsdl files i have? Jan 04 15:13:31 lennert: I'dd appreciate whatever you can make available. Jan 04 15:13:55 ok, hang on Jan 04 15:14:14 The BSDL parser makes it easy to add/recognize a part from the JTAG idcode Jan 04 15:14:31 Drag and drop. Jan 04 15:15:36 yeah, that's a plus Jan 04 15:15:57 it would be nice to have a database of (idcode, IR length, max TCK rate) parameters somewhere Jan 04 15:16:22 as you can't really 'ignore' an unknown device in a scan chain if you don't have at least the IR length Jan 04 15:16:53 figuring ir length out is easy Jan 04 15:17:43 bits [1:0] have to be b01 Jan 04 15:18:11 but the other bits can be b01 too :) Jan 04 15:18:40 mhh... trying to remember what that algorithm looked like Jan 04 15:18:59 are you confusing with determining the length of the scan chain, maybe? Jan 04 15:19:10 mhh... maybe Jan 04 15:19:34 all IDCODEs are 32 bits but it's easy to spot an invalid IDCODE Jan 04 15:19:43 so you can determine the number of devices in the chian Jan 04 15:19:57 but the IR length of an unknown device.. well, i don't know an algorithm for that Jan 04 15:20:10 beewoolie: http://www.wantstofly.org/~buytenh/ise_7.1i_bsdl.tar.bz2 Jan 04 15:20:38 * beewoolie loves wget Jan 04 15:21:25 1225 bsdl files for your parsing pleasure Jan 04 15:21:28 lennert: AFAICT, there isn't a way to guess the length of the instruction register. Jan 04 15:21:39 ~praise lennert Jan 04 15:21:39 All Hail lennert! Jan 04 15:21:44 All hail lennert! Jan 04 15:21:56 ~lart ka6sox-office Jan 04 15:21:56 * qbot drops a truckload of VAXen on ka6sox-office Jan 04 15:21:57 * purl blasts ka6sox-office to oblivion with a kamehameha wave Jan 04 15:22:06 lol Jan 04 15:22:13 rotfl Jan 04 15:23:58 Hey, a new bit type. Jan 04 15:24:14 bit type? Jan 04 15:24:28 yeah, I'd not seen a 'buffer bit'. Jan 04 15:27:56 <[g2]> anyone got an md5/sha1 on that bsdl tarball ? Jan 04 15:28:55 md5: 72e56f861f09e9ea97c5980a2ee5d82f Jan 04 15:29:03 sha1: 33db0a1ec606b506efc90ca4c6385f530a60b181 Jan 04 15:29:42 <[g2]> thx Jan 04 15:31:29 That's what I've got. Jan 04 15:33:02 <[g2]> me too :) Jan 04 15:33:06 http://www.ipfabrics.com/pdf/Double_Espresso_Datasheet.pdf Jan 04 15:33:10 that would make a nice buildd Jan 04 15:33:12 Yeah, yeah. Wise guy. Jan 04 15:34:57 lennert: what the heck is that thing for? Cracking crypto? Jan 04 15:35:42 routing and firewalling and stuff Jan 04 15:35:51 but you can of course use it for building debian packages too ;) Jan 04 15:36:03 Hmm. that's an idea. How spendy? Jan 04 15:36:08 <$300? Jan 04 15:36:13 dunno. i guess around $4k. :) Jan 04 15:36:55 With QEMU is it really worth spending that much? Jan 04 15:37:04 A fast AMD64 can build a lot of packages. Jan 04 15:37:05 it's certainly not worth spending that much :) Jan 04 15:37:24 I wonder if they'll sample one of them... Jan 04 15:37:37 or give me one to port linux 2.6 ;p Jan 04 15:38:24 <[g2]> hm looks insteresting Jan 04 15:38:29 radisys was kind enough to send me one of their boards Jan 04 15:57:18 okay, and now i'm trying to find the HDLC specs (ISO 3309 and ISO 4335) Jan 04 15:57:27 all these standards keep referencing each other Jan 04 15:57:31 it's like a conspiracy Jan 04 15:57:58 all I.xxx ITU standards reference each other, so you get all I.xxx standards Jan 04 15:58:12 then, the most interesting I.xxx standards reference Q.xxx standards Jan 04 15:58:26 so you get all Q.xxx standards Jan 04 15:58:38 those reference even different ITU standards, plus a bunch of ISO standards Jan 04 15:58:47 now i bet those ISO standards will reference ANSI standards Jan 04 15:58:54 and the ANSI standards will reference ETSI standards Jan 04 15:59:02 and before you now, you're broke and still without the info you need Jan 04 15:59:11 s/now/know/ Jan 04 16:00:32 <[g2]> lennert did you see that PCI-E DDR RAM disk card ? Jan 04 16:00:42 nope? Jan 04 16:01:08 <[g2]> http://www.ddrdrive.com Jan 04 16:02:12 is that an fpga? Jan 04 16:02:22 <[g2]> 8G DDR2 with PCI-E card, bootable and external power supply Jan 04 16:02:33 <[g2]> I think it's "upgradable" so maybe Jan 04 16:03:47 looks like a nice little board Jan 04 16:04:07 but i'd rather plug that memory in my mobo Jan 04 16:04:41 <[g2]> I think that 8G card and your ixp2350 PCI-E card you'd have one hell of a exterior BGP routers eh ? Jan 04 16:05:45 for an eBGP router, 1G is more than enough, really :) Jan 04 16:06:05 hang on Jan 04 16:06:06 <[g2]> only 1 stick then and room for growth :) Jan 04 16:06:36 this router now has 557813 routes.. that's about three times a full internet routing table Jan 04 16:06:53 'top' shows that the routing protocol daemon (rpd) takes up 180M of memory Jan 04 16:07:03 PID USERNAME PRI NICE SIZE RES STATE TIME WCPU CPU COMMAND Jan 04 16:07:03 2583 root 2 0 182M 179M kqread 90.9H 6.20% 6.20% rpd Jan 04 16:07:14 this is a juniper M7i Jan 04 16:11:23 lennert: I've been able to get some standard from the local university. It's worth a look. Jan 04 16:12:03 i work at the local university :) Jan 04 16:17:28 <[g2]> hey beewoolie are you doing any JTAG hacking ? Jan 04 16:17:41 [g2]: That's the flavor of the week. Jan 04 16:17:54 [g2]: I'm investigating how to do it efficiently. Jan 04 16:18:11 I should have a working 2232 board in a week or so. Jan 04 16:18:52 <[g2]> are you planning on using it for debugging or flashing ? Jan 04 16:20:36 Both. I've determined how to make the IXP do some nice debug tricks. The idea would be to create something that can do both. Flash is important, but it isn't the only thing. In fact, I don't use it much any more since APEX works. Jan 04 16:21:05 But, getting apex into memory still requires something. JTAG is preferrable if I can make it fast. Jan 04 16:21:12 <[g2]> are you using the PMU Jan 04 16:21:25 i couldn't get the ixp2000 pmus to work (there are 2 pmus) Jan 04 16:21:26 PMU? I've not seen that acronym. Jan 04 16:21:42 <[g2]> I think it's the PMU performance management unit Jan 04 16:21:58 I don't know that one. Sounds like xscale. Jan 04 16:22:15 There are special registers in the IXP scan chain that give us good access to the core. Jan 04 16:22:34 In fact, the xscale seems to be easier than arm7/9, but I just haven't found the right piece yet. Jan 04 16:22:40 <[g2]> are you just talking about the normal debug regs ? Jan 04 16:23:01 yeah, PMU is an xscale thing, although the intel PMUs are CHAP type Jan 04 16:23:15 I remember that someone, I believe ep1220, has loaded instructions into the Icache. I know how to do this on the xscale. I'm seeing if I can get this functionality on the arm7/9. Jan 04 16:23:28 beewoolie: IXP debug is done easiest by icache access, right? Jan 04 16:23:29 right Jan 04 16:23:54 [g2]: There are special registers in the JTAG scan chain that are only accessible from JTAG. Some are accessible internally, too, through the CP15. Jan 04 16:24:09 lennert: Icache is super slick and should be efficient. Jan 04 16:24:38 It turns out that the arm7/9 cores have a short scan chain for fast access to the data and address busses. Jan 04 16:24:50 <[g2]> LDIC is for loading the I-cache right ? Jan 04 16:24:54 I don't yet know how well this will support debug. Jan 04 16:24:56 [g2]: Yeah. Jan 04 16:25:14 <[g2]> that's what ep1220 got working Jan 04 16:25:15 There is the added hassle that we cannot load immediate operands that are larget than 8 bits. Jan 04 16:25:31 But, I think I have a way to mitigate that. Jan 04 16:26:31 <[g2]> are you going to be debugging the slug ? Jan 04 16:26:59 xscale is important. Jan 04 16:27:45 <[g2]> are you thinking ixp or pxa or obth Jan 04 16:28:01 The only hassle with starting with xscale is that I have only one with jtag and it's running a file server at the moment. Jan 04 16:28:20 [g2]: I don't know if there is much difference from the JTAG POV. Do you have a PXA device? Jan 04 16:28:25 <[g2]> that's why you need a Loft :) Jan 04 16:28:43 I thought my invoice was backordered. Jan 04 16:28:53 Besides, I thought that the loft was IXP? Jan 04 16:28:59 i have two PXAs, actually, but i don't think they have accessible jtag ports Jan 04 16:29:03 i.e., two gumstix 400 boards Jan 04 16:29:27 lennert: Are you sure? Last I read, the gumstix advertised the JTAG port. Jan 04 16:29:48 i have a really ancient model? Jan 04 16:30:07 * lennert checks Jan 04 16:34:14 i _think_ i have the model that came before the waysmall basix 400ax Jan 04 16:34:18 i do have the mmc slot Jan 04 16:34:29 and the hirose connector Jan 04 16:34:39 but i don't think the jtag lines are brought out to a connector on mine Jan 04 16:34:45 so i probably need a daughterboard or something Jan 04 16:35:40 JTAG isn't mentioned on their expansion board page, http://www.gumstix.com/spexExpnsion.html Jan 04 16:37:10 It's on the hirose connector. Jan 04 16:37:23 http://www.gumstix.org/tikiwiki/tiki-index.php?page=I%2FO Jan 04 16:37:34 yeah, i saw that Jan 04 16:37:41 but it's not brought out on any of the boards Jan 04 16:37:49 so i'd have to solder tiny wires to the connector myself Jan 04 16:37:54 which is just right out :) Jan 04 16:38:27 [g2]: to answer your question, I doubt that there will be many changes between the two. I'll find out as soon as I get a PXA board to test with. Jan 04 16:38:42 <[g2]> beewoolie are you going to be driving the 2232 with usb ? Jan 04 16:38:47 Yeah. Jan 04 16:38:57 I'm assembling the board that ep1220 designed. Jan 04 16:39:04 <[g2]> nod Jan 04 16:39:13 <[g2]> You've got a circuit board ? Jan 04 16:40:22 [g2]: 2 Jan 04 16:40:34 [g2]:2 Jan 04 16:40:46 [g2]: me 2 Jan 04 16:41:02 [g2] me 2 too Jan 04 16:41:06 [g2]: 2 me 2 me 2 2222222222 Jan 04 16:41:06 <[g2]> is that so you can send 1 to the soldered-challenged ? :) Jan 04 16:41:08 :) Jan 04 16:41:34 *cough* and I still wonder where that loft board is... Jan 04 16:41:50 <[g2]> I thought you wanted a case Jan 04 16:42:02 Is it still on order? Jan 04 16:42:15 <[g2]> the Loft board or the cases ? Jan 04 16:42:25 <[g2]> I get 5 more tomorrow Jan 04 16:42:33 I don't know. Last you told me there weren't any cases. Jan 04 16:42:53 <[g2]> I've got 2 cases not and 5 more tomorrow Jan 04 16:43:27 <[g2]> I"ve got 15 boards but I think 7 are sold Jan 04 16:43:41 Well, the question that my pal asked is whether or not it is better to get the cirrrus based board since it is a more open platform. Jan 04 16:43:46 <[g2]> There's 100 in the queue Jan 04 16:44:05 100 sold, or on order? Jan 04 16:44:11 <[g2]> built Jan 04 16:44:39 <[g2]> there may be 100s on order on 1000s in seveal months Jan 04 16:45:11 <[g2]> but we'll see how it turns out Jan 04 16:45:31 <[g2]> I think Jan 15th is next batch of Glomation boads Jan 04 16:45:52 I feel like I've got too many choices. Jan 04 16:46:06 just in time for jan 16th when i come home Jan 04 16:46:20 you are in .lt? Jan 04 16:46:27 yeah, right now i am Jan 04 16:46:42 ah cooolies Jan 04 16:47:04 You guys heard of IEEE 1500? Jan 04 16:47:37 nope Jan 04 16:47:40 Looks a lot like JTAG, but it's for SoCs and multi-core devices. Jan 04 16:48:14 so that's not IEEE 1532? Jan 04 16:48:27 http://www.arm.com/pdfs/IEEE1500_compliant_wrapper_cell_defensive_pub.pdf Jan 04 16:48:42 * lennert grumbles... IEEE.. standards conspiracies Jan 04 16:49:41 it looks kind of odd at first sight Jan 04 16:53:07 They also have something that professes to give JTAG functionality with a two-wire interface...they say one wire, but the diagrams show two wires. Jan 04 16:53:46 GND doesn't count ;) Jan 04 16:53:56 * lennert is waiting for a vendor to advertise 0-wire parts Jan 04 17:00:08 It lowers costs. After all, these bit-serial interfaces are an improvement, too. Jan 04 17:27:34 <[g2]> anythoughs on bittorrent versus emule ? Jan 04 17:28:03 emule is a stupid name? Jan 04 17:28:26 I think so. Jan 04 17:30:00 beewoolie: hey Jan 04 17:30:05 beewoolie: whats cookin? Jan 04 17:30:22 me 2 me 2 me 2 me 2 yipee!! Jan 04 17:30:34 beewoolie: ? Jan 04 17:30:54 I started with the Internet late in life. I'm just catching up. Jan 04 17:30:56 beewoolie is cooking? Jan 04 17:31:06 oh Jan 04 17:31:08 the aol-phase Jan 04 17:31:16 prpplague: hey man. Been working on some JTAG stuff. Jan 04 17:31:34 BTW, I asked Jun about the wiggler code you sent. He claims ignorance. Jan 04 17:31:38 'aol phase', actually. (i keep connecting noun parts..) Jan 04 17:32:14 prpplague: I'll have a 2232 working in a week or so. Jan 04 17:32:49 beewoolie: yea i got your email just been swampped with a big high dollar legacy project Jan 04 17:32:58 beewoolie: should be free'd up mid of next week Jan 04 17:48:07 I.430 specifies that for ISDN S/T cables.. "..the difference in the resistance of conductors of a pair shall not exceed 6% or 60Mohms, whichever is greater." Jan 04 17:48:21 60 Mohms, eh.. Jan 04 18:28:36 [g2]: you know stuff about BRI ISDN, what is the Activation bit used for? it's described in the frame format but i don't see it referenced anywhere in I.430. Jan 04 18:29:11 <[g2]> lennert I know a little about T1/E1 but not really ISDN Jan 04 18:29:16 okay Jan 04 18:29:28 <[g2]> is BRI 2D + 1B ? Jan 04 18:29:32 yup Jan 04 18:29:53 <[g2]> I think the 2D are just like the channelized T1/E1 Jan 04 18:29:56 192kHz bit rate, 4000 frames of 48 bits per second Jan 04 18:30:15 (actually, it's D + 2B) Jan 04 18:30:22 32 of those 48 are the B channels Jan 04 18:30:24 <[g2]> right Jan 04 18:30:25 4 are D Jan 04 18:30:47 <[g2]> it's been a while Jan 04 18:31:06 <[g2]> 2B + 4D ? Jan 04 18:31:13 then there are some low bandwidth channels between the TE and NT for enabling selftest, loopback Jan 04 18:31:17 no, 2B + 1D Jan 04 18:31:23 but 4 bits out of the 48 are for D Jan 04 18:31:28 and 32 out of 48 are for B Jan 04 18:31:46 that makes the D data rate 16000 bits/sec Jan 04 18:31:51 and the B data rate 2x64000 bits/sec Jan 04 18:31:57 <[g2]> nod Jan 04 18:32:04 <[g2]> that sounds familiar Jan 04 18:32:10 the rest is framing and balance Jan 04 18:32:14 but there is one "Activation bit" Jan 04 18:32:20 which doesn't seem to be documented anywhere else Jan 04 18:32:27 <[g2]> and the signalling on the 16000 bit channel is the tricky part Jan 04 18:32:35 that's LAPD Jan 04 18:32:42 related to LAPB and HDLC Jan 04 18:32:49 all Q.xxx stuff Jan 04 18:32:54 i finally have those Q.xxx standards in .pdf now Jan 04 18:33:05 <[g2]> does the Activation bit just toggle high and low ? Jan 04 18:33:06 instead of antiquated microsoft word 2.0 format (which no modern program can read anymore) Jan 04 18:33:15 i don't know, it doesn't say Jan 04 18:34:06 ok, so, thanks Jan 04 18:34:08 <[g2]> I forget or never really knew how the clocking was done with ISDN Jan 04 18:34:12 well Jan 04 18:34:16 the NT clocks the BRI off the network Jan 04 18:34:26 there is the 'U' interface between the NT and the ISDN network Jan 04 18:34:37 the BRI (the S/T interface) is clocked off the U interface Jan 04 18:34:56 and the ISDN equipment synchronises to that 192kHz clock and synchronise the transmissions back to the NT to that clock Jan 04 18:35:22 (with 2 bits delay) Jan 04 18:35:35 <[g2]> my Q is how the NT derives the clock from the signal Jan 04 18:35:46 <[g2]> what's the clock recovery mechanism Jan 04 18:35:53 which signal? the signal from the network or the signal from the terminal equipment? Jan 04 18:36:39 <[g2]> often the network is the master and the CPE just recovers clock from there right ? Jan 04 18:36:42 yeha Jan 04 18:36:49 <[g2]> the Xmit is slaved to the RX Jan 04 18:36:51 i assume with a PLL of some sort Jan 04 18:36:56 <[g2]> then they jitter together Jan 04 18:37:03 <[g2]> and there aren't any frame slips Jan 04 18:37:06 the S/T uses inverse AMI to ensure enough transitions Jan 04 18:37:20 not sure what U uses Jan 04 18:37:27 probably something like that too Jan 04 18:37:52 <[g2]> I thought in E1 the Channel 0 or 16 whichever had something in it to derive the clock Jan 04 18:38:02 yeah Jan 04 18:38:06 <[g2]> T1 can get it from the framing Jan 04 18:38:12 could be Jan 04 18:38:27 <[g2]> I'm pretty sure that's how it's recovered with T1 Jan 04 18:39:09 <[g2]> So there's either some bits in the D channel or in the wrapper of the 2B + D envelope Jan 04 18:39:19 <[g2]> s/bits/bit(s) Jan 04 18:40:10 i can't find where the U interface is defined Jan 04 18:40:27 well, S/T uses AMI Jan 04 18:40:29 which is ternary Jan 04 18:40:37 i.e. there is not just on/off but -1, 0 and 1 Jan 04 18:40:49 a sequence of 11111 is sent on the line as 0000000 Jan 04 18:40:58 but a sequence of 00000 is sent as -1 +1 -1 +1 -1 Jan 04 18:41:10 010101010101 is sent as -1 0 +1 0 -1 0 +1 0 etc Jan 04 18:41:26 <[g2]> I thnk that's how the recover the frame and clock Jan 04 18:41:31 yeah Jan 04 18:41:41 to find the start of the 48-bit frame, look for a code violation Jan 04 18:41:47 <[g2]> and the -1 and +1 are used to not build up cap. on the line Jan 04 18:41:53 so instead of -1 +1 -1 there will be -1 +1 +1 or something Jan 04 18:42:06 yes, to keep it DC-free Jan 04 18:42:37 <[g2]> and the bit-stuffing in HDLC had to do with the repeater lenght Jan 04 18:42:42 <[g2]> at least for T1 iirc Jan 04 18:42:57 <[g2]> cause 45 years go the electronics were a little different Jan 04 18:43:00 not sure about HDLC yet Jan 04 18:43:03 :) Jan 04 18:43:08 stuff changes.. Jan 04 18:43:20 <[g2]> the bit-stuffing prevents more than 5 1's iirc Jan 04 18:43:43 <[g2]> it inserts an extra bit with a 0 Jan 04 18:43:44 oooh Jan 04 18:43:48 <[g2]> maybe it's 6 1 Jan 04 18:43:50 <[g2]> 1s Jan 04 18:43:50 i see what you mean Jan 04 18:44:05 B8ZS? Jan 04 18:44:11 http://en.wikipedia.org/wiki/B8ZS Jan 04 18:44:17 <[g2]> no HDLC Jan 04 18:44:21 oh Jan 04 18:44:33 HDLC is carried Jan 04 18:44:33 <[g2]> B8ZS is clear channel Jan 04 18:44:41 HDLC is carried inside the D-channel, no? Jan 04 18:44:53 <[g2]> yes it's bit oriented Jan 04 18:45:05 you don't need to prevent more than X 1s at that level because the lower layers do the proper escaping, right? Jan 04 18:45:26 <[g2]> well it's transparent Jan 04 18:45:40 yeah Jan 04 18:45:41 <[g2]> you don't know if you're running over fiber or a T1 Jan 04 18:45:48 oh Jan 04 18:46:01 so this crap is actually done on two different layers for T1? Jan 04 18:46:05 <[g2]> so yes it's transparent to the upper layers Jan 04 18:46:36 damn, i can't find the U specs Jan 04 18:46:37 <[g2]> it's just an interface Jan 04 18:47:08 <[g2]> with B8ZS you just glob together N 64K channels Jan 04 18:47:16 <[g2]> like 1,3,5,7 and 9 Jan 04 18:47:25 <[g2]> that'd be 5x64K Jan 04 18:47:39 B8ZS is replacing 00000000 by 000V10V1 iirc Jan 04 18:47:59 <[g2]> that's sounds right too Jan 04 18:48:05 (V = violation code) Jan 04 18:48:13 <[g2]> you couldn't have too many 0s on the line either :) Jan 04 18:48:18 of course ;) Jan 04 18:48:29 actually, you can't have any bits on the line or it'll break! Jan 04 18:49:07 <[g2]> I thought they'd just fall out of the middle :) Jan 04 18:49:20 indeed, they could Jan 04 18:49:27 hey.. I left you all with JTAG and now.. whate are all those ISDN acronyms? :-D Jan 04 18:49:41 dwery-away: sorry :) Jan 04 18:49:46 dwery-away: switched subjects :) Jan 04 18:49:47 it remembers me the good old days when I was a XyXEL betatester :-D Jan 04 18:49:53 ZyXEL ? Jan 04 18:49:54 ZyXEL Jan 04 18:49:56 yeah Jan 04 18:50:02 i have an adsl modem of theirs Jan 04 18:50:14 i had one of their isdn modems Jan 04 18:50:16 i'm plenty of old ISDN routers and TAs... Jan 04 18:50:30 the TAs where fine.. you can't find a TA like theirs nowadays Jan 04 18:50:42 ah Jan 04 18:50:47 the U interface uses 2B1Q Jan 04 18:50:53 they were small ISDN PBX Jan 04 18:51:32 U = ANSI T1.601 Jan 04 18:52:57 80 ksymbols/sec at 4 levels (2 bits per symbol) Jan 04 18:53:54 it's not like AMI.. so i assume the clock can be derived from the framing Jan 04 18:54:21 <[g2]> QPSK ? Jan 04 18:54:32 no, not phase shift encoding Jan 04 18:54:36 they don't use a carrier Jan 04 18:54:47 <[g2]> FSK Jan 04 18:55:02 just -2.5V for 00, -0.83V for 01, 0.83V for 11 and +2.5V for 10 Jan 04 18:55:09 <[g2]> ASK Jan 04 18:55:13 <[g2]> AM Jan 04 18:55:16 [x] none of the above Jan 04 18:55:20 <[g2]> AM Jan 04 18:55:42 not AM either Jan 04 18:55:46 <[g2]> VM Jan 04 18:55:47 <[g2]> :) Jan 04 18:56:05 what's that? :) Jan 04 18:56:21 <[g2]> Voltage Modulation :) I just made it up Jan 04 18:56:37 hehe Jan 04 18:56:42 <[g2]> I don't think it's really called that Jan 04 18:56:52 well, it's kind of like Amplitude Shift Keying, except that it doesn't use modulation Jan 04 18:57:00 <[g2]> right Jan 04 18:57:10 <[g2]> there's no carrier Jan 04 18:57:11 you can say it's ASK with DC +2.5V as the 'carrier' wave :) Jan 04 18:57:20 DC instead of a sine Jan 04 18:57:23 [g2]: indeed Jan 04 18:57:54 so, as i said.. you get all the ITU specs, and the U ISDN spec is not part of the series cause it's an ANSI spec Jan 04 18:57:55 <[g2]> and how do they recover the clock ? Jan 04 18:58:05 [g2]: i don't have the spec.. Jan 04 18:58:17 [g2]: not from the data bits, i assume Jan 04 18:58:24 [g2]: so from the framing somehow Jan 04 18:58:40 [g2]: there's 12kbps (out of 160kbps) used for framing Jan 04 18:58:47 <[g2]> nod. there's most likely a framing wapper Jan 04 18:59:02 <[g2]> bps or sps Jan 04 18:59:29 bps/sps ? Jan 04 18:59:38 <[g2]> cause that's 6k symbols or 80k symbols Jan 04 19:00:09 the start of each frame probably has some clear pattern Jan 04 19:00:45 <[g2]> nod, but I'm just saying the framiing and data are running at half the rate Jan 04 19:00:54 <[g2]> due to the physical encoding Jan 04 19:00:55 yeah, they do Jan 04 19:00:58 2 bits per symbol Jan 04 19:01:27 <[g2]> so 12kps is really 6k symbols per second.... that's all I was saying Jan 04 19:01:40 yeah, okay, got it Jan 04 19:01:50 <[g2]> you get twice at long to process the symbol Jan 04 19:02:03 <[g2]> I didn't know what the real data rate was Jan 04 19:02:24 'real' data, 64+64+16 Jan 04 19:02:39 <[g2]> nod Jan 04 19:02:42 12 for framing and 4 for loop management Jan 04 19:03:11 =160 Jan 04 19:03:38 still didn't figure out what the activation bit is :) Jan 04 19:03:57 <[g2]> sorry I don't know Jan 04 19:04:07 no i mena, i'm looking through the docs Jan 04 19:04:15 <[g2]> nod Jan 04 19:05:23 <[g2]> lennert did you test you UART or just simulate it to find out the rate it would support ? Jan 04 19:05:33 <[g2]> s/your UART Jan 04 19:09:12 i tested it on the s3 board and it seemed to work okay Jan 04 19:09:20 i only tested it up to 115k2 though Jan 04 19:09:39 but the timing report said it should work up to 50MHz-ish Jan 04 19:09:46 <[g2]> right, but I thought you said that it could run to like 1M Jan 04 19:09:50 <[g2]> in theory Jan 04 19:09:54 (that's oversampled clock rate) Jan 04 19:10:19 ok, let me synthesize it to see what it says, i'm kind of vague on the actual rate Jan 04 19:11:03 i didn't test 1M Jan 04 19:11:20 not yet :) Jan 04 19:11:30 don't have a suitable receiver Jan 04 19:11:38 maybe i could test it in loopback Jan 04 19:11:41 <[g2]> lennert you don't have to... I was wondering whether you had tested it or just synth'd it Jan 04 19:12:22 extensively tested, on the s3 board, only up to 115.200 Jan 04 19:12:28 Clock period: 6.391ns (frequency: 156.459MHz) Jan 04 19:12:30 hum Jan 04 19:12:43 <[g2]> I meant at the 1M rate Jan 04 19:13:05 <[g2]> ka6sox-office had mentioned something about how fast the OC could run Jan 04 19:13:17 <[g2]> open-collector Jan 04 19:13:19 OC? Jan 04 19:13:29 oh Jan 04 19:13:32 how do you mean? Jan 04 19:14:17 <[g2]> that's what I'm trying to understand. He mentioned there might be a rate limiting factor and I didn't really grasp why Jan 04 19:14:29 well Jan 04 19:14:40 he probably means that if you use OC, your output can't switch too fast? Jan 04 19:15:03 OC = external pull-up resistor, and the output buffer shorts the output to ground or floats it Jan 04 19:15:19 if you float it, it takes a while for the output to go back high Jan 04 19:15:31 <[g2]> RC tie Jan 04 19:15:34 <[g2]> RC time Jan 04 19:15:41 depends on how stiff you pull-up is or how much current you sink into it Jan 04 19:15:54 kind of, yes, since your transmission line is kind of a C Jan 04 19:16:13 with a regular resistor it'll go exponentially back to 1 Jan 04 19:16:16 with a current source linearly Jan 04 19:16:24 check the SMBus specs, it has a good explanation about this Jan 04 19:16:30 the SMBus is open collector too Jan 04 19:16:33 and they have the same issues Jan 04 19:16:45 <[g2]> thx for the reference Jan 04 19:16:50 a regular RS232 connection is not OC though (since there's only one master) Jan 04 19:16:56 <[g2]> is JTAG driven OC ? Jan 04 19:16:57 so i wonder if this is what he meant Jan 04 19:17:01 JTAG is OC, yes Jan 04 19:17:05 external pullups Jan 04 19:17:12 so, same issu Jan 04 19:17:13 e Jan 04 19:17:39 http://www.smbus.org/specs/smbus20.pdf Jan 04 19:18:08 <[g2]> now that's great timing :) Jan 04 19:18:11 see page 10 Jan 04 19:18:24 page 15 for the smbus model Jan 04 19:18:31 (Cbus and Rp) Jan 04 19:18:44 hi ka6sox Jan 04 19:18:58 hiya Jan 04 19:19:02 whazzup? Jan 04 19:19:24 talking about OC :) Jan 04 19:19:52 cool...I'm here Jan 04 19:19:53 <[g2]> lennert's sch00l1ng me Jan 04 19:20:17 i just explained OC and how rise/fall time is affected by the stiffness of your pullups Jan 04 19:20:36 the problems with OC and FPGA/CPLD's are well known :) Jan 04 19:20:43 and pointed [g2] to the smbus spec (http://www.smbus.org/specs/smbus20.pdf) which has purty diagrams Jan 04 19:20:45 exactly. Jan 04 19:20:56 good plan. Jan 04 19:21:23 p10 and p15 mostly Jan 04 19:21:29 <[g2]> is I2C OC too ? Jan 04 19:21:31 some have a step function in them where they go to 3.3v quickly and then sorta creep up to the OC pullup voltage. Jan 04 19:21:34 [g2]: yeah Jan 04 19:22:00 its definately OC. Jan 04 19:22:05 ka6sox: you get linear voltage rise with a current source and exponential with a resistor.. Jan 04 19:22:22 ka6sox: so you can do the linear thing to get there quicker.. Jan 04 19:22:37 ya..but its still a step function. Jan 04 19:22:54 how do you mean, step function? Jan 04 19:23:23 <[g2]> _|--- Jan 04 19:24:09 the voltage rise isn't a step function, is it? Jan 04 19:24:43 yes it is...it rises quickly to Vio and then slowly up to Vpullup Jan 04 19:25:23 if you let it float? doesn't it go exponential all the way if you have a pullup resistor? Jan 04 19:25:39 what exact configuration are you thinking of? :) Jan 04 19:25:45 maybe we're thinking of different circuits Jan 04 19:26:27 the OC with a pullup Jan 04 19:27:30 ka6sox: Is the Memec ijc-2 cable supported by wince jtag? Jan 04 19:29:43 ka6sox: OC is an RC circuit, is it not? Jan 04 19:30:32 http://en.wikipedia.org/wiki/RC_circuit Jan 04 19:30:39 i'm thinking of those diagrams Jan 04 19:30:52 {capacitor,resistor} voltage step-response Jan 04 19:45:20 yeah, time for sleep, 5 AM here Jan 04 19:45:21 g'nite all! Jan 04 19:46:26 <[g2]> nite Jan 04 19:46:45 [g2] how is the download coming? Jan 04 19:46:54 <[g2]> so far so good Jan 04 19:47:03 <[g2]> 8% Jan 04 19:47:10 ah Jan 04 19:47:11 :) Jan 04 19:47:16 <[g2]> started about an hour ago Jan 04 19:47:49 ah cool. Jan 04 19:47:58 <[g2]> I dl'd and SCP a few iso's without error Jan 04 19:48:17 <[g2]> Knoppix and a couple Ubuntu's Jan 04 19:48:53 <[g2]> Knoppix was pulled around 500KB/s and the ubuntus were local at 1.8MB Jan 04 19:49:18 <[g2]> http woud probbly be faster Jan 04 19:49:30 <[g2]> I'll have to try that tomorrow Jan 04 19:49:36 you are wgetting it? Jan 04 19:50:29 <[g2]> yeah Jan 04 19:50:54 <[g2]> I was saying that locally I did a SCP for the ubunutu xfers Jan 04 19:51:00 ah Jan 04 19:51:10 okay I"m going out to a meeting for a bit...bbiaw. Jan 04 19:51:19 <[g2]> cheers and thx Jan 04 19:51:28 np...cya! Jan 04 20:09:23 [g2]: holy mackerel. Cable broadband? Jan 04 20:10:27 <[g2]> beewoolie ??? Jan 04 20:10:37 [g2]: Hey Jan 04 20:11:37 <[g2]> beewoolie the cable broadband runs at 11MBs to 60MBs :) Jan 04 20:11:45 sheesh Jan 04 20:11:56 <[g2]> 100Mbs and 1000Mbs Jan 04 20:45:16 [g2]: dollface says hi Jan 04 20:45:43 <[g2]> hey dollface Jan 04 20:46:30 <[g2]> beewoolie do you know Vincent Sander's nick ? Jan 04 20:49:44 [g2-lap]: Who's that? Jan 04 20:51:16 <[g2-lap]> http://linuxdevices.com/news/NS2222705755.html Jan 04 20:51:32 <[g2-lap]> http://www.simtec.co.uk/products/EB675001DIP/ Jan 04 20:52:18 <[g2]> 32MB ram, 4MB flash, CPLD and room to grow a little Jan 04 20:52:33 <[g2]> sounds about perfect for a little JTAG device no ? Jan 04 20:53:13 <[g2]> "custom cost-effective in lots about 25"... Jan 04 20:54:48 Depends on how fast it can run. Jan 04 20:54:58 That is, how fast it can signal the jtag port. Jan 04 20:55:35 The only thing that the USB device won't be able to do is reach the 20MHz scanningfrequency. Jan 04 20:56:36 <[g2]> the ARM runs at 60Mhz Jan 04 20:56:48 So it might get there. Jan 04 20:57:03 <[g2]> well, it depends on how it's wired to the CPLD Jan 04 20:57:12 <[g2]> I'm guessing at least 8 or 16 bits wide Jan 04 20:57:15 <[g2]> maybe 32 Jan 04 20:57:48 <[g2]> I'd guess the CPLD is hung off a chip select Jan 04 20:57:59 * [g2] should probably just dl the doco :) Jan 04 20:58:06 indeed. Jan 04 20:58:14 I'm going to work on getting something working first. Jan 04 20:58:39 They use a closed source boot loader. Jan 04 20:59:10 <[g2]> yeah so ppl don't have to JTAG Jan 04 20:59:28 <[g2]> but it does have a JTAG header Jan 04 20:59:44 <[g2]> so we could self-reprogram it Jan 04 20:59:58 <[g2]> well not the _same_ unit obviously :) Jan 04 21:00:24 It has a jtag header. Jan 04 21:00:31 Oh, you saw that.... Jan 04 21:00:41 <[g2]> 40 lines tothe Xilinx Jan 04 21:00:49