**** BEGIN LOGGING AT Sat Jan 14 02:59:58 2006 Jan 14 03:32:30 * lennert kicks the ixp23xx one more time **** BEGIN LOGGING AT Sat Jan 14 06:41:03 2006 Jan 14 08:54:53 hi Jan 14 08:55:41 lennert ? there ? Jan 14 09:17:37 someone has ever ran a linux on a Xilinx XC2VP30 ? Jan 14 11:25:34 <[g2]> key2 I've got a BlackDog with a Xilinx PPC core on it running Sarge Jan 14 11:38:37 ka6sox: ping Jan 14 12:42:49 g2: how many PPC is there in your Xilinx ? Jan 14 12:43:18 g2: did you manage to do somethin interesting with it ? Jan 14 13:57:40 <[g2]> key2 I think there's just one hardcore Jan 14 13:58:14 <[g2]> I haven't played with it a whole lot as I'm very busy with Lofts and stuff Jan 14 13:58:23 <[g2]> JTAG etc... Jan 14 13:59:19 <[g2]> I've been following softcores and hardcores on FPGAs for several years and it's just getting cheaper and more possible all the time Jan 14 13:59:59 <[g2]> I think that in 90% of the situations, they don't make sense from a cost side versus a specific chip and smaller FPGA/CPLD Jan 14 16:31:11 Tiersten: ping? Jan 14 16:41:47 hello beewoolie Jan 14 16:47:21 lennert: Jan 14 16:47:25 Hey. Jan 14 16:47:32 I have another circuit question. Care to try it? Jan 14 16:47:45 sure :) Jan 14 16:47:50 ;-) Jan 14 16:47:53 it's like a quiz Jan 14 16:47:55 http://wiki.buici.com/twiki/pub/Main/SimpleJTAG/jtag-schematic.pdf Jan 14 16:48:03 that's the schematic for the JTAG dongle I built. Jan 14 16:48:07 It looks like it works OK. Jan 14 16:48:24 403 Forbidden Jan 14 16:48:35 I don't understand that. Jan 14 16:48:41 You can fetch it from another place... Jan 14 16:48:42 (with wget) Jan 14 16:49:03 ftp://ftp.buici.com/pub/jtag/jtag-schematic.pdf Jan 14 16:49:11 firefox also gives a 403 Jan 14 16:49:18 From ftp? Jan 14 16:49:20 maybe you don't allow lithuanian IPs :) Jan 14 16:49:22 trying ftp now Jan 14 16:49:33 I need to look into that. It seems to work sporadically. Jan 14 16:49:51 okay, got it Jan 14 16:50:23 OK. So the transisitor drives the nTRST line. Jan 14 16:50:41 i see that Jan 14 16:50:51 Trouble is, the signal is really sloppy. Jan 14 16:51:13 Based on my inspection of the circuit, I believe that the transistor is inverting the signal. Jan 14 16:51:16 Is that right? Jan 14 16:51:40 Or, is it just amplifying it? Jan 14 16:51:58 let me check.. Jan 14 16:52:05 I wonder because I'm driving that signal low and the TAP is working. Jan 14 16:53:06 well Jan 14 16:53:17 the base has a pulldown Jan 14 16:53:27 I suppose I can test it OK. Jan 14 16:53:28 so normally the base is at GND and it won't be conducting Jan 14 16:53:30 Right. Jan 14 16:53:39 Hmm. So, it's just amplifying. Jan 14 16:53:44 I wonder why this is working. Jan 14 16:53:48 well Jan 14 16:53:51 There are really two questions. Jan 14 16:53:57 you have to write an 1 to pull nTRST to ground Jan 14 16:54:03 i assume that nTRST is normally pulled high Jan 14 16:54:07 i.e. it's inverting Jan 14 16:54:11 (i think :) Jan 14 16:54:57 what signal is sloppy? Jan 14 16:56:39 The output of that transistor. Jan 14 16:56:54 I need to get a power strip so that I can look at it again... Jan 14 16:57:22 i'm looking at a 2n3904 datasheet which says the prop delay is 35ns and the rise/fall are 35/50 ns respectively Jan 14 16:57:43 does that match what you saw? Jan 14 16:57:59 lennert: What I've been concerned about is whether or not it is driving the line, or simply grounding it when the base is ground. Jan 14 16:58:06 Let me try again... Jan 14 16:58:21 when the base is driven _high_, the nTRST line is shorted to ground Jan 14 16:58:33 when the base is undriven (pulldown), the nTRST line floats Jan 14 17:00:12 i guess that doesn't answer your question.. ? Jan 14 17:00:22 Wait. Let me read that again. Jan 14 17:00:34 Ah, so it does invert. Jan 14 17:00:39 yes Jan 14 17:00:45 OK. That helps some. Jan 14 17:00:51 I'll need to edit my schematic. Jan 14 17:00:56 oh Jan 14 17:01:01 you made this schematic? Jan 14 17:01:03 The problem is that when it floats. Jan 14 17:01:09 Yeah. I drew it. Jan 14 17:01:14 I didn't design it. Jan 14 17:01:17 oh, okay Jan 14 17:01:24 The notation on the inputs is wrong. Jan 14 17:01:30 It should read TRST and not nTRST. Jan 14 17:02:01 in jtag, does TRST have a pullup like TDI/TMS/TDO do? Jan 14 17:02:03 The other problem is that when the base pulled low and the collector floats, the nTRST output takes a long time to float. Jan 14 17:02:12 I think it is supposed to. Jan 14 17:02:24 well Jan 14 17:02:27 What I've read is that the standard requires pull-ups. Jan 14 17:02:52 But, the signal is fast to fall from 3.3V. It takes a long time to rise back again. Jan 14 17:02:57 the transistor probably floats right away but the trst still has some capacitance Jan 14 17:03:11 the transistor itself probably has some c-e capacitance as well Jan 14 17:03:16 -- you'd need a pullup Jan 14 17:03:42 i.e. the electrons aren't leaking away very quickly when the transistor floats Jan 14 17:03:45 OK. That's what I thought. Jan 14 17:03:54 I'll see about modifying the circuit. Jan 14 17:04:05 I want to look at the other lines, too. it could be that all of them need pull-ups. Jan 14 17:04:15 i think they should be pulled up on the board.. ? Jan 14 17:04:28 I thought that nTRST was pulled up, too. Jan 14 17:04:33 i think my s3 board has pullups for tdi/tms/tck on the board... Jan 14 17:04:35 Once I look at the signals, I should be able to tell. Jan 14 17:04:53 when i looked at the diagram i assumed that trst would have a pullup too, cause i didn't see one Jan 14 17:05:05 What diagram/ Jan 14 17:05:05 fluke to the rescue :) Jan 14 17:05:05 ? Jan 14 17:05:11 the pdf i ftp'ed from you Jan 14 17:05:20 i thought, hey no pullup Jan 14 17:05:33 so i assumed that trst would have a pullup on the board Jan 14 17:05:34 I don't understand. Jan 14 17:05:39 okay Jan 14 17:05:40 Oh, right. So do I. Jan 14 17:05:46 okay :) Jan 14 17:05:47 I'll check. Jan 14 17:06:04 i'm going home on monday and first thing i'll do in .nl is get my fluke :) Jan 14 17:06:24 Yeah! Jan 14 17:06:30 OK. the clock signal looks really clean. Jan 14 17:06:41 I'm going to increase the speed and see how it looks. Jan 14 17:07:03 you have a scope, too.. Jan 14 17:07:29 Yeah. I bought it from an auction site. Jan 14 17:07:35 It was about $150. Jan 14 17:07:39 wow Jan 14 17:07:44 Maybe $200. Jan 14 17:07:51 It was a reasonable price considering. Jan 14 17:07:57 taksa should get me one of those Jan 14 17:08:22 :-) Jan 14 17:08:36 Looks like the interface works fine, even at the highest speed. Jan 14 17:08:46 what's the highest speed? Jan 14 17:09:21 with this transistor, i think trst can toggle at 10mhz or so if you're pushing it :) Jan 14 17:10:16 The parallel port can only do 270KHz. Jan 14 17:10:34 Should a 10K pull-up be OK? Jan 14 17:11:04 .3ma drain. Jan 14 17:11:52 i think so.. Jan 14 17:12:37 the transistor has about 4 pF output capacitance Jan 14 17:13:02 (according to the datasheet) Jan 14 17:13:36 i.e. 10k will pull it up in 200ns or so Jan 14 17:17:13 lennert: how do you figure that out Jan 14 17:17:14 ? Jan 14 17:17:45 Given a charged capacitor, how long will it take to discharge through a known resistance. Or in this case, charge up. Jan 14 17:23:12 RxC Jan 14 17:24:38 4 times the RC time Jan 14 17:24:52 (as a guideline) Jan 14 17:24:57 what ka6sox said Jan 14 17:25:04 ka6sox: Hey. Jan 14 17:25:21 it looks like my UBE jtag interface is fine for the task. Jan 14 17:25:40 In fact, it even has nTRST. Jan 14 17:27:13 lennert: so, RC in this case would be 40ns, 4pf*10KOhms. Jan 14 17:27:25 But, it's really an exponential, right? Jan 14 17:28:00 e^-kt or some such nonsense. Jan 14 17:28:03 yes, it's exponential Jan 14 17:28:03 yes Jan 14 17:28:11 R * C is the "RC time" Jan 14 17:28:29 i.e the time it needs to go to x % of its value Jan 14 17:28:34 (when discharging) Jan 14 17:29:05 beewoolie, w00t Jan 14 17:29:08 glad to hear that Jan 14 17:29:16 (63%, which is 1 - 1/e) Jan 14 17:29:27 see http://en.wikipedia.org/wiki/RC_circuit Jan 14 17:29:35 ya..what he said Jan 14 17:29:40 heading "Time domain considerations" Jan 14 17:29:43 ka6sox: thx. I built it so long ago... the openwince jtag software doesn't work with it, but I'm not sure why. Jan 14 17:29:55 ah Jan 14 17:30:14 usually you take 4 or 5 times the RC time to consider it 'done' Jan 14 17:30:47 (at 5 times the RC time, (1/e)^5 = 0.7% of the charge will be left) Jan 14 17:30:58 I thought that this board was broken. I finally got around to looking at it and the only problem I cna see is this nTRST rise time. Jan 14 17:31:12 lennert: Ah, I see. Jan 14 17:44:50 any math geeks here? Jan 14 17:49:57 lennert: what's the Q Jan 14 17:50:21 i want to convert a 50mhz clock to a 1.8432mhz clock Jan 14 17:50:32 that doesn't really divide nicely Jan 14 17:50:37 so Jan 14 17:51:12 what you can do is that you generate a clock every 28 cycles for 73 times in a row, and then generate one every 27 cycles for 576-73 times in a row Jan 14 17:51:19 that will give you exactly 1.8432mhz Jan 14 17:51:21 but a lot of jitter Jan 14 17:51:42 (50 mhz / 1.8432 mhz = 27 + 73/576) Jan 14 17:52:05 what is the optimal way of dividing the 27 and 28 over the 576 slots? :) Jan 14 17:52:17 not sure how to phrase it more clearly Jan 14 17:52:20 does it make any sense? Jan 14 17:52:38 Let me think about that for a moment. Jan 14 17:54:51 How accurate do you want it? Do you want 5 digits? Jan 14 17:55:15 the optimal way Jan 14 17:55:26 28 28 28 28 28 28 28 27 27 27 27 isn't very optimal Jan 14 17:55:36 27 27 27 28 27 27 27 27 27 27 27 28 27 27 27 is much better already Jan 14 17:57:09 Are you planning to do this with some flip-flops? Jan 14 17:57:13 there are 6169588227439311236793765122563713685468080277641945401304843362102684539482558630358706188800 possible ways according to 'bc' Jan 14 17:57:18 yeah Jan 14 17:57:24 Seems cheaper to get the right crystal. Jan 14 17:57:25 i have it using the non-optimal way now Jan 14 17:57:33 hehe Jan 14 17:57:36 it's for the spartan3 board Jan 14 17:57:46 i do have a 1.8432mhz extra crystal on it Jan 14 17:57:51 but that way my projects aren't 'portable' Jan 14 17:57:57 Oh. So the flip-flops are cheap...er...free? Jan 14 17:58:09 the flipflops come with the spartan3 board ;) Jan 14 17:58:13 :-) Jan 14 17:58:48 i _think_ the 'greedy' algorithm is optimal Jan 14 17:58:54 but i can't prove it :-/ Jan 14 17:59:26 i.e. your input clock is 50mhz, 20ns period Jan 14 17:59:28 That's where I'm going. Jan 14 17:59:45 they are "free" essentially Jan 14 17:59:46 you want the output to have a 542.53ns period (1843200 hz) Jan 14 17:59:48 You accumulate error until you overflow. Jan 14 18:00:15 27 cycles gives you a 540ns period but 28 gives you a 560ns period Jan 14 18:00:23 so, the first cycle it's better to wait 27 cycles Jan 14 18:00:31 cause 542.53 is closer to 540 than 560 Jan 14 18:00:41 but then you have 2.53 error Jan 14 18:00:47 etc. Jan 14 18:00:50 it sounds like you need a "real 1.8432MHZ" Jan 14 18:01:14 ka6sox: sure, and i have one, but it doesn't come with the sp3 board by default Jan 14 18:01:30 ok, i admit, it's a bit of an academical exercise Jan 14 18:01:39 heh Jan 14 18:01:56 After about 8 27's you put in a 28. Jan 14 18:02:03 yeah Jan 14 18:02:21 the greedy method gives ---+-------+-------+- Jan 14 18:02:25 where - is 27 and + is 28 Jan 14 18:02:52 That gives 542.22 Jan 14 18:03:00 (the distance between +s is sometimes 7, sometimes 8) Jan 14 18:03:16 1.8442 Jan 14 18:03:22 1.8443 Jan 14 18:03:59 as long as you do 73 '28's per 576, you won't drift Jan 14 18:04:01 You'd have to alternate between 8 and 9. Jan 14 18:04:15 it's just for the jitter Jan 14 18:04:22 hmmm Jan 14 18:04:37 If that's what you care about, you could just do 73 28's and then the rest as 27's. Jan 14 18:04:55 yeah, but that gives awful jitter Jan 14 18:06:20 it's not a simple ration. Jan 14 18:06:22 ratio. Jan 14 18:06:46 Is this audio? Jan 14 18:07:01 1.8432mhz = 16 * 115200 Jan 14 18:07:07 it's for serial Jan 14 18:07:16 (where the jitter also doesn't matter much..) Jan 14 18:07:22 (as i said, academic exercise..) Jan 14 18:07:34 (just one of those problems that grab you and won't let go) Jan 14 18:12:09 It's a good one. Jan 14 18:13:00 Seems like you can model it with an error calculation, There is an ideal period and there is the current period. It's a DDA. Jan 14 18:13:12 The trouble is that the target is irrational. Jan 14 18:13:39 You may need 576 data points to get it right. In fact, you could precalc the steps and just code them directly. Jan 14 18:15:36 well, in hardware you can do it with a 576 bit array if you do it the ube way Jan 14 18:15:59 i'm sure you can use some tricks to get the logic down Jan 14 18:15:59 It isn't really that bad once you calculate the ideal pattern. Jan 14 18:16:02 yeah Jan 14 18:16:12 so, is the greedy algorithm ideal? Jan 14 18:16:18 It's really a short c program. Jan 14 18:16:28 I don't know that by name, I suspect yes. Jan 14 18:17:07 okay... i got disconnect 5 minutes ago - gotta love 24h disconnect Jan 14 18:17:08 You can calculate the frequency at every step. When it goes below the target, add a 28. Jan 14 18:17:16 i have a c program that calculates the root mean square of the 'jitter' Jan 14 18:17:17 :-) Jan 14 18:17:36 lennert: I don't think it's that hard. Jan 14 18:17:41 the rms is remarkably better if you do it the greedy way Jan 14 18:18:32 http://www.wantstofly.org/~buytenh/clocks.c Jan 14 18:23:29 oh, beewoolie is marc singer? Jan 14 18:25:11 vmaster_: yes.. Jan 14 18:25:27 vmaster_: how long did that take you? :-) Jan 14 18:25:44 mhh... idling this channel for 3 months Jan 14 18:26:03 i just had a look at his jtag schematic Jan 14 18:26:27 people should use their real names on irc anyway ;) Jan 14 18:27:55 hehehe Jan 14 18:28:38 [02:29] [freenode] -!- Nick dominic is already in use Jan 14 18:28:45 bad luck, i guess Jan 14 18:29:07 i don't know vmaster_'s real name either.. :) Jan 14 18:29:21 well, that's what the realname field in /whois is for :) Jan 14 18:31:23 vmaster_: dood step off! Jan 14 18:32:09 'step off'? Jan 14 18:32:21 lennert: Sure, you can use the error and optimize the transitions to get closest. Jan 14 18:32:43 It isn't polite to bandy folks' names about on a public channel. Jan 14 18:32:51 It's kinda like passing people's email addresses. Jan 14 18:33:06 ah, right. just wasn't sure what 'step off' means. Jan 14 18:33:38 it's still a DDA algorithm. Jan 14 18:33:58 I've done it countless times when drawing pixel lines Jan 14 18:34:20 oh, Bresenham? Jan 14 18:34:35 i know that as the bresenham algorithm Jan 14 18:34:49 wonder if wikipedia has a proof.. Jan 14 18:38:22 it doesn't Jan 14 18:49:33 lennert: interesting. 10K doesn't work. Jan 14 18:50:00 as in.. doesn't pull it up fast enough? Jan 14 18:50:04 Nope. Jan 14 18:50:04 how long is it taking to pull up? Jan 14 18:50:22 the resistor make the curve a little taller and squarer, but not significantly. Jan 14 18:50:38 Presently, the rise takes about 2ms Jan 14 18:50:41 is this while it's connected to the target? Jan 14 18:50:45 Yeah. Jan 14 18:50:49 okay Jan 14 18:51:02 maybe there's a lot of capacitance in the target Jan 14 18:51:23 does it go faster when it's disconnected from the target? Jan 14 18:52:03 I haven't tried... Jan 14 18:52:37 can you give that a try? Jan 14 18:52:43 Yeah. :-) Jan 14 18:52:49 :) Jan 14 18:52:52 Without a pullup, the output signal isn't nice. Jan 14 18:53:01 Hang on. I need to move the ground. Jan 14 18:53:36 It's flat without a pull-up. Jan 14 18:53:46 how do you mean? Jan 14 18:53:46 Let me try with the pull-up, too. Jan 14 18:53:52 There is no output signal. Jan 14 18:53:55 It's 0v Jan 14 18:54:02 okay, hmmm Jan 14 18:55:21 well, without the target connected there's no vcc :) Jan 14 18:55:34 i think Jan 14 18:55:39 if i'm reading this thing right Jan 14 18:56:05 Yeah. Just noticed that. I have no pullup without the target. Jan 14 18:56:34 Let me look at the schematic. Jan 14 18:56:39 For the target... Jan 14 18:58:37 10K pullups on the board for TDI, TMS and TCK. Jan 14 18:58:45 and tdo. Jan 14 18:59:36 10k should be fine Jan 14 19:00:11 Wierd. They've got a 10K pull-down on tck as well. Jan 14 19:00:40 to make it symmetric, probably Jan 14 19:00:56 so the rise time and fall time will be about equal? Jan 14 19:01:28 you're probably supposed to drive TCK both ways Jan 14 19:01:41 (instead of driving it one way and floating it the other way, as with tdi/tms) Jan 14 19:02:09 you don't know the pullup value on $RANDOM_BOARD Jan 14 19:02:13 Seems like there should only be one. Jan 14 19:02:24 Remember, this is on the board itself. Jan 14 19:02:26 It's got both. Jan 14 19:02:27 why? it makes sense to me. Jan 14 19:02:28 yes Jan 14 19:02:52 let's see what the sp3 board has Jan 14 19:03:00 All it's going to do is create a current drain. Jan 14 19:03:13 and make the clock more symmetric Jan 14 19:03:20 Oddly, trstn isn't beside the other lines. Jan 14 19:04:27 on the xupv2p tck only has a pull-up Jan 14 19:04:58 I admit I'm no pro at this, but I don't see how a pull-up and pull-down will make the signal more square. Jan 14 19:05:36 if you only have a pull-up, the fall time is determined by your drive strength (in mA) and the rise time by the size of the pull-up Jan 14 19:06:08 drive strength is determined by what's on the jtag adapter, while the pull-up is on the target board Jan 14 19:06:20 * ByronT is away: auto-away after 180m idle Jan 14 19:06:36 instead of floating it when you want to make TCK rise, you can actively drive it to vcc Jan 14 19:06:52 but then the rise time and fall time will still be different because you have the pull-up Jan 14 19:07:02 does that make any sense? Jan 14 19:07:51 if you use a current source to pull the bus down, the fall will be linear, while the rise will be exponential (due to the pull-up) Jan 14 19:09:39 I'll accept it without understanding it. for now. Jan 14 19:09:50 It looks like the board doesn't have a nTRST signal. Jan 14 19:10:00 No, the *chip* doesn't have nTRST. Jan 14 19:10:05 They wire nTRST to reset. Jan 14 19:10:09 POR. Jan 14 19:10:44 okay Jan 14 19:10:45 'POR'? Jan 14 19:11:13 Power On Reset. Jan 14 19:11:17 right Jan 14 19:11:25 hm Jan 14 19:11:28 it's a full reset instead of a warm reset. Jan 14 19:11:37 So, that means that there could be a lot of things using that line. Jan 14 19:11:42 yeah Jan 14 19:11:50 I think that I have to accept that the JTAG schematic is really OK. Jan 14 19:12:02 I just need to let the reset be slow. Jan 14 19:12:04 2ms sounds like it has not 4pF but 40nF capacitance.. well, that's still not unrealistic Jan 14 19:12:19 That's what I thought. Jan 14 19:12:39 Let's see if the data sheet has a value for it. Jan 14 19:12:57 i wonder why they don't use a simple buffer for TRST Jan 14 19:13:11 but a transistor instead Jan 14 19:13:20 probably because they expect the transistor to be off most of the time, hm Jan 14 19:14:54 lennert: do you mean on my schematic? Jan 14 19:15:01 beewoolie: yes Jan 14 19:15:08 I think because it inverts. Jan 14 19:15:16 And, there are no more lines. Jan 14 19:15:19 you can get inverting buffers too Jan 14 19:15:28 The 244 has only four outputs. Jan 14 19:15:35 right Jan 14 19:15:43 Another chip? or a transistor? Jan 14 19:15:45 but an inverting buffer isn't much bigger than a transistor.. Jan 14 19:15:52 another chip Jan 14 19:15:55 Lots more pins. Jan 14 19:15:59 one that can swing trst up as well as down Jan 14 19:16:03 Remember that I made this by hand. Jan 14 19:16:08 I agree. Jan 14 19:16:15 I don't recall where I got the schematic. Jan 14 19:16:22 if you can drive trst both ways you won't have this problem Jan 14 19:16:22 I must credit it somewhere. Jan 14 19:16:30 right, you said it wasn't yours Jan 14 19:16:31 I'm not sure it is a problem. Jan 14 19:16:41 well, no, it's only the reset line Jan 14 19:16:43 I'll have to see how it performs on the slug. Jan 14 19:16:55 Also, the design makes it possible to ignore the voltage of the target. Jan 14 19:16:58 for ntrst. Jan 14 19:17:24 The xlinx design is good this way too, but it has *no* reset capability. Jan 14 19:18:27 ep1220 uses a transistor ...let me check. Jan 14 19:20:05 He uses a FET for the RESET pin and a 245 (buffer) for nTRST Jan 14 19:20:14 right Jan 14 19:21:52 He's got four outputs and four inputs plus a reset. Jan 14 19:22:20 No, that's wrong. Jan 14 19:22:46 He's got four outputs. two inputs, and two selectable as either. Jan 14 19:22:51 Plus reset. Jan 14 19:23:10 Darn, I wish I had that last resistor. Jan 14 19:23:38 how do you mean? Jan 14 19:25:10 http://www.standardics.philips.com/products/lvc/pdf/74lvch322245a.pdf is the datasheet for a 32bit bidi buffer.. the test circuit on page 11 has both a pullup and pulldown on the output, too Jan 14 19:29:22 <[g2]> hey lennert ! Jan 14 19:29:31 [g2]! Jan 14 19:29:48 how's you? Jan 14 19:32:24 <[g2]> Great lennert thx Jan 14 19:33:47 what's funny, over here they always say 'normal' instead of 'good' or 'great' Jan 14 19:33:54 "i'm normal" Jan 14 19:34:10 * [g2] can't say that :) Jan 14 19:34:24 * [g2] is abby-normal Jan 14 19:34:29 well, neither can i :) Jan 14 19:34:36 they just mean that things are as usual Jan 14 19:34:44 <[g2]> that's _why_ we IRC so much :) Jan 14 19:34:55 <[g2]> I fully comprehend Jan 14 19:35:07 to me, 'good' sounds like 'normal'. but they think that 'good' is for when you win the lottery or something. Jan 14 19:35:19 subtle difference in language that i keep forgetting and making mistakes with Jan 14 19:35:24 <[g2]> life is all relative :) Jan 14 19:35:49 yup :) Jan 14 19:36:21 <[g2]> I haven't seen scarface but I heard a line from there "Any day above ground is a good day" Jan 14 19:36:37 hehe Jan 14 19:36:51 my profession is more boring than that Jan 14 19:37:44 <[g2]> beewoolie what was the sticking boint on the JTAG ? Jan 14 19:56:04 [g2]: I don't really know what was wrong. I think that the openwince jtag software has some sort of problem. Jan 14 19:56:30 [g2]: I've got jtag code that works fine with it. Jan 14 19:56:35 Search me. Jan 14 19:56:48 I'll be finishing my code so that I don't have to worry about openwince. Jan 14 19:56:50 <[g2]> Ok your code works but openwince doesn't Jan 14 19:56:56 right. Jan 14 19:57:10 I can read the target ID as well as some of the coprocessor registers. Jan 14 19:57:15 I'm confident that the HW is fine. Jan 14 19:57:22 <[g2]> awesome Jan 14 19:57:32 So, it's just a matter of hacking at JTAG to get the rest of the functionality. Jan 14 19:57:44 It's only been...a year since I built the thing. :-) Jan 14 19:57:56 <[g2]> are you going to move on to flashing or debugging fiirst ? Jan 14 20:00:16 I'm not sure. Jan 14 20:00:23 I need to get access to the processor register. Jan 14 20:00:32 Once I do that, it should be easy to do flashing Jan 14 20:00:43 Debug is going to take more work, but the basics should be easy. Jan 14 20:00:58 [g2]: I'm working on it. ;-) Jan 14 20:01:04 <[g2]> heh Jan 14 20:09:11 ok, 4am, bed time for me Jan 14 20:09:12 nice chatting Jan 14 20:09:14 g'nite all Jan 14 20:09:19 <[g2]> sweet dreams Jan 14 20:09:20 nitey nite Jan 14 20:09:25