**** BEGIN LOGGING AT Sun Jan 29 02:59:57 2006
Jan 29 11:19:55 <vmaster> hmm... someone familiar with sdram setup here?
Jan 29 12:27:03 <AchiestDragon> vmaster:  in what way
Jan 29 12:27:20 <AchiestDragon> timings or interface 
Jan 29 12:43:07 <AchiestDragon> http://www.micron.com/products/dram/sdram/technote.html   < theres lots of related applications notes here  for sdrams 
Jan 29 12:57:44 <AchiestDragon> http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf < for timings and info needed for interfacing one  
Jan 29 15:48:42 <vmaster> AchiestDragon: i'm facing a very strange problem: when writing some addresses, two locations change, for example when writing 0x41feaa00, 0x41feaa40 changes, too
Jan 29 15:48:59 <vmaster> but it's only 0x40 and 0x00
Jan 29 15:49:06 <lennert> odd..
Jan 29 15:49:25 <vmaster> and only one some addresses, i.e. not every 0x40 is aliased to 0x00
Jan 29 15:49:58 <vmaster> s/one/on/
Jan 29 15:49:59 <purl> vmaster meant: and only on some addresses, i.e. not every 0x40 is aliased to 0x00
Jan 29 15:57:59 <vmaster> my problem is that i'm not sure if a faulty sdram setup could cause a problem like that, or if i should look for other possible mistakes
Jan 29 16:00:17 <[g2]> vmaster new board ?
Jan 29 16:00:36 <[g2]> or new sdram ?
Jan 29 16:01:02 <[g2]> sometimes a line get shorted and the connection is transient
Jan 29 16:01:34 <vmaster> mhh, old board, and known to work with a different bootloader
Jan 29 16:01:51 <vmaster> but that bootloader is ugly, so i wanted to move to u-boot
Jan 29 16:02:13 <[g2]> ahh
Jan 29 16:02:20 <[g2]> CS timing ?
Jan 29 16:04:38 <vmaster> all the sdram controller registers are set to the same values... is the sdram mode register something standardised?
Jan 29 16:05:55 <[g2]> there's nothing else on the address bus (like a CPLD or anything is there) ?
Jan 29 16:08:25 <[g2]> vmaster the there idea is that maybe the sdram controller regs are the same, but maybe the clock is from a different reference
Jan 29 16:08:43 <[g2]> causing the actual bus timings to be different
Jan 29 16:09:15 <[g2]> or the VM setup with the MMU
Jan 29 16:09:24 <vmaster> i'm just looking at this... the original bootloader selects 64mhz, while the u-boot port defaults to 70mhz (the chip should handle these)
Jan 29 16:09:52 <[g2]> can you select the 64 ?
Jan 29 16:10:01 <vmaster> yeah, it
Jan 29 16:10:07 <vmaster> 's just a different value in the pll reg
Jan 29 16:10:24 <[g2]> nod
Jan 29 16:10:34 <[g2]> That's what I'd try 
Jan 29 16:10:45 <[g2]> just as a timing test
Jan 29 16:11:08 <[g2]> maybe the picked 64 for a reason :)
Jan 29 16:12:01 <[g2]> were's AchiestDragon's logic analyzer when you need it!
Jan 29 16:13:11 <vmaster> ohh... please... looks like it's working at 64mhz - i got the u-boot prompt
Jan 29 16:13:38 <[g2]> cool
Jan 29 16:14:28 <[g2]> this is the kind of thing I was talking about reading out the chip's state
Jan 29 16:14:36 <AchiestDragon> http://www.whipy.demon.co.uk/aztag1b.zip    < close   
Jan 29 16:14:46 <[g2]> he
Jan 29 16:14:47 <[g2]> heh
Jan 29 16:15:32 <[g2]> AchiestDragon want to talk over the ISA bus right on the PC104 correct ?
Jan 29 16:15:48 <[g2]> s/want/you wan/t
Jan 29 16:15:58 <[g2]> s/want/you want/
Jan 29 16:15:58 <purl> [g2] meant: s/you want/you wan/t
Jan 29 16:16:09 <[g2]> AchiestDragon you want to talk over the ISA bus right on the PC104 correct ?
Jan 29 16:35:57 <vmaster> [g2]: thanks. that stupid clock seems to be the problem
Jan 29 16:40:42 <[g2]> vmaster np
Jan 29 16:40:59 <[g2]> I didn't do anything
Jan 29 16:44:02 <AchiestDragon> g2 yes
Jan 29 16:47:05 <AchiestDragon> tidying up the schematics atm and the silk screens for the pcb , just needs verifying and checking atm  
Jan 29 16:51:29 <[g2]> AchiestDragon are you building pcb's and going to get them stuffed ?
Jan 29 16:52:38 <AchiestDragon> so schedual atm is to allow a month for verification of the design ,  if ok and no faults or errors spotted or changes then should be ordering the first batch of 5 pcbs at end of feb  
Jan 29 16:54:05 <AchiestDragon> still to do on that pcb space is the adaptor boards , so although seperate will still be in a 160*100mm pbc aria 
Jan 29 16:56:03 <AchiestDragon> could of done those on seperate artwork but as one of each adaptor will be required with each main pcb then may as well have them panalized together 
Jan 29 16:58:23 <[g2]> what tool to see the .gxx files ?
Jan 29 16:58:32 <AchiestDragon> gerber files 
Jan 29 16:58:50 <[g2]> yeah Is there a tool you normally use :)
Jan 29 16:58:56 <AchiestDragon> GTL and GBL are the top and bottom pcb layers 
Jan 29 16:59:17 <AchiestDragon> ? for linux , but there are ones arround , 
Jan 29 16:59:36 <AchiestDragon> i use the one in dxp that will also view them 
Jan 29 17:00:34 <AchiestDragon> i did a  autocad dfx export  but at 29mb for the pcb it would not fit in my web space 
Jan 29 17:00:46 <[g2]> pcp ?
Jan 29 17:00:50 <[g2]> pcb ?
Jan 29 17:00:59 <AchiestDragon> pcb artwork 
Jan 29 17:01:03 <[g2]> pcb or gerbv ?
Jan 29 17:01:09 <[g2]> as the linux tools
Jan 29 17:01:47 <AchiestDragon> k
Jan 29 17:02:24 <[g2]> is there a layout file ?
Jan 29 17:02:27 <AchiestDragon> have used pcb in linux , its a sod to enter new parts to the libs 
Jan 29 17:02:33 <[g2]> .gbl ?
Jan 29 17:02:54 <AchiestDragon> yes
Jan 29 17:03:52 <AchiestDragon> .gbl .gbo .gbp .gbs .gtl .gto .gtp .gts
Jan 29 17:05:26 <AchiestDragon> .gbl bottom layer  .gbo bottom overlay  .gbp bottom paste  .gbs bottom silk   .gtl top layer  .gto top overlay .gtp top solder paste .gts top silk screen 
Jan 29 17:05:48 <AchiestDragon> the .ps files there are the schematics 
Jan 29 17:06:06 <[g2]> yeah I was looking at the schematics
Jan 29 17:06:34 <[g2]> now I'm tying to load the gerbers in pcb or gerbv
Jan 29 17:07:30 <AchiestDragon> the schematics need tidying , swapping pins and some changes made a mess of the layout neatness of the schematics , and some page connectors need relabeling to make it more readable  
Jan 29 17:08:05 <[g2]> AchiestDragon I think what you are doing is great
Jan 29 17:08:35 <[g2]> I saw the schematics are GPL (there wasn't a version listed)
Jan 29 17:08:44 <[g2]> I'd guess the gerbers are the same
Jan 29 17:09:09 <AchiestDragon> yes , its noted in text on the updated gerbers 
Jan 29 17:09:14 <[g2]> hey beewoolie-afk welcome
Jan 29 17:09:18 <beewoolie-afk> Hey
Jan 29 17:09:18 <AchiestDragon> but not uploaded them yet 
Jan 29 17:09:34 <beewoolie-afk> Looks like a convo in progress.
Jan 29 17:10:06 <[g2]> beewoolie-afk yeah I was looking at AchiestDragon schematics and trying to look at the gerbers
Jan 29 17:10:27 <AchiestDragon> btw dont post the link as genaral its a large zip and i only have  60mb/day  usage bandwith on my webspace 
Jan 29 17:11:41 <beewoolie-afk> AchiestDragon: is this the S3 pc104 board?
Jan 29 17:11:50 <AchiestDragon> yes 
Jan 29 17:11:59 <beewoolie-afk> Sounds like progress,
Jan 29 17:12:05 <AchiestDragon> http://www.whipy.demon.co.uk/aztag1b.zip    
Jan 29 17:12:25 <beewoolie-afk> If you want it hosted some place, I'd be glad to put it on my server.
Jan 29 17:12:29 <beewoolie-afk> I have unlimited BW.
Jan 29 17:12:35 <beewoolie-afk> Well, unmetered.
Jan 29 17:12:50 <AchiestDragon> it should go in the cvs , i supose 
Jan 29 17:14:35 <AchiestDragon> although i dont think the gerber files should untill we know it works 
Jan 29 17:16:29 <beewoolie-afk> AchiestDragon: I thought we were going to use ep1220's board as part of this?
Jan 29 17:17:44 <AchiestDragon> i used a modifyed version of his interface , on the board , to reduce sgnal losses to the fpga and allow for the extra  signals for the analizer functions 
Jan 29 17:20:03 <AchiestDragon> also allowing for a diferent connector to the adaptor board that will allow for faster data rates over the cable , so 100Mhz should be  ok to about 1' of cable
Jan 29 17:21:13 <AchiestDragon> it uses the .5" pitch cable rather than the .1"   like the cable used on the ata133 ide cables 
Jan 29 17:21:18 <beewoolie-afk> These ARM TRM's seem to be quite error prone.  Just a statement of observation.
Jan 29 17:21:50 <beewoolie-afk> AchiestDragon: I've been wondering about that.
Jan 29 17:22:07 <beewoolie-afk> It looks like the headers are the same on these higher density cables.
Jan 29 17:22:11 <beewoolie-afk> Is that true?
Jan 29 17:22:19 <AchiestDragon> no
Jan 29 17:22:47 <beewoolie-afk> So, the headers a special to accept the ribbon cable.
Jan 29 17:22:52 <AchiestDragon> the  40 way connector for the 80 way cable as ata133 is a odd one 
Jan 29 17:25:22 <AchiestDragon> yes , and avalable cheap'ish      the 3M mini D ribbon (MDR) connectors  102 series    the 36way  is the one i have used 
Jan 29 17:25:49 <AchiestDragon> there like the scsi2 ones but less pins 
Jan 29 17:25:49 <beewoolie-afk> Is there an extra ground between each signal?
Jan 29 17:25:59 <AchiestDragon> yes  
Jan 29 17:28:24 <AchiestDragon> the only exeption are the signals at the end  that is      reset , signal , gnd , signal, gnd ,.........to other end that is   signal , gnd , signal , vccjtag, signal , vcc jtag  
Jan 29 17:28:48 <beewoolie-afk> That should't matter much.
Jan 29 17:28:55 <AchiestDragon> yes
Jan 29 17:32:35 <AchiestDragon> so what adaptors do we need ,,  the analizer adaptor ,  and jtag   20pin, 12pin and 10 pin formats  any others ?  
Jan 29 17:32:49 <beewoolie-afk> AchiestDragon: There is a 14 pin ARM format.
Jan 29 17:34:08 <AchiestDragon> k,  i want to try and sort the adaptors so that it takes the cable from the tester ,and the adaptor board plugs direct into the jtag socket under test 
Jan 29 17:36:12 <AchiestDragon> could posablay get 3 jtag conectors per adaptor , on per edge with the cable on the other edge 
Jan 29 17:37:03 <AchiestDragon> may lead to the adaptor board beeing T shaped though
Jan 29 17:38:02 <beewoolie-afk> I'm not sure what you mean "on per edge with cable on the other edge"
Jan 29 17:39:49 <AchiestDragon> a right angle socket for the jtag connector , plugs direct into the jtag connector on the bord beeing tested, one on each  end of the pcb  would be a normal but a difernt one on each side also
Jan 29 17:41:32 <AchiestDragon> so  a 20 pin a 12 pin and a 14 pin ,   cannot be all on the same end of the pcb or the ones not in use may get in the way of other components on the board you want to plug it into 
Jan 29 17:43:06 <AchiestDragon> so with a T shaped pcb   there ca be one on each end of the - part and one at the bottom of the | part with the main cable running from the center at the top 
Jan 29 17:44:24 <AchiestDragon> shape of the pcb is not a problem as th place i will e using to make them can cnc route out any shape of pcb 
Jan 29 17:44:26 <beewoolie-afk> Are you suggesting that there be no cable, just a connector on the PC104 board?
Jan 29 17:45:03 <AchiestDragon> no a cable , but it runs to a board that has the diferent  jtag format connectors on the end 
Jan 29 17:45:35 <AchiestDragon> i recon there are at least 6 or 8 different jtag pinouts in use 
Jan 29 17:45:50 <beewoolie-afk> It is likely that that number could increase.
Jan 29 17:46:07 <beewoolie-afk> It would be best if the routing were handled by the FPGA
Jan 29 17:46:09 <AchiestDragon> so could the number of adaptors , just as easy 
Jan 29 17:46:41 <AchiestDragon> no , not when you have to use diferent pins for vcc and gnd on the jtag port 
Jan 29 17:46:45 <beewoolie-afk> It's impossible to make all combos.
Jan 29 17:46:58 <AchiestDragon> we can make the common ones 
Jan 29 17:47:04 <beewoolie-afk> Yeah, there isn't much we can do about that.
Jan 29 17:47:56 <beewoolie-afk> Seems like we could always build a custom cable from, say, the 20 pin header.  20 pin .10 pitch on one end and who-knows what on the other.  that seems to be the strategy used by the BDI2000.
Jan 29 17:48:15 <beewoolie-afk> Common ones can be handled with a simple, flat ribbon cable.
Jan 29 17:50:05 <AchiestDragon> any custom ones would mean a custom end , or that may be easy to impliment :) ( an adaptor with a patch aria )
Jan 29 17:50:45 <beewoolie-afk> The BDI cables use loose wires.  Makes it easy to configure a cable for whatever they need.
Jan 29 17:51:58 <AchiestDragon> maybe , but loose wires can cause problems at high speeds 
Jan 29 17:52:17 <beewoolie-afk> That's the price to be paid.
Jan 29 17:56:25 <AchiestDragon> think i can come up with a solution to the problem 
Jan 29 17:57:35 <beewoolie-afk> :-)
Jan 29 18:04:41 <[g2]> so beewoolie-afk can you look at the gerbers in linux ?
Jan 29 18:04:47 <[g2]> or dyoung-khfc or ka6sox 
Jan 29 18:04:57 <beewoolie-afk> I don't know about gerbers.
Jan 29 18:04:58 <[g2]> dunno if lennert does gerbers yet
Jan 29 18:05:19 <beewoolie-afk> I looked at the PS files, but I'm no 'spert in that area.
Jan 29 18:06:05 <AchiestDragon> ka6sox can , dont know if it was win or linux that he used 
Jan 29 18:07:45 <AchiestDragon> the .gts and .gbs are solder mask layers not silk screen as i mentioned earlyer  btw  
Jan 29 18:10:02 <AchiestDragon> the .gto top overlay  has been updated  today , the text on it is now formated right and connector names added  etc 
Jan 29 18:10:21 <AchiestDragon> not uploaded yet 
Jan 29 18:10:35 <AchiestDragon> just working on the bottom overlay atm 
Jan 29 18:13:38 <dyoung-khfc> gerbv works
Jan 29 18:14:17 <[g2]> dyoung-khfc what do I have to do to get the layers imported
Jan 29 18:16:14 <[g2]> what's the project file ?
Jan 29 18:16:31 <[g2]> Or do I just load the layers individually
Jan 29 18:18:25 <dyoung-khfc> Hmm, I dont quite rmemeber right now and gerbv is busted fromwhen I was migrating to xen.
Jan 29 18:23:49 <beewoolie-afk> dyoung-khfc: well, yes it does.
Jan 29 18:24:20 <[g2]> looks like gerbv *g* works well :)
Jan 29 18:25:54 <AchiestDragon> give me another 30 mins , and i will do a .ps of the pcb , but atm the ps print driver im using seems to make multipage outputs read as only a single page in some linux viewers
Jan 29 18:26:21 <AchiestDragon> i need to find my old driver that worked well for producing .ps files for linux 
Jan 29 18:26:26 <beewoolie-afk> AchiestDragon: try converting PS to PDF.
Jan 29 18:26:42 <beewoolie-afk> PDF viewers all around are better than PS viewers.
Jan 29 18:26:49 <AchiestDragon> yes 
Jan 29 18:28:22 <AchiestDragon> the old driver i was using was suposed to be a print to pdf , but only seemed to produce .ps output , since i had to reinsall xp because of a virus i cannot rmember where i got the driver from 
Jan 29 18:28:49 * [g2] loves the artwork (LINUX Compatable  http://www.openjtag.net) !
Jan 29 18:29:23 <dyoung-khfc> okay cool gerbv did the right thing for you?
Jan 29 18:29:25 <AchiestDragon> but the .ps was good enough for most and should convert to pdf , will have to find the converter again also 
Jan 29 18:29:46 <[g2]> dyoung-khfc yes... I think I just need to order the layers
Jan 29 18:30:26 <[g2]> dyoung-khfc I think need a way of marking up the gerbers and handling revision changes
Jan 29 18:30:26 <AchiestDragon> the gerbers are the important format as 99% of  pcb houses like it in that format 
Jan 29 18:30:52 <[g2]> AchiestDragon Oh absolutely
Jan 29 18:31:09 <[g2]> AchiestDragon do you also have a netlist and BOM ?
Jan 29 18:31:40 <[g2]> AchiestDragon I"m glad to see you put your name on there too
Jan 29 18:31:53 * [g2] is guessing that's _your_ name :)
Jan 29 18:31:56 <dyoung-khfc> [g2] which one is the proect file ?
Jan 29 18:33:17 <[g2]> dyoung-khfc heh Idon't think there is a project file :)
Jan 29 18:33:29 <[g2]> just gerbv *g*
Jan 29 18:33:33 <[g2]> *.g*
Jan 29 18:33:50 <[g2]> and turn all the layers _on_ or _off_
Jan 29 18:34:08 * [g2] forgot about wookey__ 
Jan 29 18:34:39 <[g2]> the Balloon Project has some tools on their Knoppix CD most of them are free
Jan 29 18:34:53 <dyoung-khfc> AHA....
Jan 29 18:34:57 <dyoung-khfc> okay I see stuff now
Jan 29 18:35:01 <[g2]> heh :)
Jan 29 18:35:16 <AchiestDragon> should be able to produce   protel dxp , orcad SDT Schematics , and autocad DXF schematics  
Jan 29 18:35:37 <dyoung-khfc> AchiestDragon: What software have you used to generate this?
Jan 29 18:35:53 <AchiestDragon> protel dxp 
Jan 29 18:36:01 <dyoung-khfc> Cool.
Jan 29 18:36:22 <dyoung-khfc> One of the shop guys downstairs from my office has been trying to get me on protel
Jan 29 18:36:49 <[g2]> AchiestDragon does that come with the parts library ?
Jan 29 18:36:56 <[g2]> or do you enter it
Jan 29 18:37:22 <AchiestDragon> i use it because it works , and does the job , would like to have a program with the same capabilaties for linux 
Jan 29 18:38:28 <AchiestDragon> there is a quite big parts lib and updates avalable on the web , but some parts you have to enter , but the editor is ok for that , its when you need to enter spice and simulation models forthe part thats a pain 
Jan 29 18:41:02 <AchiestDragon> the level translators for the jtag  buffers where the only par on this pcb i had to generate a schematic part entery for 
Jan 29 18:41:50 <[g2]> AchiestDragon what does Protel DXP cost ?
Jan 29 18:42:25 <AchiestDragon> an arm , leg , second morgage , mabe 2 wives and the car also 
Jan 29 18:43:39 <[g2]> $5K US ?
Jan 29 18:43:47 <[g2]> 50K ?
Jan 29 18:44:53 <AchiestDragon> £7000.00
Jan 29 18:45:10 <[g2]> 7K
Jan 29 18:45:19 <[g2]> US 
Jan 29 18:45:30 <AchiestDragon> was , , no uk£
Jan 29 18:45:54 <[g2]> 12K US ?
Jan 29 18:46:37 * [g2] wonders if there's a "network" license token
Jan 29 18:47:10 <[g2]> 1 seat - 10 dev's world-wide, but only one at at time
Jan 29 18:47:19 <[g2]> s/at at/at a/
Jan 29 18:47:19 <purl> [g2] meant: 1 seat - 10 dev's world-wide, but only one at a time
Jan 29 18:49:08 <AchiestDragon> a company that i knew of went bust , and i ended up with it , after a bit of nagging 
Jan 29 18:50:31 <[g2]> nod
Jan 29 18:50:54 <[g2]> so is it licensed to a box ?
Jan 29 18:51:43 <AchiestDragon> yes with online activation like xp 
Jan 29 18:52:49 <[g2]> so if we had some fast links it could be run locally, but the screen could be remote
Jan 29 18:53:37 * [g2] just mumbles aloud
Jan 29 18:54:02 <AchiestDragon> could be , im running it on my laptop as its the only xp box i have 
Jan 29 18:58:24 <[g2]> AchiestDragon can you tell my what the 10 layer are ?
Jan 29 18:58:45 <[g2]> .gbl .gbo .gbp gbs
Jan 29 18:59:12 <[g2]> the b is bottom
Jan 29 18:59:14 <[g2]> the t is tp
Jan 29 19:00:00 <[g2]> are the .gbs and gts the silkscreen layer
Jan 29 19:01:14 <[g2]> and the gd1 and the gg1 ?
Jan 29 19:01:17 <AchiestDragon> l  is layer (copper) , o is overlay ( silk screen ) , s is solder mask ( the green colouring  usualy) , the p is splder paste ( if you need it  used for a screen printing of the solder paste for the s/m components)m 
Jan 29 19:02:14 <AchiestDragon> the gd1  is drill guide , the gg1 should be drill size  info , may be other way round for those two 
Jan 29 19:02:52 <[g2]> Ok so this is a 2 layer board
Jan 29 19:03:01 <AchiestDragon> yes
Jan 29 19:03:07 <[g2]> THX for all the info btw
Jan 29 19:03:53 <[g2]> I'll be talking to some elementary kids about computers soon
Jan 29 19:04:10 <[g2]> this would be great to show them the layers and the colors and the zooms
Jan 29 19:05:05 <[g2]> maybe take in some tin foil sheet that they can cut out designs
Jan 29 19:14:35 <AchiestDragon> couple of sheets of clear asitate and some perminent markers , probablay be as much fun for them , although the parents may not like the laundry 
Jan 29 19:16:51 <[g2]> heh
Jan 29 19:17:33 <AchiestDragon> well the perminent marker does not wash out 
Jan 29 19:17:59 <[g2]> hence the perminent name :)
Jan 29 19:18:18 <[g2]> which compares with washable markers :)
Jan 29 19:18:53 * [g2] couldn't leave that one alone
Jan 29 19:19:06 <AchiestDragon> the hardest stain to remove is feric cloride 
Jan 29 19:19:34 <beewoolie-afk> AchiestDragon: where do you find ... FeCl?
Jan 29 19:19:47 <[g2]> beewoolie-afk he makes it!
Jan 29 19:19:58 <[g2]> at the pool
Jan 29 19:20:03 <beewoolie-afk> Probably FeCl2 or something. No periodic table handy.
Jan 29 19:20:05 <[g2]> :)
Jan 29 19:20:21 <AchiestDragon> it leaves a brown stain on cloaths , that after 3 to 4 months ends up beeing a hole 
Jan 29 19:20:27 <beewoolie-afk> Or is this a joke...FeCl.. fecal.
Jan 29 19:20:46 <AchiestDragon> FeCl  use it for etching copper from pcb's 
Jan 29 19:20:56 <beewoolie-afk> Ah.  I remember the stuff.
Jan 29 19:22:09 <[g2]> AchiestDragon is that where the mask it and put a wash over the copper to save the areas not to be etched away ?
Jan 29 19:22:24 <AchiestDragon> yes
Jan 29 19:22:40 <[g2]> kinda like printing
Jan 29 19:22:58 <[g2]> milling is the other version right ?
Jan 29 19:23:40 * [g2] guess they recover the etched copper to be reused (in both cases)
Jan 29 19:23:48 <[g2]> s/guess/guesses/
Jan 29 19:24:19 <AchiestDragon> photo etch , gerber to print on clear acitate , the pcb is covered in a photosencative material ,  put the acitate against the pcb , expose under uv light for about 60 seconds , develop , ...
Jan 29 19:25:30 <AchiestDragon> you end up with the photo coating were you need the copper , drop the pcb into FeCl, to etch , remove and wash , then strip the photo resist off, you then have the pcb with the copper on 
Jan 29 19:25:34 <[g2]> hence the "printed" part of the printed circuit board
Jan 29 19:25:55 <[g2]> nod.
Jan 29 19:26:33 <AchiestDragon> drill , and put in the through hole plates , , screen print the solder resist , then tin the pads , then screen print the overlay
Jan 29 19:30:38 <[g2]> so it's the gbl, gd1, gbp, gbs, and gpo
Jan 29 19:31:19 <[g2]> copper, drill, paste, mask, and silk screen
Jan 29 19:31:51 <[g2]> for both sides then sandwich together
Jan 29 19:32:21 <AchiestDragon> the paste is a seperate bit , its not used in the pcb manufacturing , its needed for the assembly line 
Jan 29 19:32:43 <[g2]> AchiestDragon Right!
Jan 29 19:32:56 <[g2]> that's done before the waveflow
Jan 29 19:33:00 <AchiestDragon> its a paste mask for the solder paste , so it can be screened on before the components are placed
Jan 29 19:33:08 <[g2]> and the pick-n-place machine
Jan 29 19:33:34 <AchiestDragon> then its i/r reflow for surface mount not wave soldered 
Jan 29 19:34:10 <[g2]> ah... infrared reflow for al the SMT stuff
Jan 29 19:34:35 <AchiestDragon> basicaly a convayor taking the pcb under some high power inferred lamps 
Jan 29 19:34:45 <[g2]> nod
Jan 29 19:35:46 <AchiestDragon> there was a us pcb company that suplyed a plasic sheet for top and bottom solderpaste when you ordered a pcb from them 
Jan 29 19:36:31 <AchiestDragon> so you could just put it on the board and spread the paste  like a simple silk screen print , to the prototype boards 
Jan 29 19:37:26 <[g2]> you just need an oven
Jan 29 19:37:52 <AchiestDragon> they offered them free with the boards , ,nice but there bords would cost more for me than i can get them localy , but was thinking of giving them a try ,but  lost the link to there site  
Jan 29 19:38:34 <[g2]> ah... you're across the pond right ?
Jan 29 19:38:40 <AchiestDragon> a toster overn that will do 240C should do the job so im told 
Jan 29 19:39:03 <[g2]> I think they have at sparkfun like that
Jan 29 19:39:32 <AchiestDragon> have one here but prefer the hot air gun (paint stripper ) method 
Jan 29 19:39:36 <[g2]> so with the RHoS compliance they are getting the pB out of the paste right ?
Jan 29 19:39:57 <[g2]> and everything else too
Jan 29 19:40:02 <AchiestDragon> yes ant that means higher temp needed for the solder 
Jan 29 19:42:02 <AchiestDragon> my soldering iron just needs a new tip , but have been offered both a wave soder machine and a i/r reflow machine cheap because of it , but not worth it for me if it wont cope with the  RHoS  stuff
Jan 29 19:42:25 <[g2]> nod
Jan 29 19:42:33 <[g2]> so you do contract designs ?
Jan 29 19:42:40 <[g2]> design / layout
Jan 29 19:43:36 <AchiestDragon> did do , not done any for 5 years now , health problems , but getting back into it 
Jan 29 19:44:21 <[g2]> well I hope you get very busy (meaning that your health is very good)
Jan 29 19:44:32 <[g2]> best of luck in that dept.
Jan 29 19:45:01 <[g2]> and I'll make sure I stop bugging you know so you can get some rest :)
Jan 29 19:45:02 <AchiestDragon> atm i canot ern more than £20 a week  or i loose the sickness benifit , but working towards setting up my own company this time , had enough of working for others
Jan 29 19:45:15 <[g2]> you're a few hours ahead of me :)
Jan 29 19:45:44 <AchiestDragon> i have sleep problems , like i tend to be up all night 
Jan 29 19:45:46 <[g2]> well I'm glad to hear you are getting better
Jan 29 19:46:39 <[g2]> all these type-A+ ppl
Jan 29 19:47:00 <[g2]> know wonder you guys get _so_ much stuff done
Jan 29 19:47:07 <[g2]> you're cheating
Jan 29 19:47:21 <[g2]> working all night
Jan 29 19:47:30 <[g2]> j/k
Jan 29 19:47:51 <[g2]> I had some insonmia in college
Jan 29 19:48:20 <[g2]> it took about 6-9 months to learn to settle down and fall asleep easily
Jan 29 19:52:27 <[g2]> AchiestDragon THX again for all the info. Pls sleep well and take care.
Jan 29 19:52:45 <AchiestDragon> k
Jan 29 19:53:00 <[g2]> I guess there's still a some "tombstoning" with the solder paste
Jan 29 19:53:29 <AchiestDragon> its not a big problem 
Jan 29 19:53:34 <[g2]> nod.
Jan 29 19:53:45 <[g2]> I guess it was more with wave flow
Jan 29 19:54:05 <[g2]> or maybe just more a while ago
Jan 29 20:37:27 <lennert> 04:38 here now..
Jan 29 20:38:23 <lennert> talk about insomnia
Jan 29 20:38:53 <AchiestDragon> :)
Jan 29 20:49:19 <[g2]> hey I'm going to be very soon
Jan 29 20:49:48 <[g2]> don't make be op myself to send you guys to bed :)
Jan 29 20:50:21 <[g2]> sweet dreams all
Jan 29 22:24:39 <ka6sox> ~seen AchiestDragon 
Jan 29 22:24:43 <purl> achiestdragon is currently on #brlcad #openjtag. Has said a total of 107 messages. Is idling for 1h 45m 50s, last said: ':)'.
Jan 29 22:25:00 <AchiestDragon> here
Jan 29 22:25:13 <ka6sox> I kinda expected you to be sleeping :)
Jan 29 22:25:27 <AchiestDragon> :)
Jan 29 22:25:36 <AchiestDragon> no 
Jan 29 22:25:57 <ka6sox> printed everything out now. and going to sit down over a cup of mocha and start tracing :)
Jan 29 22:26:02 <AchiestDragon> ok, well just found a pdf print driver 
Jan 29 22:26:25 <AchiestDragon> i got the silk screens sorted now , 
Jan 29 22:26:50 <ka6sox> I didn't print out the gerbers..just the schematic.
Jan 29 22:26:59 <AchiestDragon> and just uploaded a pdf of the pcb
Jan 29 22:27:07 <ka6sox> k
Jan 29 22:27:16 <AchiestDragon> and i have tidyed up the schematics today 
Jan 29 22:27:21 <ka6sox> k
Jan 29 22:27:38 <AchiestDragon> not upladed them yet , but will be on with that soon 
Jan 29 22:28:00 <ka6sox> okay I"m going to be busy with an online session soon.
Jan 29 22:28:05 <ka6sox> (in a bout 2 minutes0
Jan 29 22:28:41 <AchiestDragon> http://www.whipy.demon.co.uk/az-tag-1b.pdf
Jan 29 22:29:41 <AchiestDragon> although stupid program got a mesage at bottom of each sheet saying buy this program to remove this message , so will have to find another driver
Jan 29 22:29:48 <ka6sox> cool..htis one has the groundplane.
Jan 29 22:29:50 <ka6sox> :)
Jan 29 22:30:03 <ka6sox> is is possible to have it separate layers?
Jan 29 22:30:54 <AchiestDragon> that one should be on layer per page ,   top , bottom , top overlay .....  
Jan 29 22:31:53 <ka6sox> ya I see that now
Jan 29 22:32:02 <AchiestDragon> :)
Jan 29 22:32:12 <ka6sox> excellent...bbiaw...
Jan 29 22:34:29 <AchiestDragon> ty ,, although the pdf lacks the detail of the gerber files, and you need to realy view the pdf at over 400% zoom 
Jan 29 22:37:33 <AchiestDragon> btw  it can use the 32mb*16bit rams   so with 2 of those it can have 128mb of buffer space 
Jan 29 22:40:11 <AchiestDragon> reading the spec for thoes rams  it should also support the  64, 128, and 256mb * 16 bit ones , when they can make them that big , with no extra pcb mods , its when they get to  512mb that they need to start using pin40 as an extra address line 
Jan 29 22:41:19 <AchiestDragon> although doubt that we will need 2G bytes of jtag buffer space 
Jan 29 23:48:45 <ka6sox> probably not
Jan 29 23:50:16 <ka6sox> but 128MB I could see :)
Jan 29 23:50:37 <AchiestDragon> :)
Jan 29 23:52:40 <AchiestDragon> http://www.whipy.demon.co.uk/az-tag-1b-s.pdf ,,,, schematics ,, in colour , yet another stupid print driver that refuses to print them in landscape though 
Jan 29 23:52:59 <ka6sox> tis okay\
Jan 29 23:55:18 <ka6sox> 8 of 9 looks interesting.
Jan 29 23:59:04 <AchiestDragon> yes , on the schematics   theres the text  sp8 , sp32 ,sp 33 , sp41  , done , and cclk , there unused pins on the chips , and have been taken to a via , so that if there ever going to be needed it should be posible to solder a wire to them  
Jan 30 00:00:26 <ka6sox> good plan
Jan 30 00:01:06 <AchiestDragon> well got to be better than having to solder a wire to the pin of the chip 
Jan 30 00:01:45 <ka6sox> okay I'll print these out in the morning on my colour printer and then start cranking them into the VDHL code/UCF
Jan 30 00:01:55 <AchiestDragon> k
Jan 30 00:02:19 <ka6sox> not much different than what I was looking at earlier but easy to ready.
Jan 30 00:02:20 <ka6sox> er ready
Jan 30 00:02:25 <ka6sox> er read
**** ENDING LOGGING AT Mon Jan 30 02:59:57 2006