**** BEGIN LOGGING AT Tue Feb 07 10:59:57 2006
Feb 07 18:35:02 * prpplague expects beewoolie to show up shortly
Feb 07 18:39:13 <ka6sox-office> do you have a Crystal Ball?
Feb 07 18:39:25 <AchiestDragon> lol
Feb 07 18:47:29 <ka6sox-office> prpplague stands by a microwave oven and yells "Hurry!!!!"
Feb 07 18:48:28 <vmaster> yesterday he didn't show up before 22:00 my time - that's two more hours
Feb 07 18:48:48 <ka6sox-office> it *is* early here on the Left Coast
Feb 07 18:49:56 <prpplague> hehe he just sent out a flurry of emails
Feb 07 18:51:30 <lennert> ka6sox-office: i got the dual espresso hooked up
Feb 07 18:51:47 <lennert> ka6sox-office: now only to get 2.6 running
Feb 07 18:52:06 <lennert> double espresso, even -- sheesh
Feb 07 19:05:04 <ka6sox-office> yum!
Feb 07 19:05:12 <ka6sox-office> give me a Double Bartender!
Feb 07 19:05:30 <lennert> :D
Feb 07 19:17:57 <lennert> there's something wrong with the pci-x to pci-e bridge though
Feb 07 19:32:36 <ka6sox> bummer
Feb 07 19:33:28 <lennert> well, it's misprogrammed -- i'll sort it out, i guess
Feb 07 20:29:02 <AchiestDragon> hmmm , ok so the max jtag rate posible for a ppc runing at 2.2Ghz is 137.5 mhz according to ibm for the ppc970fx , think the i/o on the fpga will handle that no problems 
Feb 07 20:35:00 <AchiestDragon> and ram bandwith is not going to be a problem at that rate  , as a burst mode clock rate of 12mhz for ram access would give us a bit rate of  192mhz max jtag  so its down to what the fpga will be able to drive the thing to 
Feb 07 20:37:59 <AchiestDragon> given that the ram has a burst rate that clocks upto 100 mhz  then 1.6ghz jtag bit rate would be the max that is theoreticaly posable so  the limit is down to the i/o on the fpga  and the bufers 
Feb 07 20:49:53 <AchiestDragon> ok looks like 142mhz is the limit of the fpga inputs 
Feb 07 20:50:11 <ka6sox-office> the internal FPGA is only capable of 260MHZ
Feb 07 20:50:27 <ka6sox-office> so that will part of the limiting factor...BIG long shift registers.
Feb 07 20:50:55 <AchiestDragon> yes
Feb 07 20:51:24 <AchiestDragon> back on couple of hrs 
Feb 07 20:51:46 <ka6sox-office> as a practical limit we can expect 240mhz out of our chip with the 40mhz clock
Feb 07 20:53:59 <vmaster> heh, i wouldn't know what to do with 100mhz jtag clock... maybe write every byte twice, just because we can ;)
Feb 07 20:54:24 <ka6sox-office> think debugging and it becomes important
Feb 07 20:55:08 <vmaster> all i'm thinking is debugging
Feb 07 20:56:53 <vmaster> 100mhz would give 7mb/s download speed
Feb 07 20:57:46 <vmaster> how many i/o lines does the logic analyzer have?
Feb 07 20:59:50 <AchiestDragon> 16 + 1 clock but thats limited to the 100mhz ram bandwidth
Feb 07 21:00:23 <vmaster> it would make a nice platform for the embeddedtrace unit available on many arms
Feb 07 23:12:06 <AchiestDragon> yes , seem to remeber seeing one when i was looking for diferent jtag pinouts  , but think that used more inputs
Feb 08 04:30:19 <ka6sox> is it soup yet?
Feb 08 04:30:26 <lennert> soup?
Feb 08 04:30:37 <ka6sox> good morning Lennert
Feb 08 04:30:51 <lennert> 30 more minutes and it's morning here :)
Feb 08 04:31:00 <lennert> good $WHATEVER, ka6sox :)
Feb 08 04:31:09 <ka6sox> yep...what are you doin up at this hour?
Feb 08 04:31:29 <lennert> working on my huge accumulated backlog
Feb 08 04:35:30 <lennert> my chair being very very comfy is also keeping me glued to the pc
Feb 08 04:36:15 <ka6sox> uh oh...no sleep for you!
Feb 08 04:38:07 <lennert> indeed
Feb 08 04:48:24 <ka6sox> did you fix the PCI-X to PCI-E stuffa
Feb 08 04:50:51 <lennert> i'm on the right track
Feb 08 04:51:13 <lennert> found the docs for the bridge and read them
Feb 08 04:51:26 <lennert> still trying to get my brain wrapped around pci-e
Feb 08 04:55:34 <ka6sox> me too...even took a 
Feb 08 04:55:43 <ka6sox> VHDL class for PCI-X bridges
Feb 08 04:56:24 <lennert> well well
Feb 08 05:04:59 <lennert> pci core in vhdl is One Of Those Things that are on my infinitely long list of things to do
Feb 08 05:25:42 <[g2]> I was thinking we'd just build a miniPC card with the S3 and some CPLDs on it
Feb 08 05:25:51 <[g2]> then I could stick'em in the Lofts
Feb 08 05:26:08 <[g2]> and with a PCI/MiniPCI card for $19 we could stick'em in PCs
Feb 08 05:26:25 <lennert> it was said earlier that pci is out of the question
Feb 08 05:26:28 <lennert> as it won't work on laptops
Feb 08 05:26:32 <[g2]> but AchiestDragon is making such great progress that may be done already
Feb 08 05:26:57 <[g2]> many/most laptops have minipci for the wireless
Feb 08 05:27:15 <lennert> beewoolie wanted something usb
Feb 08 05:27:39 <[g2]> it was just an aside about the having a S3 with a PCI intf.
Feb 08 05:27:58 <lennert> i'm all for having a pci interfaced s3 :D
Feb 08 05:28:02 <[g2]> the "On day"...
Feb 08 05:28:07 <lennert> yeah
Feb 08 05:28:24 <[g2]> that's a "next month" project :)
Feb 08 05:28:29 <[g2]> or "next year"
Feb 08 05:28:40 <lennert> i hope sooner :-/
Feb 08 06:08:48 <lennert> the double espresso kind of boots
Feb 08 06:08:57 <lennert> now all i have to do is to make the ethernet work
Feb 08 06:09:25 <ka6sox> sweet
Feb 08 06:09:30 <ka6sox> too bad its soooo expensive
Feb 08 06:09:52 <lennert> yeah, well..
Feb 08 06:10:04 <lennert> yeah
Feb 08 06:11:47 <ka6sox> right
**** ENDING LOGGING AT Wed Feb 08 10:59:58 2006