**** BEGIN LOGGING AT Sun Feb 26 10:59:56 2006 Feb 26 17:56:54 ~seen beewoolie Feb 26 17:56:59 beewoolie was last seen on IRC in channel #openjtag, 15d 18h 4m 30s ago, saying: 'I thought they were going SA-SCSI so there'd only be a dozen or so pins.'. Feb 26 17:57:30 ~seen beewoolie-afk Feb 26 17:57:32 beewoolie-afk was last seen on IRC in channel #openjtag, 4d 12h 26m 57s ago, saying: 'On one device I've looked at, the largest packet is 128 bytes.'. Feb 26 18:53:57 anyone used the ft2232 for spi ? Feb 26 19:41:49 * p2-mate waves Feb 26 21:02:16 ~seen lennert Feb 26 21:02:24 lennert was last seen on IRC in channel #openjtag, 2d 9h 12m 27s ago, saying: 'hehe'. Feb 26 21:21:08 AchiestDragon, the CPLD and FPGA have separate JTAG chains...given that we are going to be using the FPGA is going to be fixed do we need that? Feb 26 21:23:56 p2-mate, do you know about the D-I interaction with Mac disks? Feb 26 21:24:55 ka6sox: yes. I have seen parted misbehaving Feb 26 21:25:08 ka6sox: I just erased the mac bootblock as I didn't need it anymore Feb 26 21:26:01 parted seems to not allow me to change the partition type to fd so that I can use it as a linux raid autodetect..if erase the Mac block will it allow me to use that type? Feb 26 21:26:17 ka6sox: yes. I think so Feb 26 21:26:30 p2-mate, thanks. Feb 26 21:26:32 ka6sox: not that familiar with parted Feb 26 21:26:40 me neither. Feb 26 21:26:44 ka6sox: but it does sometimes get confused Feb 26 21:26:50 I was going to do something ugly... Feb 26 21:27:16 put a CF card on the main chain as /boot and then have a mirrored root on Promise card. Feb 26 21:36:51 p2-mate, thanks for the help Feb 26 23:07:15 yop Feb 26 23:07:41 someone knows a chip embedded device that has a X server on it ? So basically u plugg the RJ45 and can export the display Feb 26 23:38:31 pong Feb 26 23:43:04 hiya lennert Feb 26 23:43:52 :) Feb 26 23:43:54 hi everyone Feb 27 08:31:29 hi Feb 27 08:31:42 lo Feb 27 08:42:15 hi Feb 27 08:42:45 yo...how goes it? Feb 27 08:43:01 ok ty :) Feb 27 08:43:21 cool Feb 27 08:43:31 I printed out the latest schematics. Feb 27 08:43:52 they look good. Feb 27 08:44:07 but I was wondering about the 2 jtag chains. Feb 27 08:44:33 3 Feb 27 08:44:43 arm , cpld , fpga Feb 27 08:45:08 are we going to reprogram the FPGA on the EP board? Feb 27 08:45:17 on the fly I mean. Feb 27 08:45:41 had not planned on it Feb 27 08:46:04 okay we could put the cpld and fpga on one chain then...save some space. Feb 27 08:46:25 the 20 pin ARM is important for debugging and bringing it up. Feb 27 08:46:30 the problem will be getting a 2.5v i/o for it on the epboard Feb 27 08:47:05 as the arm is a seperate jtag the cpld jtag is at 3v3 while te fpga is 2.5 Feb 27 08:47:08 I got a ARM debugger/programmer going to be at the office when I get in tommorrow to check out. Feb 27 08:47:15 got it. Feb 27 08:47:19 koo Feb 27 08:47:21 l Feb 27 08:47:33 ya...so I'll be able to check things out really well. Feb 27 08:47:39 ka6sox: what are you trying to build If I may ask ? Feb 27 08:48:30 p2-mate: http://www.whipy.demon.co.uk/geep.pdf Feb 27 08:48:42 a FAST jtag programmer/debugger with 32-128Channels of Logic Analyzer. Feb 27 08:48:46 aha Feb 27 08:48:52 p2-mate: and http://www.whipy.demon.co.uk/geep-sch.pdf Feb 27 08:49:30 this is the sbc control board for it , Feb 27 08:51:57 time for me to get some sleep here. Feb 27 08:52:04 I'll poke around tommorrow. Feb 27 08:52:17 k Feb 27 08:52:20 got names for the parts yet? Feb 27 08:52:31 not as yet Feb 27 08:52:36 (or did I miss that) (/me is really sleepy( Feb 27 08:53:05 okay I'll look forward to those Feb 27 08:53:23 we are looking at 208's for the s3's in 400 sizes? Feb 27 08:53:54 XC3S400? Feb 27 08:54:04 pqfp? Feb 27 08:54:10 yes Feb 27 08:54:23 okay I'll get a UCF percolating Feb 27 08:54:43 same for the GE boards or just the EP? Feb 27 08:54:52 same Feb 27 08:54:55 :) Feb 27 08:55:01 makes it easire Feb 27 08:55:02 er Feb 27 08:56:06 we can treat the expansion boards like SRAM and that will make the software easy. Feb 27 08:57:02 paged sram , theres more ram on the GE board than address space from the arm Feb 27 08:57:34 AchiestDragon: is the geep already produced or is it still in development as well ? Feb 27 08:57:38 yes...since we are going to have to multiplex A/D we can page it as well. Feb 27 08:57:59 ka6sox: my girlfriendwants to know if you have six feet for your 6 sox Feb 27 08:58:21 p2-mate: in development Feb 27 08:58:33 AchiestDragon, yes...mine, wife's and Son's Feb 27 09:00:53 although since the onboard fpga is beeing used to do the addressing for the flash and the expantion bus , the ram on the expantion board's could be paged by boards accross 4 banks of 64mb Feb 27 09:01:10 with the flash also Feb 27 09:01:17 ah.. Feb 27 09:01:47 I was hoping we could use a DMA channel to send raw frames out the ethernet Feb 27 09:02:03 (from the expansion boards) Feb 27 09:02:14 that way each expantion card can have a 256mb address space Feb 27 09:02:29 yes the fpga also has one of the dma chans Feb 27 09:02:44 the eide and cf cpld has the other Feb 27 09:02:44 how many bits of addressing 24 or 26? Feb 27 09:03:06 the CF only runs in PIO. Feb 27 09:03:15 but Eide can run in DMA Feb 27 09:03:19 yes Feb 27 09:04:25 the spi is going to have 2 onboard devices on it Feb 27 09:04:55 DDS and RTC? Feb 27 09:05:00 yes Feb 27 09:05:20 which RTC? Feb 27 09:05:31 not decided yet Feb 27 09:06:10 the ac97 will probablay be an analog devices device Feb 27 09:06:33 you looking for an SO8 devic on the RTC? Feb 27 09:07:02 so8 to so16 should fit np Feb 27 09:08:13 Maxim has some that are pretty nice. Feb 27 09:08:40 do we have access to the configuration eeprom onboard of the SoC? Feb 27 09:09:16 I'm thinking about where to store the Ethernet MAC and IP Address. Feb 27 09:09:16 would prefer a generic part that is made by a few manufactures Feb 27 09:09:25 okay... Feb 27 09:10:24 the config eeproms need a way to program them so got to look at that Feb 27 09:10:51 k Feb 27 09:11:17 I thougth they were done via the ARM jtag..but I wasnt' sure. Feb 27 09:11:27 i want to be able to ensure that the system can be initaly programmed up using only say a simple parallel port cable /programmer Feb 27 09:12:21 that will also have a pcb done for it Feb 27 09:12:25 if we can get a bootloader that is network savvy then we can load that up and serial into it. Feb 27 09:12:51 then load up the kernel and then a rootfs. Feb 27 09:13:05 (via tftp or some other faster means) Feb 27 09:13:06 but theres still the cpld's to program Feb 27 09:13:22 and the config eeprom for the fpga Feb 27 09:13:25 the CPLD and the FPGA can be programmed via the same parallel port. Feb 27 09:13:39 the config eeprom can also be done via the wiggler. Feb 27 09:13:44 (very small device) Feb 27 09:14:02 I'm sure that beewoolie/lennert can get that sorted. Feb 27 09:15:56 I'm comfortable that I can get the FPGA and CPLD done Feb 27 09:16:31 theres an open i/p core for the vga Feb 27 09:17:10 lennert did one too for his pong device (via the S3) Feb 27 09:17:10 i found a print out i had of it yesterday , although not looked though it yet Feb 27 09:17:49 vga is easy :) Feb 27 09:18:23 the hard bt is going to be deciding what colour scheam is best Feb 27 09:20:01 the colour dac is = to 8 leveles per colour so 3+3+3 bits and we only have 8 bits if muxing the vram data Feb 27 09:20:39 so take one bit away from green? Feb 27 09:20:41 but theres mor than enough ram so could use a single 16 bit access per pixel Feb 27 09:21:11 I leave that to you guys. Feb 27 09:21:33 i mean 64mb video ram , and only a requirement for 1.2mb at 1240*1024 in 256 colours Feb 27 09:22:24 so a 16 bit access would give us 512 colours with the other 7 bits unused , and take 2.4mb ram Feb 27 09:23:15 AchiestDragon: is the idea not equip the production boards intended for the jtag/logic analyzer application ? Feb 27 09:23:30 hey p2-mate, didn't know you were here too Feb 27 09:23:33 not equip VGA i mean :) Feb 27 09:24:06 theres alot of space in the fpga so (not saying we should but theres the posibilaty for ) adding windowing and sprites in hardware Feb 27 09:24:53 the idea is that the ep board should also work as well as we can as a sbc for other uses Feb 27 09:25:23 ic Feb 27 09:25:23 while providing us with the fast bus and dma for the ge board Feb 27 09:25:56 the ge board has a fpga , ram and ports for the anaizer and jtag tester Feb 27 09:26:12 hi lennert Feb 27 09:27:12 btw we can only have 2 usb ports , theres no spare i/o on the fpga for the extra 2 Feb 27 09:29:42 we can always use a hub external Feb 27 09:29:48 yes Feb 27 09:30:13 and not as important now we got eide onboard Feb 27 09:30:25 yes Feb 27 09:31:59 :) spaire connector space ,,, ps2 to rear or add audio jacks ? Feb 27 09:33:26 audio jacks Feb 27 09:33:29 its Geep! Feb 27 09:33:35 yes Feb 27 09:37:55 cya in aobut 6hrs. Feb 27 09:38:05 k , nn Feb 27 09:38:12 nn **** ENDING LOGGING AT Mon Feb 27 10:59:56 2006