**** BEGIN LOGGING AT Wed Jun 28 02:59:57 2006
Jun 28 03:01:08 <davidc___> anyone here familiar with OpenOCD / DLC5 Jtag + Arm?
Jun 28 03:04:27 <davidc___> or any arm embeddedICE jtag stuff?
Jun 28 03:14:38 <ka6sox> the guy who did it is vmaster I think
Jun 28 03:16:01 <davidc___> ok, thanks - I'm trying to do jtag bringup on an iPod - and having mixed success - trying to figure out if its due to the weird processor, a bad cable connection, a faulty board or sw bugs...
Jun 28 03:16:35 <davidc___> I can do some things - aka grab regs, soft reset [sometimes], step [if it feels like it] - but any attempt to read a memory word just results in a timeout
Jun 28 03:16:47 <davidc___> and I know the comms are ok because all the regs make sense.
Jun 28 03:17:22 <davidc___> aka - PC in the 0x40000000 / 0x20000000 range - which is where it should be [or in 0x0 range if I start it just outta reset]
Jun 28 03:19:03 <ka6sox> k
Jun 28 03:19:40 <davidc___> if anyone has any ideas where to go from here, I'd be happy to hear them :P - my next step is gonna be an LA + a scope to see if the signalling is sane
Jun 28 03:20:23 <ka6sox> might be the best answer
Jun 28 03:36:00 <davidc___> eh, and vmaster's the guy that wrote openocd?
Jun 28 03:36:25 <ka6sox> I think so
Jun 28 03:36:36 <davidc___> k, I'll bug im next time he's not idle
Jun 28 06:04:33 <vmaster> heh, yeah, i know, sleep is for the weak and such, but he came asking at 5:30am
Jun 28 06:04:50 <ka6sox> sleep is highly overrated
Jun 28 06:09:19 <vmaster> yeah, that's what i've been told, but i still feel highly addicted to it - like, every day, at the same time, and if i don't get it, i'm really angry
Jun 28 06:11:40 <ka6sox> makes 2 of us
Jun 28 07:49:46 <davidc__[2]> vmaster: I'm around
Jun 28 07:50:19 <davidc__[2]> vmaster: any thoughts?
Jun 28 07:52:26 <davidc__[2]> bah, missed him I guess ;)
Jun 28 10:36:05 <vmaster_> davidc__[2]: i'm back
Jun 28 10:36:58 <vmaster_> davidc__[2]: in case we keep missing each other: there's a forum for OpenOCD at sparkfun, and you can contact me by mail at Dominic.Rath <at> gmx.de
Jun 28 12:52:11 <M1a4U> lut
Jun 28 15:48:02 <davidc__[2]> vmaster - I'll give it one more shot on IRC - I'll try to be around about the time that you posted yesterday
Jun 28 15:59:52 <vmaster> davidc__[2]: heh, very unlikely - that was 8:15am, and i doubt i'll be up at that time tomorrow - excessive drinking is scheduled in 45 minutes ;)
Jun 28 16:00:46 <davidc__[2]> vmaster: yay! I'm around
Jun 28 16:00:48 <vmaster> davidc__[2]: make sure you have the latest OpenOCD sources (/trunk from svn), and run the OpenOCD with "-d -l <logfile>", and send me the log output
Jun 28 16:01:11 <davidc__[2]> yep, did a svn checkout
Jun 28 16:01:26 <davidc__[2]> gimme 10 secs and I'll get that for ya
Jun 28 16:01:42 <vmaster> hold on
Jun 28 16:01:51 <vmaster> the dlc5 lacks the nSRST line, right?
Jun 28 16:02:00 <davidc__[2]> yup
Jun 28 16:02:06 <davidc__[2]> just got the jtag wired
Jun 28 16:02:18 <davidc__[2]> the other issue is that there are two cores on this chip - one after the other in the jtag chain
Jun 28 16:02:19 <vmaster> make sure you have "reset_config trst_only"
Jun 28 16:02:32 <davidc__[2]> trst? - doesn't have that line either
Jun 28 16:02:46 <davidc__[2]> no HW reset - with the exception of me touching a testpoint ;)
Jun 28 16:02:48 <vmaster> oh, that use "reset_config none"
Jun 28 16:02:53 <davidc__[2]> yeah, thats what I've got
Jun 28 16:02:53 <vmaster> *then
Jun 28 16:03:11 <davidc__[2]> the reset isn't whats driving me nuts though - its the insane single stepping + its refusal to grab memory words
Jun 28 16:03:23 <vmaster> the first jtag_device corresponds to the device closest to TDO
Jun 28 16:03:32 <davidc__[2]> vmaster: yup 
Jun 28 16:03:46 <vmaster> what arm cores are on your chip?
Jun 28 16:03:52 <davidc__[2]> its two identical arm cores - arm7tdmis 
Jun 28 16:03:57 <davidc__[2]> er, 's
Jun 28 16:04:07 <vmaster> mhh, ok
Jun 28 16:04:12 <vmaster> well, then run it, and send me test output
Jun 28 16:04:23 <davidc__[2]> will do
Jun 28 16:05:01 <davidc__[2]> btw - is there any way to attach to both cores simultaneously? I'm also considering that one core might see the other as locked + reset it
Jun 28 16:05:11 <davidc__[2]> as I know theres interaction between the two going on in the bootloader
Jun 28 16:10:51 <vmaster> mhh, currently that would be only possible if you were in control of both nTRST and nSRST
Jun 28 16:11:12 <vmaster> i think i could enhance the OpenOCD so it halts both simultaneously
Jun 28 16:12:22 <davidc__[2]> I don't think it'd have to be identical - just so I can halt em one after the other
Jun 28 16:12:28 <davidc__[2]> then try single stepping one without the other interfering
Jun 28 16:13:49 <vmaster> in theory that should be possible - use two "target" lines in the config, and switch between the targets on the telnet interface
Jun 28 16:14:04 <vmaster> but i've never tested the OpenOCD with more than one core
Jun 28 16:14:11 <vmaster> so there might be some bugs lurking
Jun 28 16:14:20 <vmaster> okay, i'm sorry, but i gotta run now
Jun 28 16:14:26 <davidc__[2]> ah, tried that - got something about could not bind socket
Jun 28 16:14:29 <davidc__[2]> no problem
Jun 28 16:14:36 <davidc__[2]> I'll go source diving for that bug /w the socket
Jun 28 16:14:44 <davidc__[2]> make a patch
Jun 28 16:14:58 <vmaster> hmm, it could be the code that allocates different sockets for the gdb servers
Jun 28 16:15:03 <davidc__[2]> log here: http://david.carne.ca/ocd.log
Jun 28 16:15:12 <davidc__[2]> transcript here http://david.carne.ca/ocd.transcript
Jun 28 16:15:27 <davidc__[2]> and the result for mdw 0 is definitely wrong
Jun 28 16:15:38 <davidc__[2]> takes about 10 seconds too
Jun 28 16:15:52 <davidc__[2]> http://david.carne.ca/openocd.cfg is the config
Jun 28 16:16:03 <davidc__[2]> if ya get a chance to look at it - that'd be great, if not - no worries
Jun 28 16:16:05 <davidc__[2]> Many thanks!
Jun 28 16:16:35 <vmaster> okay, i'll look at it tomorrow, cya
Jun 28 16:16:49 <davidc__[2]> 'later
**** ENDING LOGGING AT Thu Jun 29 02:59:57 2006