**** BEGIN LOGGING AT Wed Aug 08 02:59:57 2007 Aug 08 13:03:37 anybody around? Aug 08 13:04:09 i'm finally getting the chance to try openocd Aug 08 13:05:05 hey Aug 08 13:05:19 i'm getting this error: number of discovered devices in JTAG chain (51) doesn't match configuration (1) Aug 08 13:05:36 i think it's some reset protocol mismatch Aug 08 13:05:38 which JTAG interface do you use, which target, and which version of the openocd? Aug 08 13:06:57 wiggler, arm926ejs, 2007-07-31 19:00 CEST Aug 08 13:10:39 drath: any ideas? Aug 08 13:13:51 well, it's a very low-level commuication problem Aug 08 13:14:14 the OpenOCD scans a fixed bit pattern in, and reads out the IDCODEs Aug 08 13:14:27 in your case it's receiving somewhat random data Aug 08 13:14:38 which arm926ej-s exactly? Aug 08 13:14:52 is it a geniuine wiggler? Aug 08 13:16:04 it is not from macraigor Aug 08 13:16:16 the SoC is marvell Aug 08 13:16:24 then it's not a real arm926ej-s ;) Aug 08 13:16:48 it just identifies itself as one, but marvell has a license that allows them to modify the original ARM ip Aug 08 13:17:20 are you on windows or on linux? Aug 08 13:17:25 lin Aug 08 13:17:34 did you build with ppdev support? Aug 08 13:17:37 yes Aug 08 13:17:47 did you remove the "lp" module? Aug 08 13:18:14 whoops Aug 08 13:18:31 it's not strictly necessary, but I've seen all kinds of weird behaviour with parallel ports Aug 08 13:18:54 where did you get your wiggler from - something you've built yourself? Aug 08 13:19:01 nah Aug 08 13:19:35 ok, now the number changed from 51 to 20 Aug 08 13:19:47 heh, that's equally bad Aug 08 13:21:07 is srst parport pin 2 or trst? Aug 08 13:24:32 as far as the software is concerned, that is Aug 08 13:25:46 pin 2 Aug 08 13:25:54 and it should not be inverted Aug 08 13:26:05 then where is srst expected? Aug 08 13:28:38 pin 6, and it should be inverted Aug 08 13:30:23 pin 6 unused here, and pin 2 == RST, going to nTRST through a transistor Aug 08 17:38:24 drath: still there? Aug 08 17:48:40 rd_: hi Aug 08 19:03:34 drath: according to the source code, it's the other way around -- pin 2 is srst, and pin 6 is trst Aug 08 19:05:21 pin 6 is unused on my wiggler thing Aug 08 20:33:37 sn9: hey Aug 08 20:33:54 sn9: let me double check that Aug 08 20:34:02 sn9: in only had a brief look at some old drawings Aug 08 20:35:45 i'm trying different possible cable definitions atm Aug 08 20:37:04 you are right, the code has ntrst at pin 6, nsrst at pin 2 Aug 08 20:37:10 so that's the "genuine" wiggler layout Aug 08 20:39:10 i'm comparing three schematics: Aug 08 20:39:10 http://www.k9spud.com/jtag/schematic-1.0.php Aug 08 20:39:10 http://www.diygadget.com/images/jtag/wiggler/wiggler.buffer.jtag.fta.schematic.jpg Aug 08 20:39:10 http://wiki.dns323.info/_media/hardware:dns-323-jtag.pdf?id=hardware%3Ajtag&cache=cache Aug 08 20:39:33 there's a great deal of confusion Aug 08 20:39:55 the definition labeled "wiggler" in the OpenOCD source is known to work with original wigglers and the ARM-JTAG from Olimex Aug 08 20:40:18 it is also the one used by Amontec's chameleon in its Wiggler configuration, but only by the latest update Aug 08 20:40:29 I think this one is the "original" layout Aug 08 20:40:39 but you can easily add a layout of your own Aug 08 20:41:53 the board has the same jtag pinout as the dns323, i.e. only one type of reset line Aug 08 20:42:06 http://wiki.dns323.info/hardware:jtag Aug 08 20:42:24 the cable is the diygadget one Aug 08 20:43:42 according to the debug log, parport_reset() always gets called only once, to deassert both lines Aug 08 20:44:34 after that, "TRST asserted" always gets reported three times Aug 08 20:45:34 i did not use a resistor on the EN line -- plugged it straight into Vcc Aug 08 20:46:35 drath: any ideas? Aug 08 20:49:11 if i mark pin 2 as a non-inverted signal, the device stays in a halted state Aug 08 20:53:16 TRST asserted is also called when the TMS sequence that moves to Test-Logic-Reset executes Aug 08 20:53:56 you could try old_amt_wiggler Aug 08 20:54:19 that one has D0 (Pin2) as an inverted nTRST signal Aug 08 20:55:11 use "reset_config trst_only" in the .cfg file Aug 08 20:56:43 { "wiggler_diygadget", 0x80, 0x00, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80 }, Aug 08 20:56:43 { "wiggler_diygadget2", 0x80, 0x01, 0x02, 0x04, 0x08, 0x00, 0x01, 0x80, 0x80 }, Aug 08 20:57:00 those are what i'm trying now Aug 08 20:57:52 no luck so far Aug 08 20:58:55 well, that's the main problem with parallel ports - you never know why they fail Aug 08 20:59:21 have you been able to use this PC's parallel port with some other paralle port JTAG software? Aug 08 21:00:18 have not tried Aug 08 21:00:54 i know pin 2 is responsive, because if i don't invert it, the device stays in a halted state Aug 08 21:01:54 i know pin 2 is responsive, because if i don't invert it, the device stays in a halted state Aug 08 21:03:25 did you try lowering the JTAG speed (higher jtag_speed divisor) Aug 08 21:03:46 i thought that was ignored for parport Aug 08 21:04:56 no, it's used to output the same pattern (jtag_speed+1) times, effectively diving the maximum frequency Aug 08 21:06:44 how much higher should i make the jtag_speed? Aug 08 21:07:20 1 or 2 Aug 08 21:07:46 that results in a frequency of 100 kHz or so Aug 08 21:24:27 how do i tell whether to use push_pull or open_drain? Aug 08 21:24:48 in your case it doesn't matter Aug 08 21:24:57 because? Aug 08 21:24:59 that's for cables that allow the reset lines to be either of both Aug 08 21:25:30 how do i tell the difference between the reset line types? Aug 08 21:25:31 in your case the reset line is open-drain, which inverts it Aug 08 21:26:10 ah, ok Aug 08 21:48:14 i'm off for today, bye sn9 Aug 08 21:48:22 ok **** ENDING LOGGING AT Thu Aug 09 02:59:57 2007