**** BEGIN LOGGING AT Wed May 06 02:59:57 2009 May 06 08:30:32 Anyone got a copy of ARM Architecture Reference Manual ARMv7-AR Edition DDI 0406 May 06 08:34:16 it's nda'd May 06 08:40:07 crap May 06 08:41:51 are you looking for something in particular? May 06 08:59:31 yes, all of the addresses for things like CPU_ID which might be useful for jtag debuggers, etc. So I can properly work on Cortex_A8 support for openocd. The Cortex_M3 document has them in it. But they are different on the A8. May 06 09:04:10 grr May 06 09:04:11 also check this http://www.arm.com/products/solutions/coresight_spec.html May 06 09:04:11 and http://www.arm.com/products/solutions/ADISpecification.html May 06 09:04:44 roxfan, I have all those. May 06 09:04:54 hmm, not enough? May 06 09:05:35 nope. eg. the cortex_a8.h defines: #define CPUID 0x54011D00 May 06 09:05:52 but that address appears nowhere in any of those specs May 06 09:12:02 is it an address? maybe it's the value May 06 09:23:12 its an address May 06 09:23:22 I think. May 06 09:23:40 well, i can't find anything matching in any doc May 06 09:23:49 Its an address for M3 May 06 09:53:55 Question. I have an ARM946 which appears to identify itself, over jtag, as an ARM1068E-S, soft macrocell May 06 09:54:14 Seeing as there is no such thing as an ARM1068... May 06 09:56:22 Various info at http://gist.github.com/107309 May 06 10:00:11 Strontium: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Babififh.html May 06 10:30:08 Circuitsoft: thanks for the link May 06 10:30:14 Does that help? May 06 10:30:20 Yes May 06 10:30:51 Came across it while digging through ARM docs trying to figure out what might be wrong with my JTAG setup. May 06 10:35:16 Strontium: I don't really know that much about JTAG. Any ideas what types of misconfigurations might lead to shifted bits in the returned IDCODE? Is that possible? May 06 10:37:14 Well its possible. But I couldn't really say what sort of errors. Possibly a state machine error. JTAG is a loop, so you need to clock out as many bits as you recieve. If you clock out too many or too few bits your result will be shifted by the under/over run. Is my guess. May 06 10:37:51 Its basically a big shift register and you clock bits in one end and get them out the other. (This is the data register). May 06 10:38:42 What determines the IR length? May 06 10:43:25 The specification. May 06 10:44:02 Will all ARM946e cores have the same IR length? May 06 10:44:12 One way to test it. Clock out heaps of zeros. Many more than a reasonable IR length. You should recieve zeros. Then clock out ones. Count how many zeros you recieve before your first 1. this is the IR length. May 06 10:44:42 I would think so. But the datasheet for the device should say. May 06 10:45:29 Jtag is normally part of the core architecture. Although vendors can change it, especially soc vendors. Because they might add functionality. May 06 10:45:51 This scan chain has two devices. If I specify IRLen of 8 for both of them, OpenOCD does not complain about IR length mismatch. Otherwise, it does. May 06 10:47:57 I saw somewhere someone did an ir length scan somehow with openocd. I dont know how to do that though. May 06 10:48:20 search the mailing lists for it. It was a scan of vaious dr lengths for each possible ir May 06 11:04:25 After running an "irscan" command, I get May 06 11:04:28 couldn't read the requested number of bytes from FT2232 device (1 < 2) May 06 11:04:30 couldn't read from FT2232 May 06 11:59:20 Circuitsoft: sorry, i dont know. :( Ive only started hacking on openocd myself. May 06 13:55:26 Is the way that openocd handles the arm regs info just saving their values in that context[16] ?! May 06 13:56:10 I mean, this saves the values from r0 to r15, but we still have cspr and spsr, right ? May 06 13:56:26 isn't there any struct in the code to save this ? **** BEGIN LOGGING AT Wed May 06 17:43:21 2009 May 06 18:54:54 Strontium: 54xxxxxx address is apparently omap3-specific **** ENDING LOGGING AT Thu May 07 02:59:57 2009