**** BEGIN LOGGING AT Sat Jun 29 02:59:59 2013
Jun 29 03:15:00 <ka6sox> yes
Jun 29 03:15:25 <ka6sox> interesting..must have made a misteak
Jun 29 03:15:28 <ka6sox> let me look
Jun 29 04:31:57 <ka6sox> jj2baile, I don't see an issue with the connectors
Jun 29 04:32:06 <ka6sox> they are all labelled correctly
Jun 29 04:41:42 <jj2baile> ka6sox: Alright.
Jun 29 04:42:29 <jj2baile> i'm just not quite sure what GPIOs the TDO, TDI, TMS, TCK, signals are connected to
Jun 29 05:21:57 <ka6sox> aha...
Jun 29 05:22:00 <ka6sox> they aren't
Jun 29 05:22:14 <ka6sox> this is where you and I need to meet to discuss the interface :)
Jun 29 05:22:32 <jj2baile> oh ok. makes sense now :)
Jun 29 05:23:11 <ka6sox> we need to decide if we use the serial port stuff that the PRU has
Jun 29 05:23:17 <ka6sox> or we use parallel port stuff...
Jun 29 05:23:26 <ka6sox> I've wired it so that we can do boht
Jun 29 05:23:35 <ka6sox> take a look at pg 3
Jun 29 05:23:51 <ka6sox> that is a amorphous BLOB....called a CPLD
Jun 29 05:24:12 <jj2baile> Yeah
Jun 29 05:24:13 <ka6sox> I can create a Parallel In/Serial OUT FIFO or whatever we need.
Jun 29 05:30:45 <ka6sox> its just glue...the PRU has to assemble and keep track of whats happening
Jun 29 05:35:03 <jj2baile> Alright. wait, so are you thinking of having the signals go through the CPLD first, or directly connected to the GPIOs connected to the PRU?
Jun 29 05:35:35 <ka6sox> there are GPI OR GPO's on the prus
Jun 29 05:35:48 <ka6sox> one PRU will be a TX and the other a RX
Jun 29 05:35:57 <ka6sox> since we need full duplex
Jun 29 05:36:25 <ka6sox> (and the connections are in OR out only
Jun 29 05:36:28 <ka6sox> )
Jun 29 05:36:54 <jj2baile> ok
Jun 29 05:37:43 <ka6sox> read up on parallel and serial comms with the PRU (offboard)
Jun 29 05:41:11 <ka6sox> there is a serial output with 2 FIFOs and a 2X bit RX fifo
Jun 29 23:47:24 <vvu> av500: got spl on board
**** ENDING LOGGING AT Sun Jun 30 02:59:58 2013