**** BEGIN LOGGING AT Sat May 21 02:59:58 2016 May 21 03:39:16 * ZeekHuge has received GSoC's Welcome Package :D :D :D May 21 03:39:53 well, not technically. It at my relatives's house, here in the same city. So I just need to go and grab it. May 21 03:40:29 One question . We will be receiving some bb.org laptop stickers too na ? with the hardware ? May 21 05:00:12 Good evening Wormo ! May 21 05:47:55 hmmmm May 21 06:05:23 hi ZeekHuge May 21 06:12:40 Hey Wormo ! do you have some time ? or about to sleep ? May 21 06:13:06 I can stay up a while longer, it's not even midnight May 21 06:13:24 got some questions to discuss? May 21 06:13:45 yes .. May 21 06:13:50 on the datasheet May 21 06:14:15 ok go for it May 21 06:14:41 datasheet (dsheet) = http://cds.linear.com/docs/en/datasheet/223876fa.pdf quick guide (QG) = http://cds.linear.com/docs/en/demo-board-manual/dc782A.pdf May 21 06:15:00 so on the QS page 8 May 21 06:15:05 *QG May 21 06:15:26 the jumper 2 (J2) May 21 06:15:46 pin 1 and 2 are about the EEPROM May 21 06:16:02 so, its like for auto-detection on plug in. May 21 06:16:10 I guess, so need to worry about it. May 21 06:17:18 pin 39, is to give the clock input to latch the output. May 21 06:17:44 so, the input will be from the PRU side. May 21 06:17:51 yes May 21 06:18:03 and it will be basically sampling rate. May 21 06:18:48 The point where i was confused is the J3 . The Clock input. May 21 06:19:14 as is on page 4 diagram. Encode Clock May 21 06:19:44 I discussed it with ds2 . And he suggested me to go through the circuit. May 21 06:19:45 go ahead, and I'm going to look at other schematic a minute, since I think OE is to enable operation not a clock May 21 06:20:07 since on page 4 is says to ground OE May 21 06:20:32 ahh ? May 21 06:20:35 J3 ? May 21 06:20:38 jumper 3 ? May 21 06:21:02 J2 39 May 21 06:21:26 sorry I was behind... "yes" was don't worry about EEPROM May 21 06:21:49 but pin 39 may not be what you think May 21 06:22:10 at least what I think you said May 21 06:23:18 pin 39 is connected to OE1 and OE2, and as i in the datasheet of the latch, it make the output = input when its active. May 21 06:23:35 ok then I missunderstood what you said at firsts May 21 06:24:03 when you said "latch" I thought you meant like clocking in data May 21 06:24:36 latch = the part, U2 May 21 06:25:02 it is enable, so you turn it on to be able to clock in data with the clk pin, so let's talk about that like you wanted to May 21 06:26:17 Wormo: is there a way to share and edit a pdf. May 21 06:28:34 Unfortunately the tool I use for pdfs only does one page at a time May 21 06:29:15 so I have to take it apart with pdfseparate, then edit the page I want... May 21 06:29:55 I suspect there's a more convenient way to do it May 21 06:30:11 Wormo: did you receive an invitation from dochub ? May 21 06:30:18 just now? May 21 06:30:22 yes May 21 06:30:30 I just shared the pdf with you. May 21 06:30:34 I'll check then May 21 06:33:49 trying to open it, getting server error :( May 21 06:34:15 it = the pdf after signing in w/ google accountn May 21 06:34:51 Unexpected server response (401) while retrieving PDF "https://dochub.com/api/sources/26721339.pdf?page=1&per_page=100". May 21 06:34:54 I mailed you on the vctlabs email address. May 21 06:35:11 yes I used that link May 21 06:35:32 should I mail you on your google acc ? May 21 06:35:41 no that was the one May 21 06:35:46 I don't have gmail May 21 06:35:56 okay. May 21 06:36:07 this is what I use for google docs, not sure why not quite working May 21 06:37:20 https://dochub.com/zubeentolani/oMxbVK/223876fa?dt=ibyudir9ygg3rpmg May 21 06:38:00 same May 21 06:38:08 ahh .. May 21 06:38:49 on the other hand if what you want to talk about is details of that circuit near J3 for signal quality, I'm not the right person to talk to anyways May 21 06:39:51 on the J2 ? May 21 06:40:21 oh you're asking why it goes to J2 pin 3? May 21 06:40:22 about J3, i will first dive into the circuit and ask for help from ds2 . May 21 06:40:50 what's the question about J2? May 21 06:40:54 Okay .. just a second, its getting hoch-poch May 21 06:40:58 ok May 21 06:44:12 basically what I get out of a schematic like this is the software integration perspective, I can see what bits from the ADC come out on what pins on J2 and that you want to ground pin 39 to enable output May 21 06:44:32 pin 39 of J2 that iss May 21 06:51:57 So, as you said, that you would be helping me with the datasheets, so here is all what I have understood as of now, about the board.(all details with reference to circuit page 8 on guide manual http://cds.linear.com/docs/en/demo-board-manual/dc782A.pdf ) So, basically its the J2 where the pru will be connected, as it is where the data pins come out. So most of the pins are ground pins, then there are 10 data pins (the board circuit is the general May 21 06:51:58 circuit, we will be having only 10 data pins as the part we ordered is 10bit). and the other pins on the J2 are : 1> to the EEPROM (do not need to worry for now) 2> The pin 39 on j2, since its connected to OE1 and OE2 (low active ) of the part number 74VCX16373MTD ie U2, through a XOR gate, active OE pins will bring the next data from the ADC, to the output data pins on the J2. so this 39 pin on J2 will be connected to the PRU and pru will toggl May 21 06:51:59 e the pin according to the required sampling rate. May 21 06:52:35 Wormo: ^^ May 21 06:53:00 J3 is the clock for toggling the sample in May 21 06:53:57 the OE are going to buffer part, you want the buffer turned on to pass the signals thru May 21 06:54:34 So , we just need to keep the OE active always ? May 21 06:54:39 Yes May 21 06:54:43 and dont need to toggle it. May 21 06:54:49 okay, gotcha. May 21 06:55:04 I might be wrong about keeping it low though, might be high, work through the logic with the xor May 21 06:55:37 yep okay. May 21 06:56:24 oh ! and about other jumpers May 21 06:56:44 buffer parts are good for both level shifting and keeping delicate parts safer, you see those a lot, like U2 May 21 06:58:17 okay. Other jumpers like JP1 and JP2 will both be ground May 21 06:58:49 JP3 will be on VDD as it will allow the input to have amps +- 1V May 21 07:00:07 and JP4 on 1/3VDD to enable the clock duty cycle stabilizer and output data as offset binary form. May 21 07:00:23 reference : page 11 datasheet http://cds.linear.com/docs/en/datasheet/223876fa.pdf May 21 07:00:26 Wormo: ^^ May 21 07:02:06 the jumper JP 1, 2 , 3 and 4 are SHDN, OE, SENSE and MODE respectively May 21 07:03:14 yes I see that on p11, a very useful page May 21 07:03:39 Is the above configuration correct ? May 21 07:04:42 checking, VDD for JP3 looks good for selecting range May 21 07:05:23 and yes 1/3 VDD looks like a good setting for mode May 21 07:05:45 okay May 21 07:07:53 So what i need to do next it to dive in the circuit connected to the 'Encode Clock' pin, ie J3 Clock input. May 21 07:07:54 either offset binary or 2's complement would work for output mode, just make sure your software knows which is selected so it knows whether to subtract the offset or not May 21 07:09:14 interpretation wouldn't need to be done by PRU but later by the kernel driver of course May 21 07:09:40 okay, offset is a simpler form, so I in the starting days, I'll just go with the offset form . and that will be the device driver's part to do all this mathematics on the data ? right ? May 21 07:09:43 yes. May 21 07:11:24 Wormo: ^^ it will be device driver's work na ? to do that data conversion ? May 21 07:11:34 or offload subsystem's ? May 21 07:11:47 I guess device driver's May 21 07:12:43 device driver responsibility to interpret data, other parts are just twiddling bits not interpreting May 21 07:13:05 okay. one silly question. I'll be receiving laptop sticker too na ? with the hardware ? :D May 21 07:13:23 heh I dunno, that's a jkridner question May 21 07:15:34 ADC is still to not shipped na ? I'll request jkridner to send some stickers along. May 21 07:15:39 I think you're right that offset binary is simpler to deal with in C because of 10 bit values, they'd need sign-extended to 16 bit otherwise May 21 07:16:07 ADC is going straight from digikey I believe, so no chance to put in stickers May 21 07:16:23 more likely coming with BBB May 21 07:17:19 * ZeekHuge really wants stickers ;( May 21 07:17:37 * ZeekHuge and a t-shirt if possible :P May 21 07:18:32 Wormo: Okay so, its just the clock thing to be dealt with. May 21 07:19:35 you've got a signal generator at lab to borrow for the analog in? May 21 07:21:37 yes . 1MHz max and variable amplitude. May 21 07:22:10 ahh .. 1MHz or 10MHz, i dont remember actually. but either 1 or 10. May 21 07:22:18 probably 10MHz May 21 07:22:21 ok May 21 07:22:53 Wormo: What time is it there ? May 21 07:23:52 about 00:20 May 21 07:24:25 so did you see the impact of clock stabilizer, advantage and disadvantage? May 21 07:24:31 oh . its 1254 here. May 21 07:25:02 must be 00:24 then, I don't have ntp running at the moment May 21 07:26:11 about clock stabilizer ... No. Will look into. May 21 07:32:02 Wormo: okay so to read about the clock stabilizer and the encode clock pin. Will that be all for now ? May 21 07:32:09 sure :) May 21 07:32:49 Wormo: okay then. will be leaving now. Thank you :). Have a good night ! Will see you tomorrow ! May 21 07:32:59 see you tomorrow May 21 15:05:18 I know its a silly question, but I think its cool for developer to have stickers on their laptops. So the question : Are there bb.org laptop stickers along with the shipped hardware ? ... wait, more silly question to come .. ahh ... is there any chance for something like a bb.org t-shirt ? May 21 15:11:17 Sounds like you have too much time on your hands ;) May 21 15:11:45 Not that stickers aren't a good thing in general - all the ones that turn up in my house disappear for some reason... May 21 15:12:21 How's life anyway? I'm a fairly large bisection for some really old hardware (hence mostly bored) May 21 15:17:00 Hey jic23b ! .. ahh.. Sorry. May 21 15:17:09 xmodem doesn't get any quicker. I'm sure I once figured out how to do ethernet uploads of kernels to this particular bored, but I put it on a souceforge wiki page they deleted ages ago. May 21 15:17:16 I was working on the datasheets of the ADC EVM May 21 15:17:29 and how to get it connected to the PRUs. May 21 15:17:34 ZeekHuge - deliberately not pinging you as I'm just wasting time and didn't really want to waste yours! May 21 15:17:51 yeah, that clock side of things looks a little odd for that ADC board... May 21 15:19:06 yep. So I am still not sure with it (am reading more), but it seems like a square wave will do the clock thing there. so one of the pru's GPO can be used for the purpose. May 21 15:19:53 yeah, so why have they added the complex description? May 21 15:20:20 We use similar 500ksps linear parts at work all the time and the clocking is dead simple on those. May 21 15:20:58 (says the guy who relies on the fact someone got the little cpld wired up to them right ages ago and has never poked it) May 21 15:21:32 meh - can probably just use a couple of signal generators and stick a logic analyser on the output of this to see if it's working which is nice I guess. May 21 15:26:52 but that can be only after the hardware arrives. May 21 15:29:43 zeekhuge - true enough. Plenty to mess with in the meantime though (once your exams are done!) May 21 15:29:55 Can any of the mentors tell me if the packages with our BBB's have been sent by the org? May 21 15:30:02 av500, ^^ May 21 15:30:06 hey jic23b ! May 21 15:30:32 _av500_, ^^ May 21 15:31:53 hi chanakya-vc May 21 15:32:12 They are almost done. I have 2 more practical exams (not much of preparation, but consumes time as I will have to be present in the college and 'Z' is the last alphabet ;)) and they are on 25th and on 26th May 21 15:33:13 I'm glad we never had any of them in the course I did. Practical skills? What are they for? :) May 21 15:34:02 jic23b, They are a huge pain.I have to make all sorts of oscillators and stuff in my electronics lab May 21 15:34:54 During my exams :( I think this lab system is peculiar to India or something.What do you think ZeekHuge ? May 21 15:35:07 I did information and electrical sciences (no longer exists even here) which meant nothing so dirty as actual electrical things :) May 21 15:36:30 I think most other places assess practical skills (such as they are) in longer term projects... May 21 15:36:46 jic23b, Yes,horrible to work with Induction and synchronous motors and getting to start them at full load half load and whatnot. May 21 15:37:04 They are sometimes cool ! when a real device is involved, but mostly its just another form of "Theory", as most of the focus is on making 'file' and writing the steps and the viva that involves non-practical-related questions. May 21 15:37:48 yikes - though we did have a practical session on a real gas engine once which was fun. Dread to think how much gas it was burning. May 21 15:39:02 jic23b, Yes,here as an electronics and communications engineer,some portion of my course is stuff that I will never actually use in my life :( May 21 15:39:51 No wonder all of us want to pursue masters abroad,right ZeekHuge? ;) May 21 15:40:33 either abroad, or at IISc. May 21 15:40:51 don't worry - everyone studies stuff they will never use. Anyone still working on frame relay networks? May 21 15:41:45 ZeekHuge, Are you into pure science?IISc is only into that I believe? May 21 15:42:27 ZeekHuge, And do you have any idea about the packages that the org is going to send us? May 21 15:42:55 jic23b, I know what a relay is ;) No idea about a relay network : ) May 21 15:43:11 IISc has the best in class Computer Science course all over India. And it ranks, I guess 55 all over the world. May 21 15:43:26 chanakya-vc: no idea about the packages. May 21 15:44:22 Not sure most CS masters are actually terribly useful - can learn lots of totally useless stuff :) May 21 15:44:37 ZeekHuge, Ohh..by IIS'c you mean Indian Institute of Science right?I didn't know they had a computer science program.. May 21 15:44:58 I'd go for a research heavy course if you can. May 21 15:45:51 jic23b, Well I aim to pursue masters in CS from an Ivy league college in US.It's sort of a childhood dream. May 21 15:46:31 That's fair enough. May 21 15:47:18 My wife's family are from Pune. She came to the UK to do a PhD and her brother went to the States. May 21 15:47:40 Ended up doing Phd in Colorado but got around a fair bit first through various internships etc. May 21 15:48:07 chanakya-vc: https://en.wikipedia.org/wiki/Indian_Institute_of_Science, see the Degree section, 4th para. May 21 15:48:07 KeyError: u'extract' (file "/usr/local/lib/python2.7/dist-packages/sopel/modules/wikipedia.py", line 87, in mw_snippet) May 21 15:48:38 Found a bug :D May 21 15:48:41 Father in law is retired lecturer - so have had many a conversation with him about the difference between the Indian and British education systems. May 21 15:48:52 ZeekHute - now you get to fix it ;) May 21 15:48:58 ZeekHuge... May 21 15:49:16 :) May 21 15:49:20 jic23b, Ohh ..wow! May 21 15:49:38 International world these days ;) May 21 15:50:03 I've never moved more than a few hundred miles form where I was born ;) - mind you we do have little places like London in that radius. May 21 15:50:20 jic23b, Actually there isn't much difference in the education systems.I mean educatiion system in India is based on the British model May 21 15:50:52 yeah, but scaled up and about 40 years behind changes that happened here on the whole (not all of which were good) May 21 15:50:53 jic23b, I have been to London.Beautiful place.Though I was very small then. May 21 15:52:58 jic23b, The major difference I guess is that in the west especially US,many of the good colleges are all privately funded.Where here in India,most of all good colleges are Government controlled. May 21 15:53:49 So Government==slow pace of change in syllabus and policies(except the IIT's) May 21 15:54:53 Almost all UK are government funded as well... May 21 15:55:20 More independent though - they can within reason teach what they like... May 21 15:56:54 A few keep up with the US ones. Still nasty government here at the moment, aren't exactly welcoming! May 21 15:57:25 No idea on CS best places though - came from Engineering background (which in this country is pretty separate) May 21 15:57:56 jic23b, That's the reason Oxford and Cambridge are world renowned. : ) : ) May 21 15:58:50 May 21 15:59:18 Actually as you move on in education through masters and beyond the institution doesn't matter as much as who you are working with. May 21 15:59:42 Good and bad accademics in lots of places... May 21 16:00:13 Not so important in taught masters but if you are tempted to do a research degree that gets tricky. May 21 16:01:06 jic23b, Haha,True.But most of these institutions have the best profs.My dream==stanford and work with Andrew Ng.He is so good with Machine learning and stuff May 21 16:02:29 founder of baidu and coursera. May 21 16:03:01 I'm never sure on the superstar profs. Often they end up with too many students to actually interact sensibly with them. Some labs are setup well for this (have a good bunch of people inbetween the prof and students), others are 'sweatshops' where the students rarely actually learn to think for themselves. May 21 16:03:26 Come across a few people starting again having burnt out in such a lab. May 21 16:04:10 oh goody - my board got broken somewhere in the 4.5 cycle. May 21 16:05:08 even worse with the profs with a few 'side' interests... Either the students end up working for 'free' for the side interests or they never see the prof. May 21 16:05:42 Anyhow, you are a few years from that currently! :) May 21 16:06:48 jic23b, hmmn.Really hadn't thought it that way. Yes atleast two-three years. May 21 16:07:50 + btw I've never come across Andrew Ng (been out of that world for a while) so was talking generally! May 21 16:08:01 (and not going to name any names on a logged irc channel either ;) May 21 16:09:24 jic23b,haha, But in any case pretty difficult to qualify there.So many brilliant people apply.Hoping that GSOC will help on the way : ) May 21 16:09:37 jic23b, And nice to know that you have such a close connection with India.As you said truly international world these days : ) : ) May 21 16:10:07 It's all good stuff.. Never be afraid of applying anywhere! May 21 16:12:28 Also, if it doesn't work out first time around - keep in mind you can always do this stuff a little later in life. My wife did a few years at infosys and elsewhere before her PhD. May 21 16:14:26 jic23b, Ohh...Again when it comes to choice of companies,dream ==Google,haha.A lot of my seniors work at Google.Infact one of my seniors was in the lead team that has ported all the Android apps and stuff to Chromebook May 21 16:14:44 Google is going to launch it probably this year May 21 16:14:56 cool. There was some news items about it a couple of days back. May 21 16:15:38 Not sure I'd like working for such a big company myself. May 21 16:17:23 was -> were May 21 16:17:37 gah, my English always goes out the window when on IRC for some reason! May 21 16:17:58 jic23b, We all have our choices.I want to work in Machine Learning,neural networks and stuff.So Google is the place to be. May 21 16:19:04 true enough right now but who knows in say 5 years time! May 21 16:19:28 jic23b, : ) : ). Anyway,got to run.Dinner time for me.Nice talking to you.Will you be there during the summers for our projects? May 21 16:20:00 I'll be about as it's kind of fun to watch / chip in when something relevant pops up. May 21 16:20:12 Fair bit of travel though coming up so will be intermittent. May 21 16:20:57 Anyhow, have a good evening. I should probably go be sociable. May 21 16:22:19 hello everyone!! May 21 16:22:40 alexhiam, karki_: ping :) May 21 16:48:54 Hey ds2, m_w Wormo ! I was working with the dsheet (http://cds.linear.com/docs/en/datasheet/223876fa.pdf) circuit page 23 connector J3, the clock input . May 21 16:49:10 was trying to understand the circuit there .. May 21 16:49:17 hey ZeekHuge May 21 16:49:25 hih May 21 16:49:31 er hi there May 21 16:49:59 so want to keep some notes that i think is happening in the circuit there .. May 21 16:49:59 what don't you uderstand about the circuit? May 21 16:50:38 okay, so basically its to convert a sinusoidal input to a square wave. but with lesser magnitude. May 21 16:51:14 the part NC7SVU04 is just a basic inverter. May 21 16:52:07 the input clock doesn't necessarily have to be a sine wave May 21 16:53:53 they are just conditioning the clock to be appropriate for the logic levels of the devices I am pretty sure May 21 16:53:56 and why specifically an inverter is used ? it probably because the default state (ie just powered on and not giving any input to j3 ) will keep that position HIGH. So the inverter will make it LOW, and yes, to somewhat buffer the input May 21 16:54:47 you will see that they have 2 invetors May 21 16:55:05 okay one question, the capacitor there C5 . why is it marked 6.3V ? is it like a reference and will be already charged ? May 21 16:55:32 yes the other inverter is to J3 output pin. May 21 16:55:49 not directly, but through that buffer there . May 21 16:56:18 no the 6.3V is the capacitor rating May 21 16:58:22 oops ! okay. they haven't marked any other thing like that . neither ever seen such a marking without explicitly mentioning that. May 21 17:00:16 m_w: there must be an invitation at your mail inbox, for the datasheet on dochub. please can you come on it . May 21 17:00:49 do I need to register for this? May 21 17:00:57 I dont think so .. May 21 17:01:08 not sure. May 21 17:02:40 m_w: you there ? May 21 17:02:45 on the sheet ? May 21 17:02:54 I clicked it and it wants me to log in May 21 17:03:22 can use google account to log in May 21 17:03:54 Unexpected server response (401) while retrieving PDF "https://dochub.com/api/sources/26731529.pdf?page=1&per_page=100". May 21 17:04:29 after logging in with Google. May 21 17:04:55 that's where I got stuck last night actually May 21 17:05:22 ahh ... that was the problem earlier too .. anyway then, we should probably do it here. May 21 17:05:59 So, C5 and L1 are just to remove some high frequency signals . right ? May 21 17:06:45 I mean just to clear the noise out of the input voltage. May 21 17:07:06 and then R7 and R9 form a voltage divider. May 21 17:08:03 while there is no input at J3, the input to the inverter would be VDD/2. am i right ? May 21 17:08:50 nope May 21 17:08:56 there is a pulldown May 21 17:09:37 oh wait yes May 21 17:09:46 there is a voltage divider May 21 17:10:36 sorry was going by memory and just looked back at the diagram May 21 17:17:44 well send me an email with any other questions May 21 17:17:56 going to go spend some time with my family May 21 17:19:28 m_w: You know about the pru_framework project from last GSOC? May 21 17:19:44 not much May 21 17:19:55 this is my first GSOC mentoring May 21 17:20:39 though it was the very first thing we (me and m_w ) worked on. To get it working. :) May 21 17:21:37 m_w: while you are here. So, in steady state, the capacitor, C12 will be charged. May 21 17:21:43 at VDD/2 May 21 17:23:38 VDD/2 will be at one side of the capacitor May 21 17:24:32 the other side will settle to GND May 21 17:24:50 so I guess in a way yes it is charged May 21 17:26:07 and then when the input is applied on the J3 (assuming input : 0-3.3V square wave ), the polarity for C12 will change and it will then current through R9 will increase, that will decrease current through R7 and the input level to the inverter increases, thus a low signal comes out of the inverter. May 21 17:26:18 C12 is a DC blocking capacitor May 21 17:26:55 AC coupling May 21 17:27:20 okay so short-ing the cap12 will allow us to input a square wave ? May 21 17:27:48 no a signal would have to be applied May 21 17:28:58 read the section "Driving the Clock Input" May 21 17:30:02 they are calling the circuit a low-jitter squaring circuit May 21 17:30:42 yes. I was just trying to understand each part of it. May 21 17:32:56 they are supplying the clock input with a low phase noise sinusodial and getting a nice clean square wave May 21 17:34:59 well I have to go May 21 17:35:01 later May 21 17:35:06 yes, so if we already have a square wave, and we want to use that as the clock input, we can just remove the cap May 21 17:35:10 isnt it ? May 21 17:35:12 ahh .. May 21 17:35:15 .. May 21 18:02:11 ds2: Hey ! May 21 18:02:15 you there ? May 21 18:06:13 Wormo: can i ask questions related to that J3 input. What I want is to figure out a way to give input from the PRU onto that J3. May 21 18:08:21 my question is, cant we just remove R8, R9, R7 and short C12 ans use pru to generate clock ? as a pulse wave ? May 21 18:08:52 *and use May 21 18:08:56 sorry, I'm not hw support! May 21 18:09:17 okay. May 21 18:29:44 okay, so we cant remove all those components as they are terminating the transmission line. Probably thevenin termination. May 21 18:34:26 dining May 21 20:54:11 there should already be a couple of clocks builtin May 21 20:54:25 if you really need RTC just add one May 21 20:54:49 crap, he left... **** ENDING LOGGING AT Sun May 22 02:59:59 2016