**** BEGIN LOGGING AT Tue Apr 11 03:00:05 2017 Apr 11 09:22:08 ds2: Apr 11 09:22:35 Should I change the proposal wiki according to the discussions Apr 11 09:23:01 I plan to drop the UI design and go for a more comprehensive testing phase Apr 11 09:23:54 As you suggested the UI design can be pushed to a post GSOC Apr 11 09:24:18 Also I have got my hands on a Beaglebone black temporarily Apr 11 09:24:38 Any pointers on how to programming the PRU Apr 11 09:24:48 other than the TI wiki Apr 11 09:25:01 Since it requires a PRU cape Apr 11 10:04:38 NP95: maybe try to look into BeagleScope examples there ? They are exactly for this reason .. Apr 11 10:07:00 also, though the final decision will be based on the submitted proposal, its ok to change the wiki. Apr 11 10:33:52 Thanks zeekhuge Apr 11 12:33:16 zeekhuge Apr 11 12:33:26 Your blog was helpful thanks Apr 11 16:03:48 > Apr 11 16:04:22 nerdboy: For triggering , what do you think is best approach, I have read about this board Hc-sr04, although it is not suitable for our purpose, but the way it works can be useful for us Apr 11 16:05:01 https://uglyduck.ath.cx/ep/archive/2014/01/Making_a_better_HC_SR04_Echo_Locator.html Apr 11 16:05:42 this blog explains the working of this board and Apr 11 16:06:51 the microcontoller this board using is some EM78P153S chinese microcontroller running at 27MHz Apr 11 16:07:07 and uses max232 for generating wave pulse Apr 11 16:07:22 any suggestions or views about this approach Apr 11 16:08:19 ds2: would you provide your valuable suggestions regarding measurement of time of flight of sonic wave b/w two transducers Apr 11 16:16:58 thetransformerr: suggestions on what aspects? Apr 11 16:27:39 triggering/listening would be according to the data sheet Apr 11 16:31:18 if you don't want t use the murata sensors then you need to find an alternate sensor you can use Apr 11 16:31:30 s/t/to/ Apr 11 16:32:10 the muratas *should* work,, maybe with a bit of interface glue Apr 11 16:49:54 m_w: hi, I checked the schematic and unfortunately I found yet another unconnected pin (GPMC_BE1N). We need to find some extra pin. Apr 11 16:50:06 At my college I will be able to sloder some beagle-wire prototypes so I can use professional equipment so we can use ice40hx8k in the CBGA-225 package. We will gain a lot of logic and pins. Let me know what you think about it. As for the cost of the system it is quite similar (ice40hx4k - 6.5$ and ice40hx8k - 8.5 $) Apr 11 16:50:31 pmezydlo: do you need BE1N? Apr 11 16:50:47 i'm not sure Apr 11 16:51:19 well if we move to the BGA you will have to rely on external sources for assembly Apr 11 16:51:38 which will bring the price up for the prototypes quite a bit Apr 11 16:51:38 I compared beagle-wire with logibone and logibone uses be1n pin Apr 11 16:52:43 I'm not sure if I want but I'm afraid there will be a lack of logic Apr 11 16:54:52 When i was preparing application draft I talked with ds2 and he thought that 8k would not be enough. Apr 11 16:55:16 for what? Apr 11 16:55:34 we can't do more than 8K Apr 11 16:56:05 may as well use the logibone if with use something beside the ice40 Apr 11 16:57:37 nerdboy: I don't think we have any reasons to discriminate muratas for others, just as we don't have any reason to prefer murata, basically we require a 40khz transducer with waterproof capablity Apr 11 16:58:07 hi all Apr 11 16:58:26 hey!! Apr 11 16:58:47 m_w: We need to have enough logic for the user and for us Apr 11 17:00:00 Maybe I'm exaggerating Apr 11 17:00:25 and also nerdboy: I may not be able to devote much time to this proposal until 9 may, as I have my semester exams from 20 april Apr 11 17:00:59 m_w: if we don't need be1n all is ready for routing Apr 11 17:01:48 although I keep checking logs so you can leave message for me here, and if its important, please send it to my email Apr 11 17:03:28 and nerdboy:once the result is declared, how much time probably does beagle bone takes to dispatch beagleboard?? Apr 11 17:06:23 not sure about overseas but generally pretty quick Apr 11 17:06:49 as long as you have a good shipping address Apr 11 17:09:10 pmezydlo: determine what the purpose of the line is a report back to me Apr 11 17:11:12 jkridner: Hi, did you test the u-boot binaries? Apr 11 17:11:43 ravikp7: I tried, but I struggled with the bbblfs for OSX. Apr 11 17:12:03 I patched it to stop after the uboot load, but it never got there. Apr 11 17:12:20 I threw it on an SD card, but I don't know if that'd even work.... and I never marked it bootable. Apr 11 17:12:31 And I haven't connected a serial cable yet to test that. Apr 11 17:14:22 m_w: gpmc be1n is used for enabling upper data byte. Apr 11 17:14:27 jkridner: can you try with BBBlfs on linux? Apr 11 17:16:05 pmezydlo: are you wanting to use 16bit multiplexed bus access? Apr 11 17:16:35 they needs are based on the bus modes that you intend on supporting Apr 11 17:16:51 ravikp7: at some point.... got several tasks in the queue ahead of that right now. Apr 11 17:18:48 m_w: he is proposing some fancy interface that will burn lots of gates Apr 11 17:19:29 jkridner: ok, how do you find the timeline in the proposal? Do you suggest anything to get sorted out before official coding time ? I think I should leave further work according to timeline to keep me engaged enough through the whole period. What do you think ? Apr 11 17:20:43 MMIO should only need some simple interface logic Apr 11 17:21:38 latch if you want to use the multiplexed mode Apr 11 17:21:59 IIRC - there were more then a simple latch Apr 11 17:22:18 that's right, I was thinking about a fancy solution, because we need have a few memory cell for mapping it Apr 11 17:22:33 hmmmm Apr 11 17:23:01 you want to bump up to the 8k then? Apr 11 17:23:03 I wanted to share some of the sdram memory Apr 11 17:23:36 not sure I understand Apr 11 17:23:49 IMO - that is doing too much Apr 11 17:24:59 I thought that the SDRAM was for the FPGA? Apr 11 17:25:31 does the ice have a SDRAM controller? Apr 11 17:25:45 no Apr 11 17:25:57 sdram is for fpga Apr 11 17:26:31 ds2: not embedded Apr 11 17:26:54 so it means gates or parts.... Apr 11 17:26:59 requires 227 LUTS Apr 11 17:27:05 s#or#and/or# Apr 11 17:27:45 http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesign04/SDR-SDRAM-Controller-Advanced.aspx Apr 11 17:29:09 Does ice40hx have some internal memory? Apr 11 17:30:52 I want somewhere to hold common data for arm and fpga Apr 11 17:32:49 I don't tell the user to keep watching the gpmc bus, I want to create something comfortable solutions Apr 11 17:33:30 keep in mind the gpmc burns A LOT OF PINS Apr 11 17:34:34 Yeah we know about it, luckily there are no shortage of pins Apr 11 17:36:30 We need to add pdf with schematic Apr 11 17:37:47 pmezydlo, yes it has internal SRAM blocks Apr 11 17:38:26 ok great I will use it Apr 11 17:39:17 the ice40's are a small FPGA/large CPLD Apr 11 17:39:18 I got a picorv32 processor in the 8K and used the internal sram for the data space Apr 11 17:39:47 and code space Apr 11 17:40:02 I can not wait for this board, Now I have a few projects and I will be porting it for beaglewire Apr 11 17:40:05 and had LUT room to spare Apr 11 17:40:21 but that was the 8k Apr 11 17:41:51 the hybrid boards have bridges and share a spi/i2c contoller Apr 11 17:42:51 the ice40 is a toy FPGA Apr 11 17:43:27 propably we can use only 8bit mmio bus Apr 11 17:43:46 sure Apr 11 17:56:36 pmezydlo: do you want to proceed with the routing? Apr 11 17:57:06 or would you like to reorder the nets a bit more? Apr 11 18:00:35 yeah I want to proceed with the routing, I will still optimize the pin layout Apr 11 18:00:55 It was preliminary Apr 11 18:04:42 m_w: could you give me more information about width of net, layer and etc Apr 11 18:09:37 uses 6mil traces and spacing for the minimums Apr 11 18:10:14 does the ice40 NEED 6/6? Apr 11 18:10:35 not really Apr 11 18:11:05 wouldn't routing for 8/8 be better to max. alt fab options? Apr 11 18:11:06 but it will make routing easier Apr 11 18:11:25 yes, so would adding a stack of layers :D Apr 11 18:11:35 that is true Apr 11 18:11:48 we won't need more than 4 layers Apr 11 18:11:56 we are untangling the nets Apr 11 18:12:07 fpgas make routing a breeze Apr 11 18:12:13 heh Apr 11 18:16:56 well as long as the order does not causing intern timing issues Apr 11 18:17:07 m_w: are you wrote something before "(20:10:35) m_w: not really" I restarted my computer and I don't see Apr 11 18:17:48 about? Apr 11 18:18:20 about routing process Apr 11 18:18:43 check the logs :) Apr 11 18:19:23 ds2 was saying that we might be able to get away with 8mil traces and spacing Apr 11 18:19:56 you didn't miss anything Apr 11 18:20:14 thanks Apr 11 18:21:38 once you are comfortable with the pin ordering, do another pull request and I can do some setup and fanout Apr 11 18:22:38 for something this small, I question the GPMC approach Apr 11 18:23:27 I think that using GPMC allows for applications that SPI or I2C wouldn't Apr 11 18:24:22 hopefully the logic space isn't too constraining for anything of real use Apr 11 18:24:25 as I may have mentioned, I am looking at doing something similar Apr 11 18:24:37 I would go about it differently - Apr 11 18:24:42 Ok i'll make some more changes, should be will be ready in hour Apr 11 18:24:58 ds2, what did you have in mind? Apr 11 18:25:05 provide access to the other stuff (SPI/PRU/I2C/etc) and not depend on GPMC Apr 11 18:25:19 that way, the end application can use it as it sees fit w/o burning all the pins Apr 11 18:25:39 and the ice40 can be pressed into service as a voltage shifter if needed Apr 11 18:26:14 how many PRU pins would you bring accross? Apr 11 18:26:22 all of it Apr 11 18:26:30 worse case, I high-z it on the FPGA Apr 11 18:27:01 you are treating the ice40 as a first class citizen whereas I see it as an assistant for the arm Apr 11 18:27:30 is the ice40 big enough to treat as a first class citizen (enough LUTs, etc)? Apr 11 18:27:55 we might have different goals so.... Apr 11 18:28:20 does the gpmc and pru overlap some? Apr 11 18:28:51 probably not all Apr 11 18:28:52 yes Apr 11 18:28:59 but that isn't my point Apr 11 18:29:13 you are pretty much saying this is a device on the GPMC Apr 11 18:29:29 whereas I am saying, the FPGA has access to those signals Apr 11 18:29:49 so if all I want is a I2C device, I high-z the other pins Apr 11 18:30:07 just got to be careful with the boot pins :D Apr 11 18:31:05 they had some trouble with the blue because of the boot pins Apr 11 18:31:36 it isn't that difficult... worse case you have logic to qualify it with reset Apr 11 18:32:20 yeah the have the pin with a passive pullup going straight to a servo header Apr 11 18:32:35 "oops" Apr 11 18:34:32 ECO Apr 11 19:31:59 m_w:i'm pushing new changes, I think now is good but I will make some improvements during routing process Apr 11 19:33:34 pmezydlo: okay Apr 11 19:34:05 you are welcome to continue to the routing if you wish Apr 11 19:34:24 we can always fix issues Apr 11 19:36:05 Of course I want, the most interesting before me **** ENDING LOGGING AT Wed Apr 12 03:00:01 2017