**** BEGIN LOGGING AT Tue May 23 03:00:02 2017 May 23 04:31:47 actually i need to apply them to ti-dev kernel May 23 04:32:14 otherwise bb-kernel needs more tipwm upgrades May 23 05:57:58 Ds2 description good. I'd get them on a scope first and see how good signals are... May 23 05:59:18 Otherwise as you say basic phase detector. Need to keep distances short enough to never wrap around though... May 23 06:00:54 Only need a few multiples of 40khz sampling frequency as well which is nice. Using simultaneous sampling ADC? If not care needed with time shifts on the sequencer perhaps... May 23 06:01:10 Anyhow lots of options,! May 23 06:03:13 not simultaneous sampling ADC May 23 06:03:24 AFAICT, it is a flash converted with 2 muxed inputs May 23 06:13:49 Hmm then a bit of a phase offset to deal with as well.. more filtering fun. May 23 06:15:04 Do you definitely get a nice sinewave off the transducers? May 23 06:16:20 Which ADC are we talking about? May 23 06:16:23 I donno May 23 06:16:29 PRUDAQ May 23 06:16:34 it is an ADI part May 23 06:16:49 I suspect it will be a square wave with the higher harmonics rolled off May 23 06:18:00 ds2: what if we pass sine wave to tx, though I dont have any idea how would we genearte such sine wave May 23 06:21:24 thetransformerr: it would get complex from the EE angle May 23 06:22:18 having said that maybe a PWM drive May 23 06:22:41 then rely on the receive filters May 23 06:23:13 or even some other coding to move the undesireables away from the signal of interest (thus simplifying teh filters) May 23 06:24:20 actually what do we require output to be like? May 23 06:29:13 that's a question for nerdboy... i suspect it is a number like XXXX mph May 23 06:29:24 or kph for the wierdos ;) May 23 06:29:59 :) I was talking about output from receive filter... **** BEGIN LOGGING AT Tue May 23 06:32:54 2017 May 23 06:33:04 * nerdboy had to port the patches and then make a porting patch May 23 07:38:32 thetransformerr: check the latest branch herew => https://github.com/VCTLabs/ti-linux-kernel-dev May 23 07:38:38 *here even May 23 07:48:32 nerdboy: is it complete now ?? currently with these drivers do we need PRU? May 23 07:48:47 or just a user space program May 23 07:52:35 read the docs for the driver May 23 07:52:57 you still have a lot to do... May 23 07:55:08 anything I should start with first?? May 23 07:55:30 the round-robin example? May 23 07:55:40 okk May 23 07:56:20 or just try doing something with ecap May 23 07:57:07 also checkout the pru tools and latest examples May 23 07:57:13 v5-ish i think May 23 07:57:30 I would like to complete ecap driver program by tonight May 23 07:57:46 a simple or complex depending on its complexity May 23 07:58:10 * nerdboy has a dentist appt in the morning... May 23 11:49:34 jkridner: Hi, I received the hardware today, but I had to pay $56 as custom duties :( May 23 11:50:31 $56 ?? around 3650 May 23 11:50:44 what hardware did you received? May 23 11:56:23 Beaglebone black, blue, green and green wireless May 23 11:57:08 then it may be ok ;) May 23 12:02:41 thetransformerr: I think our custom department is cheating us. They calculated the taxes on the local imported price of the products May 23 12:03:37 Black costs $45 in US which is ₹2920 May 23 12:03:56 I am sorry but I am unaware about custom duties, but doesn't imported price already include customs charge May 23 12:04:43 In India it sells for ₹4379 with taxes included May 23 12:04:50 did you made a search on google about custom rules? May 23 12:05:06 and they have calculated import duties on 4379 May 23 12:05:12 And they calculated 17% duties on ₹4379 for the black May 23 12:05:59 and would you please tell from where you are referring 4379 ?? May 23 12:06:16 For other products, the bill inside clearly mentions $165 May 23 12:06:55 From tax duties document sent by fedex May 23 12:07:32 And they calculated taxes on $203 ( ₹13190) May 23 12:07:43 Instead of $165 May 23 12:07:57 ravikp7[m]: :( May 23 12:08:07 ravikp7[m]: that's crazy. May 23 12:08:16 Its like paying taxes on taxes :( May 23 12:09:21 I think I sent you 3 boards to test, so that's probably right. May 23 12:10:13 ravikp7: 203-165=38 which is 23% of 165 May 23 12:10:35 and they have imposed another 17% ?? May 23 12:10:41 Yeah, don't know how to deal with this wrong practice :( May 23 12:10:53 ravikp7[m]: :( May 23 12:11:09 ravikp7[m]: now that you have a board, did you get the ROM code to respond for you? May 23 12:12:00 all: any comments on http://jadonk.github.io/beaglebone-getting-started/START.htm ? May 23 12:12:40 do you know under what class your shipment is falls like mobile, electronic components etc May 23 12:13:12 jkridner: just received it, and was busy in calculating the taxes, will do that now and let you know May 23 12:14:33 jkridner: it looks nice, gives information about intial booting and all May 23 16:47:45 this one has simple ttl pulse interface plus some exampple code => https://www.parallax.com/product/28015 May 23 16:48:04 and a dental appt May 23 17:10:39 nerdboy this looks very good May 23 17:11:03 ds2: would please have a look ^^^^ May 23 17:17:53 look at what? May 23 17:18:12 https://www.parallax.com/product/28015 May 23 17:21:00 how is this different from the SR04? May 23 17:26:49 oh sorry!! I mistakenly compared with maxim board, and thought that it can receive without transmitting May 23 17:26:57 I guess this was due to too much of kernel code today :) May 23 17:29:21 Too much kernel code? Never unless it is a vendor tree in which case *laughs* May 23 17:31:27 vendor trees are fine trees May 23 17:32:01 maybe It was too much just for me to dive into ecap drivers and figure out how the code was implemented May 23 17:32:18 only problem trees are trees from developers who donno what they are doing and tosses them at you to finish stuff May 23 17:33:06 the video we have to prepare, should be of approx what length May 23 17:33:15 as gsoc student May 23 17:34:31 Depends on the vendor tree :). Some of them are vendors tossing half finished code out there :( May 23 17:35:26 thetransformerr[: but did you 'enjoy' digging ? May 23 17:36:20 Ti are better than many in oh so many ways btw. May 23 17:37:00 "enjoyment", may be it is the reason, why I am here in GSoC!!!!! May 23 17:37:19 One of the reasons beagleboard are so successful. May 23 17:37:49 jic23: :-) May 23 17:38:10 Cool. Welcome to the dark side :) May 23 17:38:53 jic23: you mean like some of the asian SoC vendors? ;) May 23 17:39:24 dark and light are again part of life ......... yin and yang!!!! May 23 17:39:35 :) May 23 17:39:36 No comment (I am going to be working for one of them from next month :) May 23 17:39:45 hehe May 23 17:40:11 Thankfully not in their mobile stuff :) May 23 17:40:31 so, is there a consense on what sensors are going to be sued for the sonic annometer project? May 23 17:40:56 And spoil the fun? Down with the consensus. May 23 17:40:58 jic23: I have learned to tolerate a lot more tree May 23 17:41:43 jkridner: I was testing BBBlfs, SPL runs, uboot gets transferred but uboot doesn't seem to run as uboot device can't be opened with uboot vid, pid May 23 17:41:45 if all we want is a proof of concept and don't care about other folks near by, we can also use regular mics and spkrs May 23 17:41:45 is there any reason not to use the sensor eval board ds2 found on digikey? May 23 17:42:22 Ds2, I kind of enjoy the challenge of digging through vendor dumps May 23 17:42:26 no I guess we are far away from consensus, May 23 17:42:47 ravikp7[m]: where do you have your u-boot build steps saved in git? May 23 17:42:49 Gut feeling would be that evaluation board... May 23 17:43:08 wormo: may be because they too need hacking May 23 17:43:29 jic23: heh... I should ask you in a few months on your views of commenting code and variable names May 23 17:43:56 still looking for one that doesn't need any? May 23 17:44:07 and we are hoping that ds2: would test them, once we develop some basic code for calculation May 23 17:44:45 do I get to dictate how the code will interact with it? :D May 23 17:45:03 I think that's typically the hw engineer's perogative May 23 17:45:20 wormo: now, go tell that to management :D May 23 17:45:30 Ds2 yeah... Will be interesting :) May 23 17:45:40 jkridner: I was using uboot binary of BBBlfs, I was checking the fit approach of bbblfs to boot into mass storage May 23 17:45:46 "Oh and it will go catatonic until power cycle if you don't get the data out by the deadline, have a nice day" May 23 17:45:55 I dont think we would be able to find any such board which doesnt require , because if it was so.. May 23 17:46:00 * wormo deals with an unnamed chip that is like that May 23 17:46:18 ds2: you can be the captain, infact you are May 23 17:46:35 jic23: right now, my view is - No comments. Please use variables like X/Y/Z/A/B/C... it'll save me and everyone else a lot of time in the end. May 23 17:46:58 wormo: chip? I can think of a camera... May 23 17:47:37 thetransformerr[: I am not much of an alg person... are you up on DSP stuff? May 23 17:48:44 well as you said in morning may be DSP is going to be different in cases of TOF or phase method May 23 17:49:15 thetransformerr[: yes, but my ability to advise on that aspect is limited May 23 17:51:24 I am currently trying to build a program using ePWM and eCAP, in which DSP is I think somewhat limited, and is described in technical manual May 23 17:52:00 Ds2 *laughs*. I have been warned by my soon to be boss that he can't get either the hardware team or software team to write any docs. Have the verilog though :) May 23 17:56:05 jkridner: I also tested with the uboot that I configured, enabled ums in menuconfig and added this https://pastebin.com/LJ5jhi6L to am335x_evm.h for ums ids. I didn't save the build logs, but there weren't any errors May 23 17:56:58 Anyone have the link for the ultrasound evaluation board to hand? May 23 17:57:02 jic23: hahaha fun May 23 17:57:51 Ds2, Right now I get to change the vhdl, otherwise much the same :) May 23 17:58:20 My vhdl is rubbish so this might be an improvement. May 23 17:58:33 jc23: I think this is - https://www.digikey.com/product-detail/en/maxim-integrated/MAXQ7667EVKIT-1-/MAXQ7667EVKIT-1--ND/4271390 May 23 17:59:17 jkridner: after enabling ums mode in uboot, should it auto mount emmc after uboot transfer? May 23 17:59:45 Ds2 thanks May 23 18:00:39 ravikp7[m]: I believe so, but I've never enabled UMS mode in uboot. Just realized you likely don't have a serial cable. :-( May 23 18:03:15 jkridner: serial cable? for what purpose? to inspect uboot? May 23 18:03:36 yes, inspect uboot and debug what commands it is running. May 23 18:03:52 simply see that it *is* running. May 23 18:06:29 jkridner: like this https://www.tanotis.com/products/tanotis-usb-to-ttl-serial-cable-pl2303hx-debug-console-cable-for-raspberry-pi?gclid=CjwKEAjwu4_JBRDpgs2RwsCbt1MSJABOY8anIIj3Ev-nJ9DezAmPGJ5e3tvlKh3-Bxm0rgSg_frBOxoC01rw_wcB&variant=21469402821 ? May 23 18:06:50 yes, one of those. May 23 18:07:24 jkridner: I'll make one out of a spare usb cable May 23 18:11:25 ravikp7[m]: great! May 23 18:15:08 jkridner: I'll let you know the status of debugging tommorow, going to sleep.. exam tommorow :( May 23 18:25:26 Hmmmm May 23 19:11:11 m_w: I'm really confused, now I'm trying to fix BeagleWire schematic and Is cat boards has the same gaps? May 23 19:11:27 https://github.com/xesscorp/CAT-Board/blob/master/docs/Manual/pics/CAT_schematic.pdf May 23 19:15:05 I'm having second confused you wrote in email "Pin 5 should go to SPI_MISO and pin 2 should go to SPI_MOSI." but on the schematic below You can see something diferent. May 23 19:15:50 for now I have 3 different way to connect SPI I don't know which is good May 23 19:22:41 pmezydlo: the cat board pdf schematic is not updated May 23 19:23:09 pmezydlo: if you look at the hackaday.io blog it talks about a revision May 23 19:23:58 https://hackaday.io/project/7982-cat-board/log/36982-cat-board-all-on-its-own May 23 19:24:14 see how it is wired differently in the pictures May 23 19:24:23 than on the PDF May 23 19:25:03 ok thanks, May 23 19:25:09 the loading of the FPGA via SPI so fast that I doubt we will even need the flash May 23 19:25:51 the board I sent today has the flash removed May 23 19:26:56 we can fix the wiring on the revision but leave it nopop on the boards May 23 19:27:51 yeah I'm thinking the same May 23 19:29:38 now I'm fixing it, when all will ready I let you know May 23 19:31:38 pmezydlo: okay great May 23 19:39:03 m_w: I understand that ice40-mgr allows only ice40 programming, when we use ice40 reset lines we can load program to flash memory? May 23 19:53:12 this is weird but is only one different thing between use spidev or fpga-mgr and it is dd if=example.bin of=/dev/spidev1.0 or dd if=example.bin of=/dev/fpga0. Using fpga-mgr is meaningless May 23 20:03:35 pmezydlo: it is more complicated than dd only May 23 20:07:16 jic23: be nice, i'm buried under msm kernel branches May 23 20:07:44 silly android devs made an unmaintainable mess... May 23 20:11:30 the dd method only works if you add a handful of bytes with 0x00 to the end of the binary and only the first time you boot May 23 20:12:12 you need to manage the reset going to the fpga to get it to work properly May 23 20:12:55 I think that the reset needs to toggle while spi cs is asserted before the data is clocked May 23 20:13:22 you can't do that from userspace which using a GPIO for the chipselect May 23 20:13:30 I pushed commit to BeagleWire pcbs May 23 20:13:56 makes more sense May 23 20:14:30 so do you guys plan on making some example projects for this thing? May 23 20:14:45 using opencores IP i assume... May 23 20:18:28 yes there will be examples of interfacing with different IP blocks May 23 20:19:07 yes examples are is bigger part of project May 23 20:19:08 we have a memory mapped interface to the FPGA so it should be pretty straightforward to add peripherals May 23 20:19:52 i meant like a full project with a makefile to build the blob May 23 20:20:13 that plus documentation... May 23 20:21:15 the (broken) dts glue and documented details about u-boot hand-off files are conveniently left of the altera/intel docs May 23 20:21:28 *left out even May 23 20:21:52 and their projects/demo images are stale and broken May 23 20:23:20 we ended up doing the work ourselves to get anything to work and without any help from their "support" engineer May 23 20:24:08 hmm, just about as messed-up/broken as most of those android kernel branches... May 23 20:24:18 altera/intel fpga? May 23 20:25:20 hopefully our stuff will be easier to understand then the broken rocketboards examples May 23 20:26:21 The main advantage is to be that there will be ready examples which e.g. users can use additional spi or gpio from python or c, and verilog code should be ready and ready to program May 23 20:27:27 project will be helpful not only for verilog hackers May 23 20:33:16 m_w: can I use your beaglewire photos for my GSOC presentation? May 23 20:33:27 yes May 23 20:33:31 go for it May 23 20:34:05 the board wont be there until the end of the month May 23 20:36:13 Nerdboy yeah android trees do seem particularly awful. May 23 20:41:42 pmezydlo: you can put them on your hackaday.io page as well May 23 20:52:11 m_w: yeah sure May 23 21:08:12 * nerdboy votes for a hd audio project May 23 21:09:33 https://github.com/VCTLabs/DE1-SoC-Sound <= something like this maybe? May 23 21:09:54 that was not an official one, i just scavanged it off github May 23 21:13:13 i pretty much just updated the proiject version and dts for 4.9 kernel May 23 21:13:43 didn't get it to work though, codec coughs an interrupt error May 23 21:14:10 Do you make simple audio processing on FPGA? May 23 21:14:14 and now i don't have a de1 anymore so no more testiing... May 23 21:14:49 not really, i just test/fix stuff May 23 21:15:19 the de1 has the wolfson code interface already May 23 21:15:26 *docec even May 23 21:15:43 * nerdboy slams fingers in the keyboard drawer May 23 21:18:34 never I had good dac and adc but this is good idea, on university I remove noise from audio using dsp and it is working very good. May 23 21:19:43 i wonder if We could do it using fpga May 23 21:21:41 I made a SAR ADC using an FPGA before May 23 21:24:18 I passed a sigma-delta output to a low pass filter to create a DAC then passed it to a analog comparator that fed back to the FPGA which had the shift register for the SAR May 23 21:24:50 probably could have maybe it better with an external sample and hold circuit May 23 21:25:02 make it May 23 21:26:25 I then used the ADC to create a capacitive to digital convertor May 23 21:27:06 school project about 10 years ago May 23 21:27:52 think it was a xilinx startan 2 fpga May 23 21:29:01 on univeristy I have to make calculator on fpga it's very boring May 23 21:29:21 but next project is aes May 23 21:30:05 m_w: You had an interesting project May 23 21:32:25 dsp project is more interesting but the problem is the teacher May 23 21:37:02 several schools have ee course pages using de1 May 23 21:37:31 there's a cool prof at irvine with some of that May 23 21:37:51 he's more into security-focused analysis i think May 23 21:38:15 or it might be uc riverside... May 23 21:39:08 pmezydlo: i think he has phd spots/money May 23 21:43:19 here we go... May 23 21:43:40 an example of how whacked the msm kernel branches are May 23 21:44:07 the old 3.4 branch has msm_serial_debugger.c and msm_serial_debugger.h May 23 21:44:25 BUT the former doesn't even include the latter May 23 21:46:52 and apparently only 2 msm boards support it, neither of which is part the that build... May 23 21:47:13 yay for upstream **** ENDING LOGGING AT Wed May 24 03:00:04 2017