**** BEGIN LOGGING AT Thu Jun 22 03:00:02 2017 Jun 22 15:38:18 nerdboy: it just works, so I didn't think about any other init, what else there should be? Jun 22 18:04:12 no idea, just asking... Jun 22 18:23:30 hmmmm Jun 22 18:23:37 rather quiet this year Jun 22 20:45:04 pmezydlo: hows the project coming along? Jun 22 20:45:40 ravikp7: I spent a bunch of time the USB stuff but didn't make a ton of progress Jun 22 20:45:56 m_w: I'm working on spi controller and kernel driver Jun 22 20:46:13 pmezydlo: your wheel house :) Jun 22 20:46:49 gpio controller is easy to implement but I have to do tri-state buffer for each pin. Jun 22 20:47:10 ravikp7: I could not get either SPL to transfer U-Boot Jun 22 20:49:15 ravikp7: I think that we are missing something Jun 22 20:50:20 pmezydlo: are you making an SPI slave or host in the FPGA? Jun 22 20:51:01 hmm maybe after more important interface Jun 22 20:51:26 so host? Jun 22 20:52:13 now spi master Jun 22 20:53:02 do you see my new led example using dual port ram Jun 22 20:53:08 https://github.com/pmezydlo/BeagleWire/blob/develop/examples/arm_blink_leds/fpga/top.v Jun 22 20:54:29 why do you need dual ported ram to blink the LEDs? Jun 22 20:55:36 because this is base for other components, Jun 22 20:56:21 dual port ram is important when we have to send data from fpga Jun 22 20:57:15 We don't set ram registster from different clock domain Jun 22 20:59:49 can't just use flip flops and tristates? Jun 22 21:00:37 tristates are kind of a pain in the ice40 though Jun 22 21:01:09 really I'm not sure how use tri state in yosys Jun 22 21:01:47 well besides how we did for the bus interface Jun 22 21:02:41 https://github.com/pmezydlo/BeagleWire/blob/develop/components/gpmc-sync.v#L50 Jun 22 21:03:05 yeah that Jun 22 21:03:45 but we used io pin directly Jun 22 21:04:31 yeah I think that the tristate have to be at the top level only on the ice40 Jun 22 21:05:28 so we have to use mulitplexors instead when feeding data back from various IP blocks Jun 22 21:08:07 I can use internal memory as dual port ram, registers use a lot of logic. Jun 22 21:08:52 but for now I'm using only 5% of logic Jun 22 21:09:02 then what if there are more IP blocks / subsystems than 2? Jun 22 21:10:55 hmm it's a small problem but it still is Jun 22 21:12:10 do you have any idea how to resolve it? Jun 22 21:12:23 I think it is not going to lead to reusable IP blocks if we can't tristate off the bus internally Jun 22 21:12:54 we would just have to multiplex the bus instead of tristate it Jun 22 21:14:23 internally to the FPGA Jun 22 21:15:48 more interfaces can use only one bus, but each interface has to check if the bus is busy Jun 22 21:17:57 state machine might just not skip to next state Jun 22 21:18:47 just needs careful consideration Jun 22 21:21:30 fifo buffer with transactions to/from dual port memory :) Jun 22 21:22:14 in high level all is prettier Jun 22 21:22:55 lets worry about single controller instances for now Jun 22 21:24:03 yes now I want to create components Jun 22 21:24:38 this week I want to start working on sdram Jun 22 21:26:32 ok I'm going to sleep bye Jun 22 21:32:28 sdram????? Jun 22 21:32:51 is the plan to add memory to the BBB via a FPGA SDRAM controller? Jun 22 21:35:16 ds2: it is accessed via FPGA to be used locally I think Jun 22 21:35:34 oh I see Jun 22 21:35:47 does the ice40 have the right drive modes to handle SDRAM? Jun 22 21:35:56 (or DDR?)\ Jun 22 21:36:23 it is just regular SDRAM Jun 22 21:36:35 no differential drivers are needed Jun 22 21:36:49 I think it'll work Jun 22 21:36:54 afaik cycloneV works the same way Jun 22 21:37:28 as fas as shared/local sdram anyway Jun 22 21:39:37 ooohhh Jun 22 21:51:09 * nerdboy not an fpga guy Jun 22 21:51:39 just had to fix some de1 stuff and now i don't have the board anymore... Jun 22 22:29:51 DE1 == that mini O-scope? Jun 23 01:31:12 m_w: you couldn't get spl to transfer uboot on linux ? Jun 23 01:32:18 m_w: which distribution you're using? so that I can test it Jun 23 01:41:09 Incase I need to get it tested on more linux systems. nerdboy, zeekhuge, ds2, pmezydlo, ee, maciejjo please give it a try https://github.com/ravikp7/node-beagle-boot . Installation instructions are there. Jun 23 01:47:16 m_w: what error do you get on spl? Host didn't respond in time? Please also do try the original C server by changing the uboot with the latest ums configured and commenting out code after uboot transfer in src/main.c https://github.com/ungureanuvladvictor/BBBlfs Jun 23 02:34:57 DE1 as in terrasic hybrid fpga/arm board Jun 23 02:45:36 ravikp7: debian but with a 4.10 kernel that I compile myself Jun 23 02:45:55 the same thing happens with BBBlfs Jun 23 02:46:40 m_w : and what do you think could be the reason for this? Jun 23 02:46:58 the drivers that are attaching to the device Jun 23 02:47:26 your code and the BBBlfs code piggy back on the initialization from the linux drivers Jun 23 02:48:29 I blacklisted the kernel drivers that were attaching and it never starts even the SPL load Jun 23 02:48:54 but if I add the RNDIS code from the Window branch it works Jun 23 02:49:25 for the SPL load but it still fails on the u-boot load from the SPL Jun 23 02:49:48 m_w: the spl broadcasts bootp ? Jun 23 02:50:07 lemme see what it prints Jun 23 02:50:17 found my serial cable finally Jun 23 02:52:02 * nerdboy still debugging stupid raid... Jun 23 02:53:16 I think I saw it work only once Jun 23 02:53:33 https://pastebin.com/xSYUjWcZ Jun 23 02:53:38 this is with the new SPL Jun 23 02:54:02 And with old one? Jun 23 02:54:20 almost indentical Jun 23 02:54:40 https://pastebin.com/cqESDt8i Jun 23 02:55:35 m_w: and what error code shows? spl device opened? Jun 23 02:56:12 RangeError: out of range index Jun 23 02:56:45 it probably gets empty buffer Jun 23 02:57:05 m_w: log please Jun 23 02:57:34 https://pastebin.com/X10JXLWJ Jun 23 02:57:53 m_w: without rndis init, the code doesn't work in beginning? Jun 23 02:58:25 it does not unless I take off the blacklist Jun 23 02:58:56 the driver is doing some initialization for you before you unbind it Jun 23 02:59:26 m_w: the kernel driver dettach command in code doesn't work even? Jun 23 02:59:41 here is something that is interfesting that is printed in the kernel messages on my PC when the SPL starts **** ENDING LOGGING AT Fri Jun 23 03:00:04 2017