**** BEGIN LOGGING AT Sat May 01 03:00:43 2021
May 01 08:07:47 * DhruvaG2000[m]  < https://matrix.org/_matrix/media/r0/download/matrix.org/HolpWNnHWAJWtfCBshYqrMsp/message.txt >
May 01 08:08:20 <DhruvaG2000[m]> <del>contains</del> mentions of
May 01 08:20:31 <ArchismanDey[m]> The X15 has 4 PRUs instead of 2 afaik, maybe he meant X15 instead of AI?
May 01 08:21:02 * vedant16[m]  < https://matrix.org/_matrix/media/r0/download/matrix.org/aLeAYrEdhRYYTpQzTccbkCzf/message.txt >
May 01 08:22:30 * DhruvaG2000[m] uploaded an image: (139KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/rwJomnJFKIBOynwgLXYlGUfy/image.png >
May 01 08:22:36 <DhruvaG2000[m]> pru 0 and 1 only
May 01 08:43:15 <pratimu[m]> DhruvaG2000: so there are  2 PRU subsystems on the board (PRU-ICSS) and each has two cores
May 01 08:43:28 <DhruvaG2000[m]> yes that is correct
May 01 08:43:40 <DhruvaG2000[m]> so that doesnt necessarily mean 4 PRUs individually right
May 01 08:43:58 <pratimu[m]> Some board like the black have 1 PRU-ICSS
May 01 08:44:22 <DhruvaG2000[m]> The pins and memory that we can access still remains the same
May 01 08:44:57 <pratimu[m]> <DhruvaG2000[m] "so that doesnt necessarily mean "> You can use them as 4, 2 of them would have same shared memory and interrupt controller etc. So you'll have to keep that in mind
May 01 08:44:59 <DhruvaG2000[m]> only boost in processing power @ PRU level will be observed, if I am not wrong
May 01 08:46:50 <DhruvaG2000[m]> <pratimu[m] "You can use them as 4, 2 of them"> oh, I will have to check this out..
May 01 08:47:02 <pratimu[m]> <DhruvaG2000[m] "The pins and memory that we can "> DhruvaG2000: yes
May 01 08:58:54 <pratimu[m]> <DhruvaG2000[m] "oh, I will have to check this ou"> Sure, keep posting any doubts you have
May 01 12:26:28 <pratimu[m]> DhruvaG2000: However I think in your case only 2 will be required (i.e. whatever Bela was using before). Please confirm with giuliomoro[m]
May 01 12:27:07 <DhruvaG2000[m]> right..
May 01 15:24:52 <vedant16[m]> <DhruvaG2000[m] "so that doesnt necessarily mean "> 1 pru-icss has 2 cores, so 2 pru-icss haa 4 cores
May 01 15:25:52 <DhruvaG2000[m]> yes, almost like having 2 ESP32's ...
May 01 15:27:07 <DhruvaG2000[m]> just to give a familiar analogy..
May 01 15:28:16 <OmkarBhilare[m]> More likely having two raspberry pi pico, pico is almost like a pru device.
May 01 15:29:22 <DhruvaG2000[m]> Haaa yes better analogy
May 01 15:29:34 <DhruvaG2000[m]> *  yes better analogy
May 01 15:30:51 <vedant16[m]> nope this is incorrect in the sense that each pru core is completely independent
May 01 15:31:03 <vedant16[m]> so more like having 4 separate mcu
May 01 15:32:26 <OmkarBhilare[m]> Okay I haven't checked pru docs, will take look at it.
May 01 15:35:40 <vedant16[m]> <OmkarBhilare[m] "Okay I haven't checked pru docs,"> cool, let me know if you have any doubts
May 01 15:35:43 <DhruvaG2000[m]> <vedant16[m] "nope this is incorrect in the se"> the cores do share the same memory tho
May 01 15:36:00 <vedant16[m]> they have separate ram
May 01 15:36:05 <vedant16[m]> and rom
May 01 15:36:12 <vedant16[m]> but only a 12kb common scratch area
May 01 15:36:21 <vedant16[m]> but you can access each other's memory
May 01 15:36:35 <DhruvaG2000[m]> aha! I will have to be more thorough with the SRM I guess..
May 01 15:41:44 <DhruvaG2000[m]> <vedant16[m] "they have separate ram"> yes it does say
May 01 15:42:59 <DhruvaG2000[m]> they have a common interrupt controller?
May 01 15:44:18 <DhruvaG2000[m]> <vedant16[m] "they have separate ram"> > 12-KiBprogramRAMper PRUCPU(signifiedIRAM0for PRU0and IRAM1for PRU1)
May 01 15:44:35 <DhruvaG2000[m]> >8-KiBdataRAMper PRUCPU(signifiedRAM0for PRU0and RAM1for PRU1)
May 01 16:04:28 <vedant16[m]> <DhruvaG2000[m] "they have a common interrupt con"> afaik no
May 01 16:04:36 <vedant16[m]> you should read srm, lot of doubts will be clarified
May 01 16:05:55 <DhruvaG2000[m]> yes
**** ENDING LOGGING AT Sun May 02 02:59:56 2021