**** BEGIN LOGGING AT Wed May 12 02:59:56 2021
May 12 17:30:24 <satacker[m]> Hello 👋
May 12 17:31:04 <YadnikBendale[m]> Hello everyone!
May 12 17:31:05 <vedant16[m]> Hello all
May 12 17:31:18 <OmkarBhilare[m]> Hello Everyone
May 12 17:31:21 <lorforlinux[m]> Hello everyone
May 12 17:31:30 <ArchismanDey[m]> Hello!
May 12 17:31:37 <Willmish[m]> Hi
May 12 17:31:43 <IainHunter[m]> Hello
May 12 17:32:07 <pratimu[m]> Hi all
May 12 17:32:09 <jduchniewicz> Hi
May 12 17:32:19 <jkridner> oops, hi all
May 12 17:32:23 <jkridner> sorry to be late.
May 12 17:33:13 <vedant16[m]> you are on time jkridner :P
May 12 17:34:39 <jkridner> :-D
May 12 17:34:47 * satacker[m]  < https://matrix.org/_matrix/media/r0/download/matrix.org/jtAOLqLnyxSyMmWtnrCIlsTV/message.txt >
May 12 17:34:49 <jkridner> oh, but I'm getting more coffee. :-)
May 12 17:34:57 * jkridner wants to kick matrix
May 12 17:35:53 <YadnikBendale[m]> jkridner: I was able to port micropython for QEMU, can you please have a look at it once.
May 12 17:36:01 <jkridner> I have *no* idea how to find mentions in irccloud. :-(
May 12 17:36:11 <jkridner> YadnikBendale[m]: sure... where's the link?
May 12 17:36:25 <YadnikBendale[m]> I had shared the screenshots here
May 12 17:36:46 <vedant16[m]> Yadnik Bendale: Screenshots are not good way to share anything especially code
May 12 17:36:56 <vedant16[m]> make a habit to put it on github
May 12 17:37:04 <vedant16[m]> so that we can reproduce it
May 12 17:37:16 <YadnikBendale[m]> I will do that
May 12 17:38:19 <YadnikBendale[m]> I was going to do that just wanted to know whether what I had done was correct.
May 12 17:38:33 <sakethr98[m]> hello all
May 12 17:39:12 <sakethr98[m]> apologies for the absence.
May 12 17:39:14 <YadnikBendale[m]> <vedant16[m] "Yadnik Bendale: Screenshots are "> Actually it didnt involve coding as such.I just had to build it using some commands.
May 12 17:39:18 <sakethr98[m]> *sighs exams
May 12 17:39:35 <vedant16[m]> <YadnikBendale[m] "Actually it didnt involve coding"> ohh, then document it on your blog.
May 12 17:39:40 <sakethr98[m]> <YadnikBendale[m] "Actually it didnt involve coding"> even for that, sharing plain text is always preferred to images is what Vedant meant
May 12 17:39:44 <vedant16[m]> or create a gist.
May 12 17:39:56 <YadnikBendale[m]> <vedant16[m] "ohh, then document it on your bl"> Yes will do that
May 12 17:39:56 <cwicks[m]> Hello students and mentors - I hope everyone's end of semester is going well and I hope that everyone is staying healthy!
May 12 17:40:05 <vedant16[m]> <sakethr98[m] "*sighs exams"> Hi :P
May 12 17:40:29 <sakethr98[m]> 👋 Vedant!
May 12 17:40:45 <sakethr98[m]> Thank you Cathy! I'm doing well.
May 12 17:41:17 <sakethr98[m]> wish the same with you
May 12 17:44:17 <jkridner> fyi: https://github-externships.github.io/externship/organization/beagleboard.html
May 12 17:45:32 <YadnikBendale[m]> jkridner: I also tried to build circuipython but found that the port does not exist for zephyr.For micropython it can be seen  https://github.com/adafruit/circuitpython/tree/main/ports as opposed to https://github.com/micropython/micropython/tree/master/ports/zephyr for circuitpython.
May 12 17:46:27 <YadnikBendale[m]> jkridner: I think I will have to add the zephyr port to the circuitpython upstream repo to build it.I have also written to them on discord regarding this.Can you also please share your views on this.
May 12 17:46:50 <YadnikBendale[m]>  * jkridner: I think I will have to add the zephyr port to the circuitpython upstream repo to build it.I have also written to adafruit on discord regarding this.Can you also please share your views on this.
May 12 17:47:41 * DhruvaG2000[m]  < https://matrix.org/_matrix/media/r0/download/matrix.org/FbidjdfxEfmfIOEHLcRIOqSE/message.txt >
May 12 17:54:34 <jkridner> YadnikBendale[m]: where's your fork?
May 12 17:56:29 <DhruvaG2000[m]> Thank you cwicks ,I'm doing well! Wish the same with you
May 12 17:56:29 <DhruvaG2000[m]> end sems went well.
May 12 17:57:01 <YadnikBendale[m]> <jkridner "Yadnik Bendale: where's your for"> fork of the circuitpython repo?
May 12 17:57:15 <sakethr98[m]> yes
May 12 17:57:21 <YadnikBendale[m]> jkridner: I honestly havent forked any can you please ellaborate
May 12 17:57:40 <OmkarBhilare[m]> https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py
May 12 17:57:40 <OmkarBhilare[m]> I was looking into how litedram can produce standalone Verilog code so that the SDRAM code generated by LiteDRAM in Verilog can easily be interfaced with other codes.
May 12 17:57:40 <OmkarBhilare[m]> Abhishek @mw
May 12 17:58:01 <cwicks[m]> Hello Students - can you please check in by tagging me?  thankyou!
May 12 17:58:51 <jkridner> YadnikBendale[m]: if you made changes to code to get it to work, where did you post your code changes?
May 12 17:59:01 <DhruvaG2000[m]> Hey cwicks !
May 12 17:59:12 <ArchismanDey[m]> cwicks: checking in!
May 12 17:59:15 <jkridner> If they are all just on your computer, please create a fork of the project and push your changes to a public fork for review.
May 12 17:59:16 <satacker[m]> Hi cwicks
May 12 17:59:35 <OmkarBhilare[m]> Hello cwicks
May 12 17:59:49 <YadnikBendale[m]> <jkridner "If they are all just on your com"> Yes ill do that.You mean it for the circuipython port right?
May 12 18:00:06 <jduchniewicz> Hi cwicks
May 12 18:00:06 <jkridner> yes, that's what you wanted me to look at, no?
May 12 18:00:12 <YadnikBendale[m]> > <@freenode_jkridner:matrix.org> If they are all just on your computer, please create a fork of the project and push your changes to a public fork for review.
May 12 18:00:12 <YadnikBendale[m]>  * Yes ill do that. You mean it for the circuipython port right?
May 12 18:00:17 <YadnikBendale[m]> <jkridner "yes, that's what you wanted me t"> yes
May 12 18:00:43 <YadnikBendale[m]> Hi cwicks
May 12 18:00:55 <jkridner> OmkarBhilare[m]: cool. aside, since you are looking at hardware, have you looked at all at the efabless shuttle wafer?
May 12 18:01:08 * jkridner wishes he could find the time to make a submission to that.
May 12 18:01:29 <jkridner> something like a RISC-V core optimized for PRU-like functions.
May 12 18:04:19 <OmkarBhilare[m]> <jkridner "Omkar Bhilare: cool. aside, sinc"> Glad you asked, Me and my friends trying for this shuttle. We are trying to add more peripherals to the RISC-V core already in the carvel which is picorv32.
May 12 18:05:22 <OmkarBhilare[m]> <jkridner "something like a RISC-V core opt"> This will be really great idea, but the window is really small. So I doubt this much doable at this time.
May 12 18:06:56 <Willmish[m]> cwicks: hey
May 12 18:32:38 <sakethr98[m]> @lpillsbury you here?
May 12 19:02:44 <DhruvaG2000[m]> <sakethr98[m] "@lpillsbury you here?"> If I'm not mistaken just earlier today I witnessed lpillsburh left this irc Reason:. Idle 30 days
May 12 19:03:08 <sakethr98[m]> okay
May 12 19:03:13 <DhruvaG2000[m]> @lpillsbury*
May 12 19:03:14 <sakethr98[m]> thanks
May 12 19:03:24 <sakethr98[m]> I missed logs
May 12 19:04:22 * DhruvaG2000[m] uploaded an image: (173KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/TcOsXhXSYolwWjpEWEFOCAfV/Screenshot_20210512-233412_Element.jpg >
May 12 19:31:47 <sakethr98[m]> thanks DhruvaG2000
May 12 21:02:37 <jkridner> OmkarBhilare[m]: yeah, pretty late time to start!
May 12 21:03:53 <jkridner> @here can you please check if the Github Externship is an option for you?
May 12 21:04:51 <lorforlinux[m]> https://github-externships.github.io/externship/schoollist.html
May 12 21:05:41 <OmkarBhilare[m]> <jkridner "Omkar Bhilare: yeah, pretty late"> Yes before going to asic we should definitely try the pru core on the FPGA.
May 12 21:06:09 <OmkarBhilare[m]> I guess someone suggested this idea earlier, running pru on beaglewire.
May 12 21:06:19 <jkridner> cool.
May 12 21:12:32 <m_w> jkridner, what is late to start?
May 12 21:12:47 <vedant16[m]> skywater shuttle
May 12 21:12:50 <m_w> I really wish the logs would come back
May 12 21:13:01 <m_w> it is never too late
May 12 21:13:19 <m_w> if you miss this shuttle we can jump on the next
May 12 21:14:24 <m_w> I have the icebreaker+++ for pyfive development and want to throw a pru like coprocessor on it
May 12 21:14:51 <m_w> I am excited to get our first silicon this summer
May 12 21:16:18 <OmkarBhilare[m]> Hi Michael,
May 12 21:16:18 <OmkarBhilare[m]> I was looking into the liteDRAM. As we have most of the other code in Verilog so I needed the SDRAM core in the Verilog itself so it will be easy to interface.
May 12 21:16:18 <OmkarBhilare[m]> The litedram has one nice feature is that it also produces Standalone Verilog sdram core
May 12 21:16:21 <OmkarBhilare[m]> https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py
May 12 21:16:50 <OmkarBhilare[m]> <m_w "I am excited to get our first si"> Great, you are getting the chip in the august, right?
May 12 21:17:09 <m_w> yes the first test chip for pyfive
May 12 21:17:24 <m_w> tnt is going to get them actually
May 12 21:17:34 <m_w> but I think he will send me some of the smples
May 12 21:17:44 <OmkarBhilare[m]> Does efabless also provides the PCB for tha asic chip?
May 12 21:17:59 <m_w> I think they do provide the PCB
May 12 21:18:05 <OmkarBhilare[m]> * Does efabless also provides the PCB for the asic chip?
May 12 21:18:32 <m_w> but you also get some bare chips
May 12 21:19:11 <m_w> they are going to be tricky to work with since they waferscale packaging
May 12 21:22:12 <OmkarBhilare[m]> <m_w "I have the icebreaker+++ for pyf"> https://github.com/riscv-mcu/e203_hbirdv2
May 12 21:22:50 <OmkarBhilare[m]> Maybe this can be used as a co processor, has enough peripherals and it says ultra low power.
May 12 21:23:08 <vedant16[m]> <m_w "they are going to be tricky to w"> what's waferscale packaging?
May 12 21:28:13 <OmkarBhilare[m]> https://twitter.com/johndmcmaster/status/1392338460493574146?s=21
May 12 21:28:49 <OmkarBhilare[m]> Chips are sent out in this package, right?
May 12 21:28:49 <OmkarBhilare[m]> Or does they did something different only for strive chips.
May 12 21:29:20 <OmkarBhilare[m]> * Chips are sent out in this package, right?
May 12 21:29:20 <OmkarBhilare[m]> Or they done something different only for strive chips.
May 12 21:32:50 <m_w> vedant16[m], https://en.wikipedia.org/wiki/Wafer-level_packaging
May 12 21:34:48 <m_w> OmkarBhilare[m], I think that they are using QFN on strive
May 12 21:35:25 <OmkarBhilare[m]> What will I receive?
May 12 21:35:25 <OmkarBhilare[m]> Each project will receive 50 packaged parts and 5 evaluation boards assemblies based on prefixed package and board designs.
May 12 21:35:37 <OmkarBhilare[m]> This was one mpw shuttle one site
May 12 21:36:09 <m_w> OmkarBhilare[m], did you submit a project on mpw one?
May 12 21:36:27 <OmkarBhilare[m]> Nope, missed it.
May 12 21:37:51 <OmkarBhilare[m]> * This was on mpw shuttle one site
May 12 21:38:48 <m_w> oic
May 12 21:43:31 <vedant16[m]> > <@ombhilare99:matrix.org> What will I receive?
May 12 21:43:31 <vedant16[m]> > Each project will receive 50 packaged parts and 5 evaluation boards assemblies based on prefixed package and board designs.
May 12 21:43:31 <vedant16[m]> 50 parts, that's a lot
May 12 21:43:36 <vedant16[m]> <m_w "vedant16, https://en.wikipedia.o"> ohh
May 12 21:50:16 <m_w> https://github.com/samlittlewood/caravel_carrier
May 12 21:50:39 <m_w> here is a PCB based on the carrier chip
May 12 21:51:00 <m_w> notice the pattern in the middle that looks like a BGA
May 12 21:51:32 <m_w> not for the novice solder tech
**** ENDING LOGGING AT Thu May 13 02:59:56 2021