**** BEGIN LOGGING AT Mon Mar 17 02:59:58 2014 Mar 17 03:02:04 ok, what about a nice map of all the GPIO that the PRU cores can access? Mar 17 03:14:32 kristina: the AM and DM series from the catalog group share some of the same lineage as the OMAP, but they are not OMAP Mar 17 03:14:55 kristina: so asking about OMAP will give you answers for OMAP, which may not be what you really want Mar 17 03:15:10 prpplague: My grief is with OMAP5, but literally no one is willing to help me in any other channels. Mar 17 03:15:21 I am literally out of options. Mar 17 03:15:24 kristina: hehe Mar 17 03:15:29 So I'm asking everywhere. Mar 17 03:15:48 kristina: yes, your grief is well deserved, should i give you delagi's email address? Mar 17 03:15:59 Who's that? Mar 17 03:16:19 kristina: the senior TI management that killed the OMAP division at TI Mar 17 03:16:29 kristina: which OMAP5 board are you working with? Mar 17 03:16:34 prpplague: I think I hit a hardware bug on OMAP5. Mar 17 03:16:38 OMAP5432 ES2 Mar 17 03:16:42 UEVM Mar 17 03:16:50 HAHAHAHA Mar 17 03:17:22 * prpplague laughs loudly and goes back to drinking beer Mar 17 03:17:23 prpplague: When running on top of a hypervisor, some really weird shit happens in terms of data coherency. Mar 17 03:17:36 kristina: yea, i expect it would Mar 17 03:17:45 There seems to be an invisible cache. Mar 17 03:17:53 That is not defined anywhere according to the spec. Mar 17 03:17:54 * ds2 spikes the beer with vodka Mar 17 03:18:19 But this invisible cache is not always coherent with RAM (even when D+I caches are off). Mar 17 03:18:28 However, when the TLB is flushed. Mar 17 03:18:35 The invisible cache loses it's data. Mar 17 03:18:54 kristina: these are some known issues with OMAP5 Mar 17 03:19:10 kristina: only the green hills folks have resolved a bunch of the issues Mar 17 03:19:22 kristina: omap5 is dead, i really suggest you look for something else Mar 17 03:19:33 prpplague: Is there a workaround for that issue in software? Because otherwise this problem makes developing for OMAP5 impossible. Mar 17 03:20:22 It's impossible to make sure that this invisialbe cache is flushed. Mar 17 03:20:33 kristina: like i said, delagi closed the OMAP division down, so there is no one directly working on resolving the omap5 issues. green hills is still using omap5 for some of their automotive work Mar 17 03:20:46 kristina: but that work is only in preparation for jacinto6 stuff Mar 17 03:20:56 Why did the OMAP division die? Mar 17 03:21:12 i'm having some troubles getting my bbb to flash the emmc from SD. when i boot and hold down the boot switch with the usd card with ubuntu 12.04 in the slot, three of the four user LEDs come on and just stay on Mar 17 03:21:19 And why is the hardware so buggy? Mar 17 03:21:25 kristina: hehe Mar 17 03:21:41 kristina: plenty of info on google with regards to the close of the WTBU group inside TI Mar 17 03:21:47 prpplague: It feels like the Cortex-A15 extensions for OMAP5 were really half-assed. Mar 17 03:22:47 So many places in which it just doesn't follow the spec. Mar 17 03:22:58 kristina: as far as the hardware goes, as the designer of the omap5432-uevm (otherwise known as PandaBoard5), i can tell you that the OMAP5 processor is poorly implemented, basically unsupported, and only minimally tested Mar 17 03:23:19 Oh god. Mar 17 03:23:39 prpplague: What you just said literally makes me want to burst in tears. Mar 17 03:23:51 I spent weeks getting things like Xen working on OMAP5. Mar 17 03:23:58 * prpplague hands kristina some tissue Mar 17 03:24:05 Only to find out that I can't do much because of hardware bugs. Mar 17 03:24:31 Oh my god. Mar 17 03:24:34 I have no words. Mar 17 03:24:49 kristina: unless you are planning to transition to jacinto6 for some auto applications, i recommend abandon omap5 immediately Mar 17 03:25:14 I was messing with getting Xen to work and virtualize Linux/Darwin. Mar 17 03:25:54 prpplague: I wrote some code that saved 1000 or so DWORDS from the stack before a TLB flush and compared them after. Mar 17 03:26:07 They were different. Mar 17 03:26:16 But only sometimes. Mar 17 03:26:40 Turns out that while the writes are visible to the local CPU, they are not commited to RAM. Mar 17 03:27:10 And after a TLB flush ... some random DWORD would drop out of this magic cache. Mar 17 03:27:27 There was no reasonable explanation. Mar 17 03:27:43 kristina: like i said, this was a know issue, iirc there were some work arounds that were implemented in u-boot and kernel, but only the green hill folks are doing any serious work on omap5 at this time Mar 17 03:28:05 prpplague: Oh, this is a known issue? Mar 17 03:28:11 kristina: yes Mar 17 03:28:16 kristina: http://www.eetimes.com/document.asp?doc_id=1262782 Mar 17 03:28:57 Is there a patch? Can you please link it? There is still a ray of hope ... Mar 17 03:29:02 kristina: omap5 has basically been no-supported since november of 2012 Mar 17 03:29:17 Is there is a software hack to work around this weird TLB stuff. Mar 17 03:29:18 kristina: like i said, only the green hill guys are doing any serious support of omap5 Mar 17 03:29:32 "iirc there were some work arounds that were implemented in u-boot and kernel" Mar 17 03:29:57 yes, from the green hill folks Mar 17 03:30:01 I can integrate that workaround into Darwin-ARM. Mar 17 03:30:07 Oh, are they mainlined? Mar 17 03:30:12 kristina: no Mar 17 03:30:16 CRAP Mar 17 03:30:34 http://www.ghs.com Mar 17 03:30:35 prpplague: How hard would it be to contact them? Mar 17 03:32:19 kristina: not hard at all..... just make sure you have your CC number handy Mar 17 03:32:27 prpplague: So personally, do you know much about that particular issue? Mar 17 03:32:48 kristina: like i said, i designed the OMAP5432-UEVM..... Mar 17 03:33:15 prpplague: Can you please help me? :( Please? Mar 17 03:33:21 kristina: and no, i am not helping you with it unless you have you CC number handy.... recommendation - move to something other than omap5 Mar 17 03:33:36 Credit card? Mar 17 03:33:55 Or what? Mar 17 03:34:01 yea credit card Mar 17 03:34:18 How much would you charge for that? :O Mar 17 03:34:28 It's a hobby project. Mar 17 03:34:43 Entirely non-commercial. Mar 17 03:34:47 hehe, more than you can afford as a hobby project, hehe Mar 17 03:34:59 * prpplague wanders off Mar 17 03:35:01 * kristina cries Mar 17 03:35:11 Is it easy to work around that issue? Mar 17 03:35:24 Or can you at least tell me more? Mar 17 03:36:49 God damn it, so this project is screwed. Mar 17 03:37:28 There is no way I could have known OMAP5 would have these issues. Mar 17 03:47:45 Can I at least get a more detailed description of the issue? Mar 17 03:48:58 I'm sorry if I sound rude but what you just said sounded like "We don't care about you, and if our HW has bugs, it's not our problem" Mar 17 03:51:36 i dont think anyone ever said the omap was supported by anyone Mar 17 03:52:06 JFK911: The hardware has a blatant and serious bug. Mar 17 03:52:13 maybe thats why everyone left it Mar 17 03:52:24 sucks if you paid for hardware Mar 17 03:52:38 but uh there is a reason ti didnt want to sell it to anyone Mar 17 03:52:43 JFK911: I wasted weeks during bringup of my software. Mar 17 03:52:53 thats a terrible result Mar 17 03:52:58 Only to hit a permament roadblock. Mar 17 03:53:19 Because of a hardware bug that is not described anywhere and without a PoC software fix. Mar 17 03:53:32 How do you think I feel like right now? Mar 17 03:53:49 mad Mar 17 03:53:53 Yes. Mar 17 03:53:55 Fucking mad. Mar 17 03:54:43 seems like ti refuses to sell it now Mar 17 03:54:58 before, you had to be on some elite list to buy it Mar 17 03:55:05 This has ruined my day. Mar 17 03:55:23 why did you have your heart set on this thing Mar 17 03:55:41 No one told me the HW has a really severe bug. Mar 17 03:56:05 I could not have known that the A15 extensions to the OMAP platform were half-assed and poorly tested. Mar 17 03:56:26 you never know what you will find when you wander into the forest by yourself Mar 17 03:56:55 How is that a defense? The product blatantly doesn't do what it's required to do? Mar 17 03:57:40 It's the vendors job to make sure their silicon works. Mar 17 03:58:11 the vendor decided to stop selling it Mar 17 03:58:35 its not a defense its a risk you take Mar 17 03:58:50 The why do I have a UEVM board right next to me? Mar 17 03:58:56 I should not have it. Mar 17 03:58:58 i passed on this chip because of the support conditions Mar 17 03:59:27 Or what about the ISEE folks? Mar 17 03:59:38 They also sell their OMAP5 boards? Mar 17 03:59:54 Probably with the same buggy silicon. Mar 17 03:59:59 they are selling the chip on the board that they made. Mar 17 04:00:01 yes probably. Mar 17 04:00:12 maybe they have some software, maybe they want to be paid for it Mar 17 04:00:58 So a cache is broken? Mar 17 04:01:45 ALL caches are off. Mar 17 04:02:16 And some memory does not work reliably? I dont have a full understanding of what you are facing Mar 17 04:02:42 1). Dump 1000 DWORDs from the stack 2). Flush TLB 3). Dump those 1000 DWORDS again, and if they mismatch, abort. Mar 17 04:02:54 In about 1/2 of the boots, this issue occurs. Mar 17 04:03:17 One DWORD does not get commited to physical RAM. Mar 17 04:03:33 Instead it goes into WTFCACHE Mar 17 04:03:57 Which is okay, because the write is still observed locally, because WTFCACHE caches it. Mar 17 04:04:12 But if you flush TLB, WTFCACHE loses the data. Mar 17 04:04:34 So the STR you made earlies never enters RAM. Mar 17 04:04:43 This is with ALL caches off. Mar 17 04:04:58 But WTFCACHE can't be turned off. Mar 17 04:05:06 It shouldn't even exist. Mar 17 04:05:13 You think maybe you can work around it with some timing rain dance? Mar 17 04:05:28 What do you mean? Mar 17 04:06:11 by doing something stupid by writing twice, or trying to fool it by making spurious writes to scratch ram or nonexistent memory Mar 17 04:06:27 Guys, I am trying to connect my BBB with Eclipse for Remote Systems, but I always have this error once I want to go to home or root "Make sure that the DataStore daemon is running on 192.168.7.2.", any suggestions? Mar 17 04:06:33 stuff that you would think is retarded and nonsense but sometimes you just have to do Mar 17 04:06:51 The data that gets stuck in WTFCACHE is a PUSH {PC, R7} instruction. Mar 17 04:07:03 The push'd data enters WTFCACHE. Mar 17 04:07:04 which register is the target Mar 17 04:07:44 The PC and R7 get commited to WTFCACHE (instead of physical ram?!?!) Mar 17 04:08:12 If I read them back, they get read back from WTFCACHE Mar 17 04:08:22 If I flush the TLB. Mar 17 04:08:29 WTFCACHE will lose a DWORD of data. Mar 17 04:08:51 what if you lookup the stack pointer, write your junk, and adjust the stack pointer Mar 17 04:08:53 WTFCACHE seems to cache one recenty written DWORD of data. Mar 17 04:09:43 I need to make sure that this DWORD of data actually enters physical memory. Mar 17 04:09:59 is the memory on die? Mar 17 04:10:07 No. Mar 17 04:10:21 probe it with a logic analyzer and find out what you need to do to ensure the write Mar 17 04:11:19 Everything results in a write unless WTFCACHE caches it. Mar 17 04:11:33 WTFCACHE is unpredictable. Mar 17 04:11:52 I can just do lots of reads and writes of dummy data. Mar 17 04:11:59 To attempt to get WTFCACHE to fuck off. Mar 17 04:12:08 And flush itself. Mar 17 04:12:10 if it works sometimes, then there has got to be a way to ensure it works in software. Mar 17 04:12:25 I think I can just flood it with IO. Mar 17 04:12:42 Which will eventually retrigger the WTFCACHE bug and force it to commit. Mar 17 04:13:24 there must be a minimum number of steps you can do to guarantee the result. Mar 17 04:13:31 youve got a puzzle to figure out. get to work. Mar 17 04:13:47 unless you want to hunt for someone who fixed it and put their binary into idapro Mar 17 04:14:09 Everyone wants money. Mar 17 04:14:23 If it's linux it's GPL. Mar 17 04:14:36 They are legally obliged to release the source if they give me the binary. Mar 17 04:14:37 money for binaries is not really a good business case Mar 17 04:14:55 arent they obliged to release the source anyway? Mar 17 04:15:07 Only if they release the binary. Mar 17 04:15:33 If you compile a GPL'd program and give it to someone, you're obliged to give that person the sources too. Mar 17 04:15:44 i got source code for a kernel from shop equipment out of a carmaker. i think they knew that i did not buy the shop equipment. it costs as much as a house and there is a list of people who are allowed to buy it. Mar 17 04:16:53 Also, if you ship a product with GPL'd binaries on it, you have to publish the source code. Mar 17 04:18:06 You might try and fool people with a sticker that looks like a vxworks sticker. Mar 17 04:18:31 I got sources for many things. Mar 17 04:18:50 VxWorks, ThreadX, SGX DDKs, Mali DDKs etc Mar 17 04:19:30 can't you buy vxworks source? Mar 17 04:19:42 Sure, with lots of money. Mar 17 04:24:48 Fuck it, if no one who can help me will, I will try to implement the workaround myself or die trying. Mar 17 04:24:54 I don't give up like that. Mar 17 04:25:23 it sounded like you were about to Mar 17 04:25:37 that other chap seemed to imply that you'll run into more trouble Mar 17 04:26:09 I am not going to let TI win like this. Mar 17 04:32:53 have you checked whether the issue also exists w.r.t. on-chip SRAM ? (almost done reading backlog on this...) Mar 17 04:34:16 hmm, nm, the thought I had doesn't make sense for the symptoms you're describing, I misread Mar 17 04:35:16 or maybe it does... "one recenty written DWORD of data" .. like maybe a write-buffer or so? Mar 17 04:35:40 no idea why it would be affected by a TLB-flush though Mar 17 04:37:00 hello frnds, Is there any way to reload the g_multi module. My requirement is to copy a file to BEAGLE_BONE partiotion from Angstrom and access it from PC. Now this feature is working but if we write or modify that file multiple times , the modifications not immediately reflects in BEAGLE_BONE partiotion in PC side. It shows some type of delayed write. Once the beaglebone black restarts, it shows the correct modified file. Why this del Mar 17 04:38:51 zmatt: All caches are off at that point. Mar 17 04:38:59 cache != write buffer Mar 17 04:39:19 How do I drain the write buffers? Mar 17 04:40:02 None of the barrier instructions seem to help. Mar 17 04:40:03 they should do so quickly normally, but maybe there's some weird bug Mar 17 04:40:12 Can I force it? Mar 17 04:40:30 I'm assuming your current issue is with data stored in DRAM right? Mar 17 04:40:46 testing whether the issue also exists with on-chip SRAM would at least narrow it down Mar 17 04:41:11 Yes, a DWORD of data gets caught up in between CPU->WTFCache->DRAM Mar 17 04:41:50 Nothing should get caught in WTFCache because it loses its data on TLB flushes. Mar 17 04:43:33 yea losing data on tlb flush is really weird... Mar 17 04:44:07 hmm Mar 17 04:44:53 In this particular case, the DWORD that is corrupted happens to be on the stack. Mar 17 04:45:09 it does look like the omap5 does mpu-emif interfacing quite differently, compared to earlier devices Mar 17 04:45:25 no ELLA-port to the DMM, but direct interfaces to the EMIFs Mar 17 04:45:29 curious Mar 17 04:45:47 that's new, hence a good place for a bug Mar 17 04:46:18 This only happens when a hypervisor is on. Mar 17 04:46:37 This bug does not occur on bare bones execution. Mar 17 04:46:46 hmz Mar 17 04:47:46 I've never worked with the A15, so it's tricky for me to extrapolate from the knowledge I do have Mar 17 04:48:49 still, if you can easily check a test-case against a different memory region, then I would recommend trying: a. some on-chip SRAM and b. the external DRAM but accessed via TILER rather than directly Mar 17 04:51:02 How do I access it via TILER? I don't even know what TILER is. See how hard this is for me. Mar 17 04:51:06 I'm not TI. Mar 17 04:51:14 neither am I Mar 17 04:51:20 And I'm trying to hunt down a silicon bug in the HW. Mar 17 04:51:36 oh I've found plenty in the dm8148 I'm working with Mar 17 04:52:15 prem: try "sync" Mar 17 04:52:29 shit happens, these chips are enormous and bugs will no doubt be all over the place Mar 17 04:52:56 zmatt: http://crna.cc/EiTX1SSWWq6KJJ5 Mar 17 04:53:02 Can you take a look at that? Mar 17 04:54:10 Er, sec, I'll remove some junk. Mar 17 04:54:41 hehe, I guess there's no such thing as too many barriers ;-) Mar 17 04:54:44 zmatt: http://crna.cc/QJoRhVsEb4vyR5A Mar 17 04:54:54 zmatt: I was desperate. Mar 17 04:54:59 Trying everything. Mar 17 04:55:00 I can understand Mar 17 04:55:06 Sprinkled the barriers everwhere. Mar 17 04:55:41 I linked you a version without the irrelevant routine. Mar 17 04:56:27 hash_fail gets hit on around 2/3 of the boots Mar 17 04:58:30 I'm not sure what you hope I'll be able to say after looking at this though... Mar 17 04:59:00 But is there a reason for why the second check will fail? Mar 17 04:59:10 Other than a hardware issue? Mar 17 04:59:21 (keep in mind caches are off) Mar 17 04:59:44 I'm not sure what caches have to do with things here anyway, you're flushing TLB, not a cache Mar 17 04:59:57 Right. Mar 17 05:00:25 flushing TLB should have no effect whatsoever unless you've just changed some page tables or something Mar 17 05:00:33 And the translation tables remain the same, but I do write to TTBR1 and TTBR0 Mar 17 05:00:40 It's the same mapping. Mar 17 05:00:50 I checked that it matches. Mar 17 05:00:55 hmm Mar 17 05:00:58 You can see the VtP code there as well. Mar 17 05:01:27 The physical address to which the SP-rel stuff gets resolved to remains the same. Mar 17 05:01:48 I tried to isolate any bugs that could come from my own code. Mar 17 05:02:07 (ie look at v7_vtop) Mar 17 05:02:32 > ARM: tlb: don't perform inner-shareable invalidation for local TLB ops Mar 17 05:02:56 that's one line in a git commit when googling for: a15 tlb bug Mar 17 05:03:17 This only occurs when running with a hypervisor by the way, Mar 17 05:03:25 Bare metal works without a hitch. Mar 17 05:03:51 On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down all use of the old entries. Mar 17 05:06:07 which rev is in your device? Mar 17 05:06:39 What's the rev for OMAP5432 ES2.0? Mar 17 05:08:19 how should I know :P pull it out of CP15 Mar 17 05:08:30 c0,0,c0,0 Mar 17 05:08:46 One sec, will build a baremetal XNU. Mar 17 05:09:49 this is why I love having a Forth system running on my target Mar 17 05:10:44 I can type $f0000 cr? and get my answer right away ;) Mar 17 05:12:44 but I'm guessing then that you haven't checked the Cortex-A15 errata yourself yet? Mar 17 05:12:51 zmatt: mrc p15, 0, r0, c0, c0, 0 ? Mar 17 05:12:57 yes Mar 17 05:13:21 0x412fc0f2 Mar 17 05:15:00 ok, so that would be r2p2 Mar 17 05:16:45 zmatt: Is this explained in the ARM ARM (this issue)? Mar 17 05:17:22 interesting, r2p2 isn't listed on the ARM website Mar 17 05:17:30 it goes from r2p1 to r3p0 Mar 17 05:17:49 If you can help me with this I will love you forever. Mar 17 05:17:50 that register will be in the ARMv7A yes Mar 17 05:18:26 I meant the actual "note" about the bug. Mar 17 05:18:26 you should also get the A15 TRM and errata (for the errata you'll need to register on the ARM website if you haven't already) Mar 17 05:18:36 errata are in the errata obviously Mar 17 05:18:38 zmatt: I have it in front of me. Mar 17 05:18:42 not in an architecture manual Mar 17 05:18:49 Oh. Mar 17 05:18:59 ARM® Architecture Reference Manual Mar 17 05:19:00 ARMv7-A and ARMv7-R edition Mar 17 05:19:03 Not this one? Mar 17 05:19:19 that describes how things are *supposed* to work Mar 17 05:19:31 which may or may not match reality ;) Mar 17 05:19:56 also the architecture covers many processors Mar 17 05:20:02 Topic closedARM Cortex-A15 MPCore - NEON Software Developers Errata Notice Mar 17 05:20:05 This one? Mar 17 05:22:25 I'm still browsing myself... the revision-thing is weird... I suggest getting the docs for r2p1 and r3p0 Mar 17 05:23:42 Errata has only r0 r1 r2 r3 r4 Mar 17 05:24:09 r2 Mar 17 05:25:31 got it Mar 17 05:26:02 outstanding loads or stores to the old translation might not be globally observed Mar 17 05:26:20 this might lead to data corruption if the physical memory of the invalidated memory region is accessed before the memory requests that used the old translation are complete Mar 17 05:26:32 bingo Mar 17 05:26:58 OH WOW Mar 17 05:27:03 I LOVE YOU Mar 17 05:27:11 if this is it Mar 17 05:27:16 I will be so happy. Mar 17 05:27:18 it does sound like it Mar 17 05:28:21 and I did see patches in at least some git repos, so maybe it is in mainline or at least heading there... I suggest you do some googling, and of course study the errata intensely :) Mar 17 05:29:02 zmatt: I love you. Also, I didn't ever pay attention to erratas. Mar 17 05:29:13 Because my old ARM ARM has Errata markup. Mar 17 05:29:29 Which was neat. Mar 17 05:29:29 yes but that's just documentation errata Mar 17 05:29:37 not chip errata Mar 17 05:29:56 do be sure to get and read the errata for the omap5 also Mar 17 05:30:04 You taught me a really valuable lesson. Mar 17 05:30:20 zmatt: Doesn't the TRM include an errata? Mar 17 05:30:23 hahaha Mar 17 05:30:48 no, the TRM usually explains how things are supposed to work in the wishful thinking of the designers Mar 17 05:31:00 which, fortunately, often reasonably matches reality Mar 17 05:31:30 but no, the TRM do not contain the errata. errata are always published separately (or not published at all but only available on request) Mar 17 05:32:49 zmatt: I can't express my gratitude. Mar 17 05:33:27 :) Mar 17 05:34:01 good luck with getting your board up&running... I think you'll need it Mar 17 05:34:22 I sure will! Mar 17 05:35:14 I hope you have no specific deadline, it will take a lot of time to become familiar with a chip like this Mar 17 05:36:39 anyhow, I'm gonna continue working on my getting mine up&running too ;) Mar 17 05:36:50 zmatt: I've had no issues on beagle whatsoever with OMAP4 though. Mar 17 05:36:52 OMAP3 Mar 17 05:37:01 yea Mar 17 05:37:02 but Mar 17 05:37:48 the beagles have received much more attention from developers in the open source community than most other TI SoCs I think Mar 17 05:38:12 zmatt: Linux has all those erratas but my kernel doesn't. Mar 17 05:38:24 where'd you get your kernel from? Mar 17 05:38:31 It's Darwin. Mar 17 05:38:38 oh yea I saw you mentioning XNU Mar 17 05:38:46 so ehm... why? Mar 17 05:38:57 zmatt: But I do wonder why this issue never affected bare metal. Mar 17 05:39:07 zmatt: I want to run iOS on it. Mar 17 05:39:54 why? no idea, memory-subsystem problems can be a boundless source of fun Mar 17 05:40:19 What do you mean? Mar 17 05:40:38 My Darwin-ARM port works really well, if you forget all the erratas for a second. Mar 17 05:41:30 zmatt: Can you explain what errata categories mean? Mar 17 05:41:40 Like, are there ones that you ABSOLUTELY MUST FIX? Mar 17 05:42:14 I mean that these high-performance chips often have very complicated memory controllers with all kinds of buffering, caches, cross-checks, and many many opportunities for subtle bugs that only surface under very specific circumstances Mar 17 05:42:51 I bet bugs related to those erratas are very common. Mar 17 05:43:04 And the bug I hit here is very obscure. Mar 17 05:43:07 did you find your problem in an errate item? Mar 17 05:43:16 Seems so. Mar 17 05:43:20 I'm writing a fix. Mar 17 05:43:22 i didnt see it Mar 17 05:43:24 which one is it? Mar 17 05:43:59 798181 Mar 17 05:44:09 oh, ARM document? Mar 17 05:44:14 Yeah. Mar 17 05:44:30 Ah I looked in the omap5 errata it looks like its all peripheral stuff there. Mar 17 05:44:59 yes, TI refers you to ARM for the core errata Mar 17 05:45:11 i didnt see an easy link to it on ti's product page Mar 17 05:46:04 (after which ARM referred me to my TI FAE, who referred me back to ARM, who then contacted TI directly and eventually errata did appear in my inbox) Mar 17 05:48:10 no idea why the A8 errata are such a fuss to get a hold of... at least the A15 errata are simply available for download (to registered users) Mar 17 05:48:37 I didn't know erratas existed. Mar 17 05:48:40 I feel like an idiot. Mar 17 05:48:55 I thought all ARM's designs were flawless. Mar 17 05:48:58 D: Mar 17 05:50:13 yea I used to have an idealized picture of hardware too, before I started working with it Mar 17 05:50:40 But I mean, I did so much low level work with ARM stuff. Mar 17 05:50:48 And this is the first time. Mar 17 05:51:03 I hit a bug like that. Mar 17 05:52:05 well they've been getting more and more complicated, hence more bugs too Mar 17 05:56:29 errata is already plural, like data. erratum Mar 17 05:56:43 some of the older C6000-series DSPs had some fun ones too... while searching for info I came across one doc which described a bug which caused the logic to get clocked before it got initialized, leading to a small probably (on each boot) that the eFUSE controller would proceed to blow a random fuse Mar 17 05:56:53 zmatt: OUCH Mar 17 05:57:00 aaahaha was there a workaround for that Mar 17 05:57:16 yea it only happened with specific power-on sequencing Mar 17 05:57:41 one of the stellaris chips had a poweron erratum like that too, it would erase flash or something Mar 17 05:57:50 Hehe. Mar 17 05:57:52 so hopefully you hadn't produced many boards with the wrong timing yet Mar 17 05:58:44 or else, well, don't power-cycle your board too often ;) I'm not sure how long they'd last when playing russian roulette with eFUSE Mar 17 06:00:38 the cache coherency issues of early C64x+ revisions also look like they were fun... never seen so many drawing and diagrams in an errata doc Mar 17 06:01:47 (another instance of "fun with memory systems") Mar 17 06:05:43 that erratum is an informative doc about the DSP's memory subsystem though, more details then you'd find in a TRM Mar 17 06:19:00 hi Mar 17 06:19:22 That did not seem to work :O Mar 17 06:20:38 hi Mar 17 06:21:09 anyone here ? Mar 17 06:22:30 wazzuuup Mar 17 06:23:32 zmatt: http://crna.cc/WfTQ9HtqT61UH3G Mar 17 06:26:31 kristina: I'm sorry, I really have other things I need to be working on right now... Mar 17 06:26:37 D: Mar 17 06:26:59 Is there any other time I can ask you? Mar 17 06:30:41 look, I've never worked with the omap5 nor with the cortex-a15. all I did was google and report what I read, this is something you should be able to do too. an hour ago you hadn't even looked at the errata yet, and after one attempt at resolving your issue you're asking for my help again... Mar 17 06:31:43 and you're trying to get an unusual choice of kernel running on, apparently, a buggy chip Mar 17 06:31:46 this will take time Mar 17 06:32:33 go read the trms, read the errata, do experiments, get to know that chip like the back of your hand... eventually you will figure it out and it'll seem obvious all along Mar 17 06:35:09 Google is my friend. he made me secure my diploma and a job. hihihi Mar 17 06:35:17 lol Mar 17 06:51:07 Guys, how can you stop a java code to run at beaglebone? for example i 'java test' (it runs about 40 secs until it stops) I want to interrupt it Mar 17 06:51:16 <_av500_> CTRL-C Mar 17 06:52:37 thanks! Mar 17 06:55:48 SeanMark: looks like google isnt your friend anymore Mar 17 07:09:12 * kristina sobs quitely Mar 17 07:18:37 On the bright side, I have added this erratum to my kernel. Mar 17 07:18:55 On the not-so-bright side, I still have this problem. Mar 17 07:26:23 @KotH This irc is my 2nd friend. hahaha Mar 17 07:27:32 * KotH hands kristina a handkerchief and some chocolate Mar 17 07:27:53 KotH: I've implemented the erratum though *sob* Mar 17 07:28:27 welcome to the real world. where there are more problems to implementing stuff than what is written in the documentation Mar 17 07:28:38 Also. Mar 17 07:28:39 This erratum does not affect the processor if the revision and variant reported by the MIDR is r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[4] is set to 1. Mar 17 07:28:46 (not to mention that the documentation can be wrong) Mar 17 07:28:52 REVIDR[4] = 1 Mar 17 07:29:10 hmm? processor != core Mar 17 07:30:16 Processor = all cores. Mar 17 07:31:49 TI's erratum just talks about peripheral stuff. Mar 17 07:32:42 errata Mar 17 07:33:00 I keep getting it confused, erratum would make more sense as a plural. Mar 17 07:34:15 Maybe I need to make sure Xen also follows this Erratum. Mar 17 07:35:17 People mix it up a lot anyway. Mar 17 07:36:50 errata is plural Mar 17 07:37:06 .o0(know thy latin) Mar 17 07:37:08 I know, but it sounds as if it's singular. Mar 17 07:37:23 you never had latin, did you? Mar 17 07:37:32 No. Mar 17 07:37:33 BOARD_ERRATA_798181 Mar 17 07:37:37