**** BEGIN LOGGING AT Fri Feb 27 02:59:58 2015 Feb 27 03:00:16 It would be nice if they would put some of those 64bit ARMs with 64bit buses and real big space. I was eyeing the keystone SoC's which are a bit bigger but I am not going to do any BGA layout I have trouble enough with QFN Feb 27 03:00:36 still weird that a chip with ARM + DSP + IVA-HD + video processing gets branded as a Sitara AM-part... that feels kind of like a death sentence for the DaVinci brand Feb 27 03:00:42 lol, a bit bigger... Feb 27 03:01:23 4 arm cores and dsp cores nice huh? Feb 27 03:02:07 Oh yes the 2 1G and built in ethernet switch with 4 100T lines Ld Feb 27 03:02:12 keystones are afaik intended for things like 4G cellular barestatiosn Feb 27 03:02:50 Yes but they would make a great mini super computer Feb 27 03:03:39 (the WCDMA receive and transmit coprocessors, turbo decoders, viterbi decoders, "bit rate coprocessor" supporting "WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A and WiMAX Uplink and Downlink Bit Processing" are also a hint of course) Feb 27 03:04:45 there's some crazy PCI card with four KS2s on it (total 16 DSP cores) Feb 27 03:04:45 Great for sattelite com Feb 27 03:05:58 Or over land short haul point to point (could get 50km with proper noise floor) big issue them becomes earth curvature of course (stupid earth getting in the way) Feb 27 03:06:56 but you get relatively little "normal IO" on keystones... like they only added USB (one port) in keystone2, and even the am335x has more GPIO Feb 27 03:08:23 (and they're... not cheap) Feb 27 03:11:07 but vayu is pretty nuts too in a different way... although not all of it available on the am527x, that thing has iirc 10 digital video inputs :P Feb 27 03:12:44 *am572x Feb 27 03:16:57 also, if you need another pin available, at least on my BBB (an A5A) the eMMC reset signal isn't actually enabled in the eMMC device, so the pin is ignored Feb 27 03:17:01 :P Feb 27 03:18:26 I've noticed most of TI's SoC's are a bit too specialized at times. Feb 27 03:19:20 they're made for one or a few big application domains, and the leftovers become broadmarket parts Feb 27 03:20:40 Seems a repeated pattern of 'over thinking' parts. Atmel has more broad scoped parts and they do better in industrial as a consequence. Feb 27 03:21:37 * zmatt has no idea how well TI is doing, so has no comment really Feb 27 03:22:09 intuitively I can understand the strategy of going for hw + sw "solutions" Feb 27 03:23:07 Their arm line ... for industrial I will politely call "tolerable" but can't be used? Feb 27 03:23:45 well the am335x *is* specifically targeted at industrial applications Feb 27 03:24:02 The BBB SoC is the BEST of their industrial parts and it's all quirky :D Feb 27 03:24:33 I haven't met a processor yet that *isn't* quirky Feb 27 03:24:46 im glad the am335 thing has a regular m4 instead of the oddball pru, might have more generalised support ? Feb 27 03:25:54 bwarff__: you mean the am572x ? it has two dual-core cortex-m4 subsystems (four cores total) *and* two PRU subsystems (four cores total) Feb 27 03:26:11 my mistkae Feb 27 03:26:14 the M4 is no replacement for PRU though Feb 27 03:26:18 A standard ISA is wonderful in terms of support. Feb 27 03:26:20 (nor vice versa) Feb 27 03:26:39 the m4 cant share memory with the main cpu ? Feb 27 03:27:01 eh, sure they can Feb 27 03:27:11 local memory is faster to access obviously Feb 27 03:27:26 what does the pru have then ? Feb 27 03:28:08 PRU is essentially a fancy bitbang-engine ... it's used to emulate all sorts of weird bus interfaces Feb 27 03:28:32 which relies on its extremely simple timing Feb 27 03:31:03 the IPUs (cortex-m4 subsystems) are an evolution of the "ducati" dual cortex-m3 subsystem which is mainly used to micro-manage video-related peripherals without burdening the main cpu (especially since that management may be relatively simple, but is also hard real-time if you don't want video to stall/glitch) Feb 27 03:32:05 of course they can also be used for a variety of other applications Feb 27 03:32:27 if they make sure their is spme mbed style fat libs for them so they can be used like regular micros it would make that board quite cool Feb 27 03:34:30 except they're not regular micros, and never will be Feb 27 03:35:16 in what way ? Feb 27 03:35:44 they're cores on a honkin' bigass SoC, they communicate with peripherals over a packet-switched network Feb 27 03:35:45 my hope would be some io pins and the ability to manage sensors/blah independantly of the main cpu Feb 27 03:36:31 not to mention I don't think I've ever seen a "dual-core" cortex-m3/m4 ... and that's actually slightly tricky to work with since they have exactly the same memory image (apart from the PPB) Feb 27 03:36:55 (there is an MMU but it's shared by the two cores, no separate mappings) Feb 27 03:38:35 but sure you could reserve some peripherals/io for them specifically Feb 27 03:38:41 The hercules IC does the same thing with ARM cores for ultra high reliability Feb 27 03:38:52 hmmm that's not the same thing Feb 27 03:38:56 the new imx6 blah does aswell i think Feb 27 03:38:59 the IPU cores don't run in lock-step Feb 27 03:39:01 they're independent Feb 27 03:39:22 hrmm Guess so but the concept is similiar no? Feb 27 03:39:44 no Feb 27 03:40:04 two cores in lock-step behave like one core Feb 27 03:40:08 but more reliable Feb 27 03:41:28 also they use cortex-R, not -M Feb 27 03:42:01 -R rotten right? :D Feb 27 03:42:50 btw, don't forget the am335x has a cortex-m3 also... it's officially just intended for assisting with suspend/resume, but that doesn't mean you can't use it for other purposes... the main limitation is that it only connects to the L4WK which limits the peripherals you can use Feb 27 03:43:12 (unless you use some ugly hack involving EDMA) Feb 27 03:45:19 ohhh that sounds like fun ... heh Actually good for turning stuff on and off but IO access of some sort would be handy. Feb 27 03:45:40 the L4WK is not devoid of peripherals :P Feb 27 03:47:32 two of the two timers, one gpio bank, one uart, one i2c, and the adc/tsc Feb 27 03:48:02 uart and an i2c covers lots of cases. Feb 27 03:49:03 and you'll need to avoid writing bloatware, since the cortex-m3 has only 24 KB memory total and no (direct) access to main memory Feb 27 03:49:41 Looks like it's primary purpose is to keep things operating can it force the main processor to reset? Feb 27 03:50:06 if it can manage the power to the main processor its perfect for our use cases actually. Feb 27 03:50:24 which is a micro doing basic sensor jobs and waking up the big board when things get interesting. Feb 27 03:50:41 it doesn't keep anything operating, it's in reset until the cortex-a8 loads firmware onto it (I'm not even sure mainline linux does at all), and then spends most of its time in WFI Feb 27 03:52:01 when the cortex-a8 wants to suspend, it informs the m3 of the relevant wakeup sources, requests PRCM to turn itself off, then enters WFI to acknowledge PRCM's idle-request Feb 27 03:52:22 if it succesfully enters idle, the M3 gets an IRQ and is now in charge Feb 27 03:53:24 it can then make sure the relevant wakeup sources are enabled, and turns off the light Feb 27 03:55:11 I'm not sure it can forcibly reset or powerdown the cortex-a8... it might, but it's not meant to... the cortex-a8 is supposed to cooperate by entering WFI Feb 27 03:56:53 (also to ensure all pending interconnect transactions are finished, some previous SoCs had problems where the cortex-a8 could be suspended with a transaction still open, leading to desynchronization and lockup requiring chip reset to resolve) Feb 27 04:00:42 sounds sane enough Feb 27 04:01:45 also, with a minor hw patch the cortex-m3 can use JTAG on the SoC and totally 0wn the cortex-a8 ;) Feb 27 04:04:08 that would be good for bugging err debugging Feb 27 04:10:47 https://github.com/dutchanddutch/jbang Feb 27 04:11:53 still contains a minor issue though... I kinda assumed bitbanging this way would be "slow enough", but there are indications this may not be the same so actual delays should be inserted Feb 27 04:13:04 and it's still missing an OCP barrier necessary to guarantee ordering between control module writes and gpio reads Feb 27 04:14:05 watchpoints are very useful though, and it's annoying you have to jump though such hoops to allow the cpu to use them Feb 27 04:18:29 I've learned that SW delays never work right. You can use the timers you have for help with delays that are consistent at least. Feb 27 04:18:48 eh, why wouldn't usleep work right? Feb 27 04:18:55 (note that there's no harm in delaying too much) Feb 27 04:19:11 (in this case) Feb 27 04:22:04 Well I had a 40 usec delay on a radio loop SW wasn't consistent enough (stupid radio hardware) so I had to use a timer to wake the processor up after it counted correctly. Didn't have a magic usleep so HW was put too good use. Delays cost you on RF com (I hate radio com). Feb 27 04:23:10 Anyhow I'lll see if I can dig up my old BBB project and look at what I did to make sure power isn't messed up. Feb 27 04:23:21 night all Feb 27 04:23:23 ok, but that's a very different situation.. jtag doesn't require any consistent timing Feb 27 04:23:34 Lucky you huh? :D Feb 27 04:24:34 I should probably get some sleep too Feb 27 06:05:46 Anyone mentoring for PRUduino ? High-level language support with PRU ? Feb 27 06:18:56 When controlling the LEDS on the BBB, I am using the /sys/class/led/beaglebone:green:usr0 as instructed. Is the beaglebone:green:usr0 actually a device driver with source code that I can use to build my own version? Feb 27 06:19:32 its a kernel driver Feb 27 06:19:41 exposed via the sys filesystem Feb 27 06:19:59 yes, source is available Feb 27 06:20:12 but for GPIOs and LEDs you dont need to write a new driver Feb 27 06:22:36 OK. The reason that I ask is I am needing to port a device driver from Gumstix to BBB and wanted to tickle the LEDS to make sure my driver is working. Also wanted to use the beaglebone:green driver as a starting point. Sounds like I may be on the correct path. Feb 27 06:23:16 what kind of driver? Feb 27 06:23:20 why leds if you can just print to kernel console (UART)? Feb 27 06:23:33 UART is so 90's Feb 27 06:23:47 yeah, not even nation state actors need UARTs Feb 27 06:23:55 It is a driver to an FPGA Feb 27 06:24:03 ah Feb 27 06:24:12 SO I will be using mapped memory Feb 27 06:25:29 Thanks for your help. Today is first day getting BBB up and running. Sure is a nice platform. Feb 27 06:47:40 have fun with GPMC Feb 27 12:44:52 Hi Feb 27 12:45:12 I customize Linux embedded to Beaglebone Black with Yocto Project... Perfect! Feb 27 12:45:52 My problem is with net-snmp... install OK.. but to start... Feb 27 12:46:24 pcilib: Cannot open /proc/bus/pci Feb 27 12:46:32 snmpd[15460]: pcilib: Cannot find any working access method. Feb 27 12:47:41 Command lspci same problem Feb 27 12:47:44 Hi, I just switched to Debian on my BBB and i'm looking for the apporpriate toolchain for the cross-compilation from windows Feb 27 12:48:09 And I don't find any Feb 27 12:49:35 CleitonBueno: the device doesn't have pci, that's why Feb 27 12:50:14 Vibouk: I'd recommend a debian wheezy VM. Should be much easier to cross-compile. Feb 27 12:51:12 OK, I know.. but in version net-snmp 5.7.2.1 fix this BUG PCI... same problem continue Feb 27 12:51:18 ho really? I used to cross-compile for Angstrom successfully and quite easilly Feb 27 12:51:39 In Yocto Project the fix in ifmib.patch in the recipe net-snmp Feb 27 12:51:41 Vibouk: ok, then you might go down that same route Feb 27 12:51:46 If I don't have the choice, I will install debian on my pc Feb 27 12:55:05 Suggestion? Feb 27 12:55:39 yeah, I will try to find the good toolchain Feb 27 12:56:13 CleitonBueno: What's your problem? Feb 27 12:57:07 tbr : I will try the Linaro-gcc Toolchain Feb 27 12:57:26 Up net-snmp (snmpd service) and not possible Feb 27 12:57:37 Error Cannot open /proc/bus/pci Feb 27 12:58:01 OK, I know.. but in version net-snmp 5.7.2.1 fix this BUG PCI... same problem continue Feb 27 12:59:13 umm msorry I don't have access to my BBB at the moment so i'm not of any help Feb 27 13:02:10 Strange .. in linux default of BEAGLEBONE lspci command nor is there and the /proc/bus/pci does not exist and the error Feb 27 15:23:54 hi guys I have been trying to get my beaglebone black to take commands from my dualshock3 controller. I have gotten the controller paired and can run some test programs to see input but i cant seem to get things mapped right. I came across some c++ defines on the ros website but those dont seem to work properly either Feb 27 16:07:21 hi everyone ! how can i take a single bit input using a push button ? Feb 27 16:08:37 abch: look up gpio Feb 27 16:09:21 abch: http://www.linux.com/learn/tutorials/765810-beaglebone-black-how-to-get-interrupts-through-linux-gpio Feb 27 16:13:45 OK, so I finally got myself to the beagle with the exact same procedure that Jolla recovery mode used and what was my issue with it Feb 27 16:13:45 1. ifconfig -a, 2. ifconfig eth1 192.168.7.1 3. go to http://192.168.7.2/ using webbrowser Feb 27 16:14:01 this is so important, why I never learned steps 1 & 2 before during these years Feb 27 16:34:16 blaine: i followed this tutorial http://elinux.org/images/b/b7/Beaglebone_-_Hands_on_Tutorial.pdf Feb 27 16:36:28 so you should be good to go Feb 27 16:38:59 blaine: but when i keep pressing the button i need only one output ... how can i go about doing that ? Feb 27 16:40:33 <_av500_> what do you mean? Feb 27 16:40:57 abch: the link i sent earlier exactly describes a push button over gpio -- you should follow that and report back Feb 27 16:42:53 blaine: okay Feb 27 19:43:35 rcn-ee: on osx there's a trouble when packing kernel modules, missing some files like modules.alias, modules.dep and so on Feb 27 20:12:22 Catslab, wonder what generates those.. Feb 27 20:23:05 I'll find :) Feb 27 20:23:39 I'm sure this has something to do with the xargs and so on Feb 27 20:35:51 Catslab, with a lot of these fixes, you should push mainline.. someone might want to boot linux on a mac osx userspace.. ;) Feb 27 21:46:26 <_Pink> hey all. quick question. if I have a prebuild qnx IFS that I am trying to boot using qemu (beaglexm), how would I get it in to, or extract from it, a binary in the zImage format? Feb 27 23:37:49 I got a bbb rev a6 and another rev c. I'm running my FS on a RAMDISK and this the question: Why u boot load the image on rev c faster than rev a6 ? Feb 27 23:39:02 eMMC on Beaglebone Black rev is faster than rev a6a? Feb 27 23:39:10 rev c* Feb 28 02:09:05 ahoy Feb 28 02:10:24 * nerdboy trying to explain to wife why 12monkeys is a stupid show... Feb 28 02:12:38 * nerdboy has overly high expectations since Babylon 5 Feb 28 02:13:11 actually today the yardstick is ToS Feb 28 02:13:26 * nerdboy takes off hat **** ENDING LOGGING AT Sat Feb 28 02:59:59 2015