**** BEGIN LOGGING AT Thu Oct 06 02:59:56 2022 Oct 06 05:24:40 docs! Oct 06 05:24:47 You guys? Way to go! Oct 06 05:41:57 bbl! Oct 06 09:07:24 * mvaittin has the infamous "duck in a thunderstorm" - moment. Oct 06 09:07:28 for 3 days I Oct 06 09:07:39 sorry - message escaped :) Oct 06 09:08:32 for 3 days I've been trying to get my accelerometer driver working on beagle bone black SPI using the upstream v6.0-rc7 kernel. Oct 06 09:09:24 I just put the accel DT node directly in am335x-boneblack.dts. Tried both SPI0 and SPI1. Oct 06 09:10:31 configured spi-D0 as input (fore MISO) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) Oct 06 09:11:33 I can see correct-looking traffic in wires (, CS pulled low, clk, 8 bits register address in MOSI and 8 bit data reply in MISO) Oct 06 09:11:52 but the BBB spi driver always reads 0x0 :/ Oct 06 09:13:20 Any good guesses what I am missing(?) I've used SPI on BBB previously with some temperature-sensor but don't remember if it used 4 or 3 wires. Oct 06 09:38:19 Um... Oct 06 09:38:35 I tried SPI recently too. The location of the file(s) may be located elsewhere. Oct 06 09:38:54 So, one may need a .dts file or config-pin (either/or). Oct 06 09:39:05 But...my spi device was not reading well either. Oct 06 09:39:13 maybe /dev/bone/spi/? Oct 06 09:42:39 I was trying CS1 w/ spidev1.0 but I think there are symlinks to spidev1.0 from /dev/bone/spi for now? Oct 06 09:48:17 set_: thanks :) I don't use spidev - I've done a kernel driver for the accelerometer. It has quite a lot of layers as I used regmap - but I added prints to the spi-omap2-mcspi.c pio_rx/tx just to ensure I don't lose data somewhere on the higher layers. It seems rx is all zeros already in the spi-omap2-mcspi.c Oct 06 09:48:42 and I did try setting the pinconf/mux from the dts Oct 06 09:50:09 pin 85 (PIN85) 3:gpio-96-127 44e10954 00000028 pinctrl-single - looks correct for SPI0 d0 to me. Oct 06 09:50:42 0x28 being receiver enabled, no pull and mode 0 Oct 06 09:51:24 (I guess the clk, MOSI and CS are fine as the data logged from wires look good). Oct 06 09:52:31 also the MISO data looks good, voltage levels being ~3.4V and data being what I expect to be read from the register. I just don't really know why the data in the driver is 0. I must be missing something obvious... Oct 06 09:53:34 driver being the spi-omap2-mcspi.c already Oct 06 09:54:14 (eg, not just the data from the regmap at my driver but already before the regmap layer). Oct 06 10:01:56 mvaittin: check that your pinmux has the clock pin configured as input-enabled Oct 06 10:01:59 i.e. PIN_INPUT Oct 06 10:02:33 hmm actually if that weren't the case you also wouldn't have data out Oct 06 10:03:01 Oh. Oct 06 10:04:13 mvaittin: can you try running my show-pins utility and grep for spi: https://github.com/mvduin/bbb-pin-utils/#show-pins (hopefully it still works for kernel 6.0) Oct 06 10:05:58 and share your DT fragment just in case Oct 06 10:12:45 zmatt: I don't think I have INPUT enabled for spi-clk Oct 06 10:12:55 let me see.. Oct 06 10:13:17 mvaittin: I'm pretty sure you wouldn't have any data out on mosi if you didn't Oct 06 10:13:54 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE0) Oct 06 10:14:06 well that definitely needs to be PIN_INPUT Oct 06 10:14:48 even though it drives the clock pin, it also reads it back via the input receiver to get better timing specs Oct 06 10:14:54 zmatt: hmm. out of the curiosity - why is that? I think master (beagle bone) drivers the clock, right? Well, I'll change this and see what happens - Thanks! Oct 06 10:15:03 zmatt: thanks! Oct 06 10:15:16 * mvaittin tries it out Oct 06 10:15:18 so it's the signal from the input buffer that's actually used to clock the shift register Oct 06 10:16:51 so you shouldn't be able to get address bits on MOSI if sclk is input-disabled, that's the part that confuses me here Oct 06 10:23:31 zmatt: I owe you a beer :) Oct 06 10:23:31 [ 58.069897] Test read ret 0xc8 0x20 0x20 0x0 Oct 06 10:23:59 I got valid data now. Unfortunately I can't help with the MOSI data. Oct 06 10:24:38 I think I saved a screenshot from the saleae capture yesterday - I can recheck or even upload the image :) Oct 06 10:24:56 but I am pretty sure the address was correctly output on MOSI Oct 06 10:25:10 maybe I'm just wrong, maybe it uses the internal clock for MOSI and retimed clock for MISO Oct 06 10:26:40 zmatt: maybe :) But you definitely were right on the clock needing to be input! Oct 06 10:27:32 in general just use PIN_INPUT... there's negligible benefit to using PIN_OUTPUT other than some tiny power savings, and sometimes using PIN_OUTPUT for a seemingly output-only pin breaks things :) Oct 06 10:27:41 PIN_INPUT is always safe Oct 06 10:27:57 zmatt: Thanks for the tip :) Oct 06 10:28:01 it doesn't help that the names are just terrible Oct 06 10:28:26 since it's not input vs output, it's input-enabled vs input-disabled without having any impact on the output driver Oct 06 10:28:32 Well - pinmuxes are hard... Oct 06 10:30:15 zmatt: yes - the reference manual says 'receiver enable' which is better. But the typical GPIO programming model just uses of terms input/output Oct 06 10:30:34 this has nothing to do with the gpio programming model though :) Oct 06 10:30:45 Still, it never came to my mind that the clk driven by BBB should also be received by BBB Oct 06 10:30:46 (nor with the gpio controllers for that matter) Oct 06 10:31:30 well, pin c0nf/-control is probably influenced by people used to work with GPIOs Oct 06 10:31:54 s/c0nf/conf Oct 06 10:33:40 but ... BIG thanks :) It seems my driver works also on SPI - so next week I can proceed sending v2 to upstream - without RFC tag :) Oct 06 10:34:55 now I'll back my backpack and head to the wilderness :] - offline till the Monday - but matrix should log messages in case you guys want to ping me. Enjoy the weekend! Oct 06 10:40:32 all is well again! Oct 07 00:39:47 @zmatt: Thank you for making the subartic pins diagram. Oct 07 00:39:59 You saved me 500 hrs. of work. Oct 07 00:41:42 It is all about deducing time into nano amounts! **** ENDING LOGGING AT Fri Oct 07 02:59:56 2022