**** BEGIN LOGGING AT Mon Feb 21 23:59:56 2005 Feb 22 00:57:16 ~lart fc3 Feb 22 00:57:16 * qbot --purges fc3 Feb 22 01:16:15 ~lart fc3 Feb 22 01:16:15 * qbot whips out a sword and chops fc3 in half Feb 22 01:16:20 heh **** ENDING LOGGING AT Tue Feb 22 02:08:24 2005 **** BEGIN LOGGING AT Tue Feb 22 02:08:44 2005 Feb 22 11:36:20 ~seen [g2] Feb 22 11:36:20 [g2] <~g2@g2.nslu2-linux> was last seen on IRC in channel #openjtag, 1d 3h 16m 16s ago, saying: 'I think the jtag is just the connection mechanism like serial or ethernet'. Feb 22 11:53:35 beewoolie: hey Feb 22 11:53:48 prpplague: yo Feb 22 11:53:54 beewoolie: found part of the problem with apex Feb 22 11:54:12 beewoolie: burst length was set incorrectly for 16bit databus Feb 22 11:54:40 beewoolie: need to 0x23 << 12 instead of 0x22<<12 Feb 22 11:55:20 isn't that in the initialize_bootstrap? Feb 22 11:56:20 beewoolie: yea Feb 22 11:56:54 SDRAM_CHIP_MODE Feb 22 11:56:57 prpplague: that is something that is supposed to be modified/replaced for each target. Feb 22 11:57:11 beewoolie: agreed Feb 22 11:57:13 While you can simply add ifdefs, it is generally better to replace the file. Feb 22 11:57:17 beewoolie: just over looked it somehow Feb 22 11:57:42 Fair enough. You had to make the burst length 4 instead of 8? Feb 22 11:57:47 beewoolie: yea Feb 22 11:58:01 Does that mean that the stm copy functions now works? Feb 22 11:58:13 beewoolie: yea Feb 22 11:59:15 prpplague: nice. Feb 22 11:59:19 beewoolie: the original example i got from lineo was obfuscated imho Feb 22 11:59:30 prpplague: original example of what? Feb 22 11:59:38 beewoolie: they set the value at 0x22 and then later added 1 to it Feb 22 11:59:47 beewoolie: example sdram init code Feb 22 12:00:07 prpplague: I have little good to say about the Lineo work. Feb 22 12:00:22 beewoolie: yea, me either Feb 22 12:01:35 prpplague: BTW, I released a 1.1.0 version. The fat/cf driver reliably reads CF cards and can be used to boot the system Feb 22 12:01:56 prpplague: I bumped the rev because I made an official release to Sharp. Feb 22 12:02:01 beewoolie: cool, hehe, when ya gonna do mmc? Feb 22 12:02:06 beewoolie: lovely Feb 22 12:02:15 prpplague: when you send me a board Feb 22 12:02:28 beewoolie: hehe, whats wrong with one of yours? Feb 22 12:02:35 prpplague: I don't have an mmc slot. Feb 22 12:02:58 beewoolie: they have spi though, just connect up a mmc socket Feb 22 12:03:31 prpplague: The official policy is that I don't write drivers for things I cannot test. If I had the hardware, I'd write the driver. Feb 22 12:03:57 prpplague: The LPD SDK board doesn't have an MMC slot. No slot, no driver. Feb 22 12:14:36 beewoolie-away: hmm, hehe, i could send you an interface for the lpd Feb 22 12:14:56 beewoolie-away: i had already planned to do the spi/mmc anyway myself Feb 22 12:15:05 beewoolie-away: just had to knock out this sdram iss Feb 22 12:15:07 issue Feb 22 14:05:37 <[g2]> ka6sox, ping Feb 22 14:06:01 [g2], pong Feb 22 14:06:58 <[g2]> ka6sox-office, what kind of memory is on the FatSlug ? Feb 22 14:07:09 4X8M16 Feb 22 14:07:15 Funny you shoudl ask.... Feb 22 14:07:34 they should be MT48LC8M16A2 Feb 22 14:07:51 thats right. Feb 22 14:08:09 dyoung: Why is it funny to ask? Are we just adding two extra chips? Feb 22 14:08:17 ...of the same type? Feb 22 14:08:31 No, I was sorting through my memory pile 2 minujtes ago. Feb 22 14:08:33 they are "compatible" but not the same Feb 22 14:08:45 not identical Feb 22 14:08:57 since the originals are ISI and the new ones are Micron. Feb 22 14:09:00 As long as the pinout and addressing are identical. Feb 22 14:09:07 beewoolie-away, it is. Feb 22 14:09:09 Sam CAS speed? Feb 22 14:09:15 s/Sam/same/ Feb 22 14:09:15 hmmm... Feb 22 14:09:27 sb Feb 22 14:09:45 <[g2]> or we just run at the slowest CAS speed Feb 22 14:10:15 [g2], you have a fatslug in hand? Feb 22 14:10:22 on the way to him Feb 22 14:10:26 * dyoung drool Feb 22 14:10:38 dyoung: after I get this board done I want your slug Feb 22 14:10:39 Looks like [g2] is gonna beat me to making fatslug work. Feb 22 14:11:16 8M16A2-75 Feb 22 14:11:29 that is the model of what is the "upper" row Feb 22 14:12:52 * beewoolie-away fetches the datasheets Feb 22 14:13:23 <[g2]> dyoung, not yet but I'm expecting it very soon :) Feb 22 14:13:41 <[g2]> ka6sox-office, do you know where it's at ? Feb 22 14:14:01 no..I"ve been swamped (literally) and need to follow up. Feb 22 14:15:12 <[g2]> ka6sox, it was sent last week though correct ? Feb 22 14:15:57 dyoung: those are the ones we are using with our project Feb 22 14:16:40 I have ka6sox reworking a bunch off DIMM's for oru fatslug project(s). Feb 22 14:51:12 OK boyz. I put up APEX 1.1.1 which has a streamlined SDRAM configuration. All you (should) have to do to use your fatslugs is set the configuration option CONFIG_SDRAM_BANK1=y. Feb 22 14:51:54 cool, will it autodetect the size of the memory? Feb 22 14:52:28 It may in the future. For now, it only allows one or two banks of 32MiB. Feb 22 14:52:43 good enough for testing. Feb 22 14:52:43 [g2] and I have discussed ways to allow it to detect the config. Feb 22 14:53:11 It should definitely be possible to size a single bank. I am not sure if I can detect the presence of one or two banks of memory. Feb 22 14:53:24 ka6sox-office: That's the idea. Feb 22 14:53:54 Cool. Feb 22 14:54:01 Thanks Beewoolie, youre the man! Feb 22 14:54:09 It has been my experience that attempting to read from a non-existent bank will hang the system. what I don't know is whether or not there is a way to detect the fault. Feb 22 14:54:12 dyoung: np. Feb 22 14:55:43 * prpplague heads home Feb 22 14:55:49 prpplague: later Feb 22 14:55:56 beewoolie-away: later d00d Feb 22 14:55:58 hehe Feb 22 14:58:18 so if we ever move to the 16M16 part; is it as easy as changing the CONFIG_SDRAM_BANK_LENGTH to 64*1024*1024 ? Feb 22 14:58:28 and adjusting the number of banks accordingly? Feb 22 15:01:15 dyoung: That is the idea. Feb 22 15:01:38 * dyoung drool Feb 22 15:01:57 dyoung: I haven't looked closely at the options. It depends on whether or not there is one and only one way to put 32MiB in a single bank. I believe this is so. Feb 22 15:02:17 "but where, oh where" will I find 16M16's??? Feb 22 15:02:25 * ka6sox-office ducks Feb 22 15:02:34 * dyoung grin Feb 22 15:02:40 * beewoolie-away snorts Feb 22 15:02:54 * beewoolie-away shells a peanut Feb 22 15:03:36 The part I'd like to change is I'd like to allow the SDRAM init to discover the size of the chips in a bank. This should be easy since we can detect aliasing. Feb 22 15:04:03 Moreover, it may not be necessary since the kernel *can* work with NUMA. Feb 22 18:15:29 beewoolie: boo Feb 22 18:15:38 prpplague: yo Feb 22 18:16:06 beewoolie: how goes it? Feb 22 18:16:20 prpplague: Looking into ext2 read for APEX Feb 22 18:16:25 lovely Feb 22 18:16:32 prpplague: interestingly enough, there is no ext2 code in uboot Feb 22 18:16:41 * prpplague has been hacking spi all afternoon Feb 22 18:17:30 prpplague: How's that going? Feb 22 18:32:23 good Feb 22 18:32:29 got the spi init Feb 22 18:32:33 added the i Feb 22 18:32:34 to Feb 22 18:32:37 argh Feb 22 18:32:41 beewoolie: i/o Feb 22 18:32:50 more to follow tomorrow Feb 22 18:33:05 beewoolie: debugging wore me out Feb 22 18:33:17 prpplague: Really? what's the hard part? Feb 22 18:33:42 beewoolie: sorry on the sdram is what wore me out Feb 22 18:33:46 beewoolie: the spi is easy Feb 22 18:34:21 ah. that should be the hardest part. Feb 22 18:36:39 yea Feb 22 18:36:58 been a good learning experience Feb 22 18:37:09 know more about sdram than i ever thought i would Feb 22 18:37:40 beewoolie: btw, hehe, i need your address, boss is gonna send you a jtag dongle Feb 22 18:38:04 prpplague: Really? To what do I owe the honor? Feb 22 18:38:14 beewoolie: hehe, your crappy pics Feb 22 18:38:15 hehe Feb 22 18:38:24 prpplague: Yer kidding. Feb 22 18:38:28 hehe Feb 22 18:38:36 beewoolie: he's a double E Feb 22 18:38:47 I thought the pictures were pretty good. The layout might be funky. Feb 22 18:38:47 beewoolie: i have 3 on my desk to send out Feb 22 18:38:53 beewoolie: hehe Feb 22 18:38:58 prpplague: sweet. I wont' say no. Feb 22 18:39:03 beewoolie: hehe Feb 22 18:39:05 I think You've sent me email... Feb 22 18:39:16 ye Feb 22 18:39:17 yea Feb 22 18:39:28 amltd? Feb 22 18:39:40 yea Feb 22 18:40:06 prpplague: sent. Feb 22 18:40:10 thx. Feb 22 18:40:34 ext2 looks like it might be a bit of work. Feb 22 18:40:53 fat was easy, though it isn't really done. Feb 22 20:39:29 can you steal code from grub or lilo for ext2 ? Feb 22 20:40:09 jacques: I am looking at the grub code. Feb 22 20:40:17 ah Feb 22 20:40:26 Not to worry. Reading isn't really that hard. Feb 22 21:47:46 hiya Feb 22 21:48:13 hey Feb 22 21:48:15 the goal recently is to piggyback chips Feb 22 21:48:35 yeah, i looked at the leads.. those j leads are hard to bend down like that and make a reliable solder... Feb 22 21:48:46 I've recently done it. Feb 22 21:49:02 it was a PITA Feb 22 21:49:07 i've done it in the past but it's a pain. i was looking at the data sheets Feb 22 21:49:45 and some folks mention using the extra chip select on the resistor pack but the 32M16 looks like it'll solder on the pads of the 8X16 no problem...not sure about config though but it looks like physically it'll fit Feb 22 21:50:12 that shouldn't be a problem. Feb 22 21:50:18 i think the extra address line is hooked up to the pad (A13 or A12- can't remember) Feb 22 21:50:42 you might have to move the PCI window in order to get it to work. Feb 22 21:51:07 i can initially config for 64MB w/o moving the PCI window, right? Feb 22 21:51:17 yes Feb 22 21:51:32 so how do i go about building code for a fatslug? :) Feb 22 21:52:08 contact dyoung, jacques, or [g2] about what they have already done. Feb 22 21:52:12 might save you some steps. Feb 22 21:52:51 or Tiersten..they have all played with the code. Feb 22 21:53:24 haven't seen them tonight Feb 22 21:53:34 they can be found around here as well Feb 22 21:54:02 Beewoolie has been working on a replacement bootloader called APEX. Feb 22 21:54:18 I think its alpha but they are making great strides testing. Feb 22 21:54:26 ka6sox-office: Is working. Evening. Feb 22 21:54:34 there he is... Feb 22 21:54:48 so that is another bootloader to test. Feb 22 21:54:57 ok Feb 22 21:55:14 contact beewoolie for the code location. Feb 22 21:55:18 GE beewoolie Feb 22 21:55:33 hi beewoolie... Feb 22 21:56:15 Hi. If you want to try APEX, there are links to it on the nslu2 wiki. Or try wiki.buici.com. The page is called ApexBootloader. Feb 22 21:56:40 ok..i just went to the wiki Feb 22 21:56:53 The only important piece missing is init code for the NPE. We cannot use ethernet from Linux until we load the microcode. Feb 22 21:57:16 I can't go too wild w/ the slug since i have to use it as the gallery server for baby pictures. :) wife would kill me Feb 22 21:57:42 At this point, there isn't a reason to do much with APEX unless you want to test it. You can run it from SDRAM. Feb 22 21:58:55 the work dyoung, et al have been doing, that's seperate from APEX. is that available? Feb 22 21:59:38 I'm sure it is...I'll ask them to put the code in CVS for the openjtag project. Feb 22 21:59:50 thx... Feb 22 22:00:08 since we are doing bootloaders and jtag things here. Feb 22 22:00:17 samms71, played much with Jtag? Feb 22 22:00:42 yeah, in the course of debugging boards, etc...handy when the os is dead... Feb 22 22:01:26 we are working on a inexpensive fast jtag board/software combo. Feb 22 22:02:37 to add jtag to other systems or as a standalone system? Feb 22 22:04:53 to program embedded bootloaders and such faster. Feb 22 22:05:05 current wigglers take about 40 minutes to load redboot Feb 22 22:05:17 so we want to cut that down to 4mins or less. Feb 22 22:05:32 sounds like a fpga/cpld job...maybe a small micro but that might be too slow. Feb 22 22:05:47 brb..gotta change baby diaper.. Feb 22 22:05:51 k Feb 22 22:12:31 k Feb 22 22:12:37 sorry..baby wet her shirt... Feb 22 22:12:44 life changes alot... :) Feb 22 22:14:56 anyway, i was just checking out a lattice semi cpld..they had a software package on a winxp running over jtag changing registers inside of the fpga..kinda cool...from talking to the fae you can use the jtag port after config or instantiate your own. wonder if you could do a state machine in a fpga w/ attached memory to do the reflash? not sure i'd trust it 100% since if the power went out....:( Feb 22 22:16:58 we did something similar to this w/ a hc16 reprogramming a fpga on a board..worked nice..the state machine was in the microcontroller..it took about 8min to reprogram the fpga...probably could do it alot faster in hardware. Feb 22 22:23:07 samms71: That's exactly what I want to be able to do. Feb 22 22:23:43 xilinx publishes a app note w/ the info on how to use a microcontroller to reprogram the eeproms/fpga's. they even included the code... Feb 22 22:24:07 I write VHDL for Xilinx cpld's and fpga's Feb 22 22:24:25 That's a little outside my area of knowledge. Feb 22 22:24:26 hehe...i read vhdl but only write verilog... ;) Feb 22 22:24:41 I'm the opposite. Feb 22 22:24:49 My nderstanding is that we can completely control a device that grants JTAG BSDL. Feb 22 22:24:52 read verilog but write vhdl Feb 22 22:26:12 beewoolie..that's the theory but it seems that every vendor has a slight twist they add...they conform but you don't get all of their special features... Feb 22 22:26:23 yep. Feb 22 22:26:32 but for reprogramming, etc...it shoudl be ok... Feb 22 22:26:42 either that or you have to buy the "special" toolchains Feb 22 22:26:54 As it is designed for test, there is incentive for them to make it available. That doesn't mean they publish everything. Feb 22 22:27:28 i checked out the openjtag web site...it mentions using a spartan or a microcontroller...has anyone tried either one to see how fast? Feb 22 22:27:44 yeah, my xilinx cable cost $400..it's a buffer chip off of the parallel port..sheesh. Feb 22 22:28:12 that is why we want to build a "cable" Feb 22 22:28:19 around $40 or so. Feb 22 22:28:51 Ah, the price has come down. :-) Feb 22 22:29:21 hehe Feb 22 22:30:14 well...in quantity :) Feb 22 22:30:20 so a usb to serial - possible too slow - i've seen a usb to 8051 cpu interface chip..that would work well to control a uC/fpga Feb 22 22:30:40 we looked at that too...the dev system is $500 Feb 22 22:30:47 ka6sox: Have you shared with samms71 the design? Feb 22 22:31:18 hmm..what's their dev system? man the business to get into is bulding these "dev" systems for outrageous prices.. Feb 22 22:31:21 so we were looking at a FTDI 2232 with a CPLD to reconfigure the pins depending on what connector. Feb 22 22:31:57 I think we're expecting about 4MHz top-end JTAG clock. Feb 22 22:33:05 5.6mhz is what I'm after Feb 22 22:33:13 is 4MHz fast enough? Feb 22 22:33:39 the current ones are about 500khz Feb 22 22:33:46 Fair enough. I thought that we were limited by half of the USB 1.1 frequency less some. 1/2 12MHz? Feb 22 22:34:08 The BDI runs at 8MHz. Feb 22 22:34:31 could you run two usb channels? a little more complicated in the cpld but faster.. Feb 22 22:34:38 cost higher too i guess Feb 22 22:34:43 1/2 the 12mhz - overhead Feb 22 22:35:05 samms71 I was wondering that too. Feb 22 22:35:25 Two channels to get what? Feb 22 22:35:42 maybe a data channel and a command/control channel...software on pc wouldn't get too complicated... Feb 22 22:36:05 yes...we were thinking along the same lines Feb 22 22:36:13 I'm not sure that's where the complexity lies. Isn't the bottleneck the JTAG clock? Feb 22 22:36:14 beewoolie..two usb channels gives you 2x4MHz or Feb 22 22:36:41 depending on the device, can't the clock run faster than 4MHz... Feb 22 22:36:49 samms71: I get that, but we still can only run the JTAG clock at a limit imposed by the USB chip we've chosen. Feb 22 22:37:00 the CPLD can do a PLL to get faster data rates Feb 22 22:37:06 If we put a uController on the dongle we can do anything. Feb 22 22:37:17 gotta be REAL fast Feb 22 22:37:19 ka6sox: Does it have a large enough memory ? Feb 22 22:37:28 the CPLD? Feb 22 22:37:31 brb...gotta kick dogs...barking Feb 22 22:37:33 All we need is the length of the scan chain. Feb 22 22:37:48 the Host will take care of that. Feb 22 22:37:49 And I think we only need one. Feb 22 22:37:55 we have all the proc power we need Feb 22 22:38:08 the USB channel is setup to push bits. Feb 22 22:38:26 It wouldn't be hard to use a double channel to transmit the data twice as fast. Feb 22 22:38:52 k Feb 22 22:39:23 so you have a board w/ two usb connectors...two ft2232 chips feeding one cpld/uC that generates the jtag chain to your target.... Feb 22 22:39:38 well... Feb 22 22:39:53 checkout the FTDI 2232 chip. Feb 22 22:39:58 I dunno. I think it would be better to get a USB2.0 chip and synthesize the JTAG signals another way. Feb 22 22:40:12 k...reading pdf's Feb 22 22:45:18 at a quick glance, the ftdi 2232 doesn't look like the best chip for a two usb solution... Feb 22 22:45:54 it isn't Feb 22 22:46:08 but 5.6mhz to start with isn't a slouch Feb 22 22:46:18 agreed. Feb 22 22:46:47 need a chip that's like a hub controller only in reverse. Feb 22 22:47:09 there are USB->Serial adapters that already use it but they are limited by the rs232 devices attached Feb 22 22:49:30 how about this chip: http://www.semiconductors.com/cgi-bin/pldb/pip/isp1581 Feb 22 22:51:27 interesting Feb 22 22:51:47 i love it when data sheets say DMA...just makes me think racing stripes. Feb 22 22:54:45 hell this thing is fast enough, you just need a parallel to serial shifter on the board and you can send the jtag commands straight through..just not sure how you read the data back...still need a cpld/fpga or help you out Feb 22 22:55:23 checkout http://www.beyondlogic.org/usb/usbhard2.htm for more info on dev systems.. Feb 22 22:55:35 yes I've seen some of those. Feb 22 23:00:12 they are relatively cheap for a dev system... Feb 22 23:00:26 the certianly are. Feb 22 23:01:50 night all....thx for the info..i'll be back... Feb 22 23:34:35 night. Feb 22 23:34:42 nite **** ENDING LOGGING AT Tue Feb 22 23:59:56 2005