**** BEGIN LOGGING AT Fri Mar 18 23:59:56 2005
Mar 19 12:56:21 <beewoolie-away> Any of you folks familiar with the openwince jtag error: chain.c(110) Part 0 without active instruction: 
Mar 19 12:56:24 <beewoolie-away> chain.c(110) Part 0 without active instruction
Mar 19 12:56:59 <dyoung> I've never see that one before.
Mar 19 12:57:17 <dyoung> sounds like the one I'm getting with the Xilinx tool
Mar 19 12:57:34 <beewoolie-away> Yeah, I've seen others with the error on one of those parts.
Mar 19 12:58:09 <beewoolie-away> dyoung: do you know where we stand with the openjtag hw?  I haven't seen any traffic on it in a while.
Mar 19 13:00:23 <beewoolie-away> I think it means that the BSDL data has not been properly translated.
Mar 19 13:00:32 <beewoolie-away> ...the error
Mar 19 13:12:41 <dyoung> Hmm, looks like it, or its wrong for the part, or the cable is doing something funky.
Mar 19 13:13:06 <dyoung> I dunno the status.  The board might be laid out but I'm not sure.
Mar 19 13:23:19 <beewoolie-away> I don't think it's getting as far as checking the manufacturer.
Mar 19 13:23:32 <beewoolie-away> Also, I've read other messages and it doesn't seem to be the cable because other SW works fine.
Mar 19 13:27:14 <dyoung> Hmm
Mar 19 13:27:34 <dyoung> I havnt dove into the bowels of that code yet.
Mar 19 13:27:40 <beewoolie-away> I mean, other people have  used different sw with the same cable and target.
Mar 19 13:27:57 <beewoolie-away> Me neither.  I'm unimpressed with the fact that they don't read bsdl files directly.
Mar 19 13:28:32 <beewoolie-away> Seems like an obvious design fauxpaw
Mar 19 13:29:57 <beewoolie-away> I was trying to interface my find-and-dandy JTAG board to another device to determine whether or not the board works.
Mar 19 13:30:27 <beewoolie-away> Negative result is, unfortunately, ambiguous.
**** ENDING LOGGING AT Sat Mar 19 23:59:56 2005