**** BEGIN LOGGING AT Mon Jun 27 23:59:56 2005
**** BEGIN LOGGING AT Tue Jun 28 10:26:28 2005
Jun 28 11:11:00 <ep1220> [g2] am here now
Jun 28 11:11:19 <[g2]> ep1220, hey !
Jun 28 11:11:24 <ep1220> hey
Jun 28 11:11:41 <[g2]> The NSLU2 appears to be running at 133 MIPs
Jun 28 11:11:58 <ep1220> shouldn#t it be 266 ?
Jun 28 11:12:07 <[g2]> it should be but doesn't appear to be
Jun 28 11:12:19 <[g2]> this has been brought up before
Jun 28 11:12:40 <[g2]> [g2]> Microseconds for one run through Dhrystone:     5.8
Jun 28 11:12:40 <[g2]> <[g2]> Dhrystones per Second:                        172176.3
Jun 28 11:12:40 <[g2]> <[g2]> VAX MIPS rating =     97.994
Jun 28 11:12:56 <[g2]> that's on the NSLU2 which shows 133 BogoMIPS
Jun 28 11:13:12 <[g2]> Microseconds for one run through Dhrystone:     2.9
Jun 28 11:13:12 <[g2]> <[g2]> Dhrystones per Second:                        350140.1
Jun 28 11:13:12 <[g2]> <[g2]> VAX MIPS rating =    199.283
Jun 28 11:13:41 <[g2]> That's on my avila board which is an IXP422 @ 266 and shows 266 BogoMIPS
Jun 28 11:13:54 <jacques> [g2], wallclock time on the avila should be about 10 seconds
Jun 28 11:14:19 * [g2] plugs the box and serial cable back in :)
Jun 28 11:14:36 <jacques> :-)
Jun 28 11:14:55 <jacques> oh, and make sure your wallclock isn't running at double speed
Jun 28 11:15:05 <[g2]> nod :)
Jun 28 11:15:06 <jacques> or half speed
Jun 28 11:15:45 <ep1220> Do the Avila and NSLU2 use same number of wait-states on RAM ?
Jun 28 11:16:13 <jacques> does that even matter for dhrystone?
Jun 28 11:16:33 <ep1220> Do not know
Jun 28 11:18:57 <[g2]> ok 14 seconds wall clock
Jun 28 11:19:13 <[g2]> real    0m 14.83s
Jun 28 11:19:13 <[g2]> user    0m 14.28s
Jun 28 11:20:27 <jacques> [g2], that's for 5,000,000 iterations?
Jun 28 11:21:03 <[g2]> Dhrystones per Second:                        175192.7
Jun 28 11:21:03 <[g2]> VAX MIPS rating =     99.711
Jun 28 11:21:03 <[g2]> real    0m 28.55s
Jun 28 11:21:10 <[g2]> avila versus slug
Jun 28 11:21:36 <[g2]> Dhrystones per Second:                        175192.7
Jun 28 11:21:36 <[g2]> VAX MIPS rating =     99.711
Jun 28 11:21:36 <[g2]> real    0m 28.55s
Jun 28 11:21:49 <jacques> I get almost exactly 30 seconds on a slug
Jun 28 11:22:05 <[g2]> echo '5000000' | time ./dhry2
Jun 28 11:22:16 <[g2]> well this is a fatslug :)
Jun 28 11:23:19 <jacques> well, according to pb, using the device's clock makes the results suspect which is why I kept saying wallclock time
Jun 28 11:23:48 <[g2]> VAX MIPS rating =    199.283
Jun 28 11:23:56 <[g2]> NOD that's a good thing to check
Jun 28 11:24:07 <[g2]> but in this case wall clock == onboard clock
Jun 28 11:24:38 <jacques> anyway, I think we've shown that the avila is twice as fast at dhrystone
Jun 28 11:24:58 <[g2]> nod
Jun 28 11:25:02 <[g2]> wall time
Jun 28 11:25:25 <jacques> twice as fast
Jun 28 11:25:37 <jacques> it does 2x as many iterations in the same amount of time
Jun 28 11:25:45 <[g2]> I was wonder if ep1220 or Tiersten had a scope and could output a clock to a GPIO or measure the PCI clock
Jun 28 11:25:57 <[g2]> right
Jun 28 11:26:15 <[g2]> I'll run 10,000,000 iterations in 28 secs
Jun 28 11:26:30 <ep1220> [g2] I do have a scope (200MHz BW) and a 200mHz LA
Jun 28 11:26:31 <jacques> man it sure would suck if they had to lower the speed because of some pci/usb controller instability
Jun 28 11:26:47 * [g2] hugs ep1220 
Jun 28 11:26:51 <ep1220> Hehe, the LA is 200MHz
Jun 28 11:27:03 <[g2]> lucky bastard! :)
Jun 28 11:27:31 <jacques> but it sure would be sweet if we can suddenly get full 100TX TCP saturation and 20MB/s USB
Jun 28 11:27:34 <[g2]> but I've got a board the runs faster :)
Jun 28 11:28:01 <ep1220> [g2]: could it be there are IRQs running during the benchmark ?
Jun 28 11:28:03 <[g2]> jacques, the current using does 100TX TCP saturation
Jun 28 11:28:48 <[g2]> s/using/unit/
Jun 28 11:31:29 <jacques> ok fine
Jun 28 11:31:36 <[g2]> thttpd will saturate the line at 100Mbs for < 30MB files
Jun 28 11:31:56 <jacques> hmm
Jun 28 11:32:07 <jacques> doesn't that use UDP packets?
Jun 28 11:32:23 <[g2]> http
Jun 28 11:32:31 <[g2]> TCP port 80 thingy
Jun 28 11:32:38 <jacques> oh, ok thought you said tftpd
Jun 28 11:32:47 <[g2]> now thttpd
Jun 28 11:32:53 <[g2]> now
Jun 28 11:32:55 <[g2]> no
Jun 28 11:33:09 * [g2] takes remedial typing 
Jun 28 11:38:36 <[g2]> ep1220, they are pretty much running the same sw
Jun 28 11:39:07 <[g2]> there is not RTC on the avila
Jun 28 11:39:13 <[g2]> no
Jun 28 11:39:23 <ep1220> [g2]: Do You run the benchmark directly from the bootloader ?
Jun 28 11:39:30 <ep1220> Or under an OS ?
Jun 28 11:39:36 <[g2]> from Linux
Jun 28 11:39:44 <[g2]> statically linked
Jun 28 11:40:01 <[g2]> I can reboot the slug and run it from flash like the avila
Jun 28 11:40:45 <ep1220> so the avila has no Linux during benchmark ?
Jun 28 11:41:03 <[g2]> they both are run from linux
Jun 28 11:41:17 <[g2]> the nslu was from external hd with swap
Jun 28 11:41:41 <[g2]> now it's from jffs2 like the avila
Jun 28 11:43:21 <[g2]> from jffs2
Jun 28 11:43:24 <[g2]> VAX MIPS rating =     99.572
Jun 28 11:43:25 <[g2]> real    0m 29.33s
Jun 28 11:43:29 <[g2]> same as disk
Jun 28 11:45:35 <ep1220> The devManual says the UART clock is derived from the system clock
Jun 28 11:46:00 <ep1220> So if the same divisor gives same baud-rate the core-clocks must be identical
Jun 28 11:48:34 <[g2]> that makes sense, but something is accounting for the difference
Jun 28 11:49:39 <ep1220> can you run the benchmark without linux under it ?
Jun 28 11:49:57 <[g2]> no it's linux program
Jun 28 11:51:16 <ep1220> CMIIAW, but dryhstone should not use OS calls (?)
Jun 28 11:51:54 <[g2]> CMIIAW ?
Jun 28 11:52:06 <ep1220> Correct me if I am wrong
Jun 28 11:52:52 <[g2]> it'd imagine it gets in a tight looop
Jun 28 11:53:48 * VoodooZ_Work wipes the drool off his keyboard  after imagining being able to overclock his slug to get double the performance!
Jun 28 11:55:39 <jacques> dhrystone uses the libc string functions heavily
Jun 28 11:56:14 <ep1220> But these should not call into Linux (?)
Jun 28 11:56:21 <jacques> you mean the kernel ?
Jun 28 11:56:24 <ep1220> yes
Jun 28 11:56:58 <jacques> well it has to access the console to display the results
Jun 28 11:57:13 <jacques> ep1220, but what is your point?
Jun 28 11:57:16 <beewoolie-afk> Hey folks
Jun 28 11:57:22 <[g2]> beewoolie-afk, hey!
Jun 28 11:57:30 <jacques> are you saying that because the dhrystone benchmark runs under an OS it's somehow not valid ?
Jun 28 11:57:47 <[g2]> beewoolie-afk, how's the MAN!
Jun 28 11:57:59 <ep1220> jacques: No i mean maybe the OS (or a driver) steals some time
Jun 28 11:58:16 <ep1220> e. an IRQ could invalidate the cache
Jun 28 12:00:48 <jacques> ho wlikely is it that it would cause the benchmark to be almost exactly 1/2 ?
Jun 28 12:01:14 <jacques> and what about the kernel computing bogomips? I don't think the OS would be stealing time at that point
Jun 28 12:01:42 <ep1220> Do not know how bogomips are implemented.
Jun 28 12:04:31 <ep1220> the Wiki says: GPIO14 and 15 are (should eb) both 33Mhz clocks
Jun 28 12:05:01 <ep1220> maybe i find an "access point" at one of these nets.
Jun 28 12:05:06 <jacques> :-)
Jun 28 12:06:59 <[g2]> ep1220, that'd be great
Jun 28 12:07:23 <[g2]> you know about the detailed picturres on the wiki right ?
Jun 28 12:07:31 <beewoolie-afk> Bogomips are called bogo for a reason.
Jun 28 12:08:18 <prpplague> beewoolie-afk: hey
Jun 28 12:08:21 <prpplague> beewoolie-afk: whats cookin
Jun 28 12:08:50 <beewoolie-afk> prpplague: been on the Cisco router & IPv6 research train.
Jun 28 12:08:52 <jacques> man if I hear that one more time 
Jun 28 12:09:01 <jacques> about bogomips
Jun 28 12:09:33 <beewoolie-afk> ;-)
Jun 28 12:09:45 <ep1220> g2: now I now.
Jun 28 12:09:46 <[g2]> beewoolie-afk, we've run a drystone benchmark on the avila and nslu2 and it comes out 2x on the avila
Jun 28 12:09:56 <[g2]> now I know ?
Jun 28 12:10:12 <beewoolie-afk> That makes sense.
Jun 28 12:11:03 <[g2]> beewoolie-afk, they are supposed to be the same 266
Jun 28 12:11:55 <beewoolie-afk> There are lots of ways that the systems could be different.  Has anyone looked at the clock pin?
Jun 28 12:12:33 <[g2]> beewoolie-afk, that's what we're asking ep1220  to do :)
Jun 28 12:12:55 <[g2]> If you've got an analyzer handy pls feel empowerered :)
Jun 28 12:12:57 <beewoolie-afk> Heck, I've got a scope.
Jun 28 12:13:21 <beewoolie-afk> I didn't want to do anything today, anyway...
Jun 28 12:14:23 <jacques> yeah some hard numbers from scopes (as long as they aren't running at 2x normal speed) would be appreciated
Jun 28 12:14:42 * beewoolie-afk moves to the upstairs laboratory
Jun 28 12:19:49 <jacques> morning dyoung, it's mad scientist day
Jun 28 12:20:53 <dyoung> it is?
Jun 28 12:21:12 <dyoung> like mad scientists are screwing around with my internet connection?
Jun 28 12:22:40 <jacques> are they?
Jun 28 12:22:44 <[g2]> hey dyoung 
Jun 28 12:22:57 <jacques> I was referring to mad slug experiments in the laboratory
Jun 28 12:23:24 <dyoung> Oh.  I googled it.
Jun 28 12:23:36 <dyoung> Theres actually a "talk like a mad scientists day"
Jun 28 12:23:37 <jacques> we're trying to find out if it's aliiive or only ½ alive
Jun 28 12:25:23 <dyoung> Ah, Ok read the logs.
Jun 28 12:25:29 <dyoung> well skimmed them.
Jun 28 12:25:50 <dyoung> I have a scope in my Secret Laborabory (tm) too. :-)
Jun 28 12:27:03 <dyoung> now that i've googled it, I cant want for 7/27, Talk Like A Mad Scientist Day.
Jun 28 12:27:25 <[g2]> jacques, is always early on stuff ;)
Jun 28 12:28:38 <jacques> damn I will need to brush up on my mad scientist lingo for that
Jun 28 12:29:31 <dyoung> I cant think of any catchphrases.
Jun 28 12:29:39 * bw-slugstien polishes the chest spreader
Jun 28 12:29:41 <dyoung> other than the one jacques just said.
Jun 28 12:29:51 <jacques> yeah, that's kinda the classic
Jun 28 12:30:18 <jacques> and I guess one would use the word "laboratory" a lot
Jun 28 12:30:19 <dyoung> Looks like the Count here is ready to Plug In The Electrodes.
Jun 28 12:31:04 * bw-slugstien fires up the static electricity generator so that his hair stands on end
Jun 28 12:31:19 <jacques> and "1.21 gigawatts!"
Jun 28 12:31:36 <dyoung> Do mad scientists say "Curses!"
Jun 28 12:31:37 <dyoung> ?
Jun 28 12:31:37 <bw-slugstien> bwahhahahha
Jun 28 12:32:24 <dyoung> Being mad implies that you have been shunned by "normal" scientists.  "They all laughed at my theories on why the slug runs at half speed!  I'll show those fools!"
Jun 28 12:32:30 <jacques> ooh and get one of those jacob's ladder thingies
Jun 28 12:32:42 <jacques> dyoung, yes that's a great one
Jun 28 12:33:37 * bw-slugstien lights the bunsen burner and sets the Erlenmeyer flash on the pedestal...
Jun 28 12:33:46 <jacques> was the martian on bugs bunny a mad scientist? 
Jun 28 12:33:53 <jacques> he kept talking about his space modulator
Jun 28 12:34:01 <dyoung> Did he have a european accent?
Jun 28 12:34:17 <jacques> hmm no he just sounded like a cartoon
Jun 28 12:35:18 <dyoung> I cant remember if all mad scientists on the TV have had european accents.
Jun 28 12:35:37 <jacques> "If my calculations are correct, when this baby hits eighty-eight miles per hour... you're gonna see some serious shit."
Jun 28 12:35:53 <bw-slugstien> bwahahahahaha
Jun 28 12:36:36 <dyoung> Ok fair enough.
Jun 28 12:36:49 <dyoung> I forgot about him.
Jun 28 12:36:50 <dyoung> heh
Jun 28 12:37:07 <dyoung> Flux Capacitor.
Jun 28 12:38:58 * bw-slugstien puts a tea bag in the flask.
Jun 28 12:41:24 <bw-slugstien> So, not to be pedantic or anything, but do we even know where the clock pin is available?
Jun 28 12:42:02 <dyoung> the system clock?  SDRAM clock? or PCI CLock?
Jun 28 12:42:16 <dyoung> (not that I have the answer to any of those questions)
Jun 28 12:42:45 <bw-slugstien> I think I can get the SDRAM clock.  Those pins are exposed.
Jun 28 12:43:32 <dyoung> that would be a good measure because the SDRAM Clock is supposed to be some divosr of the PCI clock.  But I gotta RTFM to verify that
Jun 28 12:44:01 <bw-slugstien> Well, the PCI clock has to be 33MHz.  Unless there is kernel code to change it.  I set it up in the boot loader.
Jun 28 12:46:48 <[g2]> if I had a scope and JTAG, I'd write a tiny assembler program to loop for 100K iterations toggling the a LED / GPIO line at the start and end
Jun 28 12:46:55 <[g2]> and measure it on the scope
Jun 28 12:47:54 <ep1220> I see the PCI clock
Jun 28 12:48:10 <ep1220> the readout says 32.7MHz
Jun 28 12:48:14 <ep1220> so it is 33Mhz
Jun 28 12:48:40 <ep1220> measured on R68, pin closer to the CPU
Jun 28 12:51:04 <bw-slugstien> I'm getting DC from the SDRAM clocks.  
Jun 28 12:52:34 <bw-slugstien> 33MHz from R68.
Jun 28 12:53:43 <bw-slugstien> ep1220: Where is your resource for finding which CPU pins are available on the PCB?
Jun 28 12:55:30 <ep1220> Actually this is not the PCI clock but the Ext:bus Clock (U2)
Jun 28 12:55:43 <ep1220> bw-slugstien: http://www.nslu2-linux.org/wiki/Info/GPIOConnections
Jun 28 12:56:20 <ep1220> plus the bare pcis in the same wiki.
Jun 28 13:02:09 <bw-slugstien> According to the data sheet, the input oscillator is 33MHz.  If the PCI clock is 33MHz I'm confident that the incoming frequency is the same.
Jun 28 13:02:16 <ep1220> Pics are at: http://www.nslu2-linux.org/wiki/Info/PhotosOfTheInternals
Jun 28 13:02:38 <ep1220> bw-slugstien: As I understand: the DS:
Jun 28 13:02:48 <bw-slugstien> So, if the CPU is performing slowly, I'm not confident that this is a clock speed issue.
Jun 28 13:02:57 <ep1220> the 33MHz is multiplied to 266MHz
Jun 28 13:03:14 <bw-slugstien> Right.  So, it could be the part itself.
Jun 28 13:03:22 <ep1220> then the PCI and the Ext_Clk are divided down
Jun 28 13:03:22 <dyoung> right.  when I read it I determined the only way that it couldnt be 266Mhz was for the master clock to not be 33Mhz.
Jun 28 13:03:31 <dyoung> but the osc on the bottom is 33Mhz.
Jun 28 13:03:32 <bw-slugstien> That could be why these slugs are cheap.
Jun 28 13:03:43 <bw-slugstien> These are the chips that couldn't run at full speed.
Jun 28 13:03:49 <ep1220> There is a multiplicatin factor for the PLL
Jun 28 13:03:56 <ep1220> It is set up at boot-time
Jun 28 13:04:10 <[g2]> from the pull ups on the expansion address bus
Jun 28 13:04:12 <bw-slugstien> I can check it, but it's the same one I use in both the slug and the avilla.
Jun 28 13:04:24 <bw-slugstien> Avilla doesn'thave this problem.
Jun 28 13:04:25 <ep1220> So e.g. a 512MHz chip can be clocekd lower
Jun 28 13:04:40 <ep1220> But for 266Mhz CPU only 1 setting is allowed
Jun 28 13:05:06 <dyoung> Maybe some undocumented internal fuse?
Jun 28 13:05:30 <[g2]> it's in the CP15 iirc or what ever that register is
Jun 28 13:05:39 <[g2]> the one bw-slugstien reads right at startup
Jun 28 13:05:44 <dyoung> or maybe these are SX's (instead of DX)
Jun 28 13:05:56 <[g2]> :)
Jun 28 13:06:01 <ep1220> dyoung: The 33mhz we measure is divided from the 266MHz.
Jun 28 13:06:15 <ep1220> If the PLL were at 133 we would see 16,5
Jun 28 13:06:35 <bw-slugstien> 16,5 what?
Jun 28 13:06:39 <dyoung> Mhz
Jun 28 13:06:40 <[g2]> bw-slugstien, 16.5 Mhz
Jun 28 13:06:53 <[g2]> bw-slugstien, do you have an avila ?
Jun 28 13:06:56 <bw-slugstien> That depends on how the chip is designed.
Jun 28 13:07:26 <bw-slugstien> They could easily have circuitry to set the CPU speed independent of the PCI speed.
Jun 28 13:07:39 <dyoung> According to the DS, they are related.
Jun 28 13:07:45 <bw-slugstien> No avilla.  [g2] has let me to believe that the avilla runs faster.
Jun 28 13:07:51 <[g2]> it does
Jun 28 13:08:05 <dyoung> like twice as fast?
Jun 28 13:08:15 <[g2]> exactly twice as fast
Jun 28 13:08:27 <dyoung> thats good news.
Jun 28 13:08:37 <[g2]> the bogo mips show up a 266 and the drystones are 2x
Jun 28 13:08:45 <dyoung> it verifies we havnt been hallucinating all this time.
Jun 28 13:08:51 <bw-slugstien> Where are you seeing the PLL discussion?  I'm reading the guide.
Jun 28 13:08:55 <[g2]> Processor       : XScale-IXP42x Family rev 1 (v5b)
Jun 28 13:08:55 <[g2]> BogoMIPS        : 266.24
Jun 28 13:09:35 <dyoung> bw-slugstien, I'm going on memory.  Lemme open up the document and look, I havnt looked for a few months now
Jun 28 13:09:41 <[g2]> VAX MIPS rating =    199.143
Jun 28 13:09:41 <[g2]> real    0m 14.83s
Jun 28 13:09:41 <[g2]> user    0m 14.29s
Jun 28 13:09:58 <bw-slugstien> Hey!  That boy's got a VAX on hand.
Jun 28 13:09:59 <[g2]> that's the drystone number with takes 29 sec
Jun 28 13:10:08 <[g2]> and comes in at 99
Jun 28 13:10:17 <[g2]> all for 5M iterations
Jun 28 13:10:27 <ep1220> bw-slugstien: Check page 393 in the Dev Manual
Jun 28 13:10:32 <[g2]> VAX MIPS rating =     99.572
Jun 28 13:10:32 <[g2]> real    0m 29.33s
Jun 28 13:11:00 <ep1220> bw-slugstien: the section on GPIO14 and 15
Jun 28 13:11:19 <bw-slugstien> My copy isn't that long.
Jun 28 13:11:36 <[g2]> old copy
Jun 28 13:11:37 <ep1220> the manual has Intel Number: 25248005
Jun 28 13:12:04 <ep1220> IXP42X Developer's Manual
Jun 28 13:12:10 <ep1220> March 2005
Jun 28 13:12:11 <dyoung> iirc, there was an addendum also regarding clocks.
Jun 28 13:12:29 <dyoung> bw-slugstien, if you cant find it I can mail it to you.
Jun 28 13:12:29 <bw-slugstien> That's the one I've been calling the guide...  I was looking for something more definitive.
Jun 28 13:12:36 <dyoung> oh.
Jun 28 13:12:37 <dyoung> ok
Jun 28 13:13:07 <bw-slugstien> I see why you think that this would mean that the CPU couldn't operate at that speed.
Jun 28 13:13:24 <bw-slugstien> I believe they could still have an extra divider circuit for the core input.
Jun 28 13:13:38 <bw-slugstien> The PLL generates 266, but the CPU receives a /2 signal.
Jun 28 13:13:52 <ep1220> Agree, but never read about such a divider.
Jun 28 13:14:12 <bw-slugstien> The only way to know would be to write code and time a gpio line....as [g2] suggested.
Jun 28 13:14:21 <bw-slugstien> ep1220: agreed.  Doesn't mean it isn't there.
Jun 28 13:14:46 <ep1220> If someone writes a GPIO/LED toggle programm i load it into the cache and measure the result
Jun 28 13:14:55 <bw-slugstien> IBM used to sell two card readers.  One was twice as fast as the other.  The only difference was a gear with 1/2 as many teeth.
Jun 28 13:15:23 <bw-slugstien> ep1220: Ah, easy enough to do.  What format do you want.
Jun 28 13:16:12 <ep1220> ideally the HEX values I have to put into the cache (as ASCII text)
Jun 28 13:16:40 <ep1220> should be written so it can run right from reset
Jun 28 13:18:52 <bw-slugstien> Do you want the assembler text?
Jun 28 13:18:58 <[g2]> ep1220, our program could be modified do that
Jun 28 13:19:08 <ep1220> bw-slugstien: yes, the assembler text woudl be OK
Jun 28 13:19:35 <ep1220> g2: nod
Jun 28 13:19:49 <[g2]> what's the decrement instruction ?
Jun 28 13:21:01 <ep1220> I think setting the GPIO to 1 and 0 in an endless loop would be best.
Jun 28 13:21:04 <bw-slugstien> add r0, r0, -1
Jun 28 13:21:15 <[g2]> :)
Jun 28 13:21:22 <[g2]> Ok that's easy
Jun 28 13:21:31 <bw-slugstien> xor on the bit would work.
Jun 28 13:21:32 <[g2]> both the decrement and the toggle
Jun 28 13:22:51 <ep1220> g2: best turn on 1 Led and toggle another
Jun 28 13:23:03 <ep1220> so i can easily see it the prog is loaded correctly
Jun 28 13:23:12 <[g2]> nod
Jun 28 13:24:18 <[g2]> HA
Jun 28 13:24:53 <[g2]> I unplugged the hd so the whole native development environ isn't there anymore :)
Jun 28 13:27:02 <ep1220> [g2]: Toggle D8,9 or 10. Their anode are easy to access.
Jun 28 13:27:34 <ep1220> With D7 some wires are missing on the bare-pics
Jun 28 13:31:18 <ep1220> Sorry, i have to leave now.
Jun 28 13:31:20 <ep1220> g2,bw-slugstien: If You e-mail me the assembly listing I run the test tomorrow morning
Jun 28 13:31:30 <ep1220> good night
Jun 28 13:31:42 <[g2]> sweet dreams
Jun 28 13:31:45 <[g2]> ep1220, THX
Jun 28 13:32:00 <bw-slugstien> nite
Jun 28 13:34:04 <bw-slugstien> How about this:
Jun 28 13:34:15 <bw-slugstien> 	mov r1, #0xc8000000
Jun 28 13:34:15 <bw-slugstien> 	add r1, r1, #0x4000
Jun 28 13:34:15 <bw-slugstien> 	ldr r0, [r1, #4]
Jun 28 13:34:15 <bw-slugstien> 	and r0, r0, #0xfff0
Jun 28 13:34:15 <bw-slugstien> 	str r0, [r1,#4]
Jun 28 13:34:16 <bw-slugstien> 	ldr r0, [r1, #0]
Jun 28 13:34:21 <bw-slugstien> 	and r0, r0, #0xfff0
Jun 28 13:34:28 <bw-slugstien> 	orr r0, r0, #1
Jun 28 13:34:28 <bw-slugstien> 0:	str r0, [r1, #0]
Jun 28 13:34:29 <bw-slugstien> 	xor r0, r0, 0x3
Jun 28 13:34:30 <bw-slugstien> 	b 0b
Jun 28 13:34:47 <bw-slugstien> I'm trying to be safe, reading the existing contents and setting the bits I care about.
Jun 28 13:38:03 <[g2]> or old code was
Jun 28 13:38:42 <[g2]>          mov    r1, #0xC8000000  @ Setup the GPIO address in R1 0xC8004000
Jun 28 13:38:42 <[g2]>          mov    r2, #0x4000      @ Load 0x40..
Jun 28 13:38:42 <[g2]>          orr    r2, r2, r1       @ R2 should now contain 0xC8004000
Jun 28 13:38:42 <[g2]>          mov    r0, #0xff00      @ We forgot to invert last time :)
Jun 28 13:38:43 <[g2]>          orr    r0, r0, #0xf0
Jun 28 13:38:45 <[g2]>          str    r0, [r2,#4]      @ Store it a GPIO_ER
Jun 28 13:38:47 <[g2]>          mov    r0, #0x0003      @ Light up GPIOs 2-3 (DISK 1 and 2)
Jun 28 13:38:49 <[g2]>          str    r0, [r2,#0]      @ Set them
Jun 28 13:38:51 <[g2]> loop:
Jun 28 13:38:53 <[g2]>         b       loop             @ Loop forever
Jun 28 13:38:58 <[g2]> I like the add
Jun 28 13:39:06 <[g2]> save an instruction
Jun 28 13:46:43 <bw-slugstien> I've got one that compiles.
Jun 28 13:46:48 <bw-slugstien>   __asm volatile ("mov r1, #0xc8000000\n\t"
Jun 28 13:46:49 <bw-slugstien> 		  "add r1, r1, #0x4000\n\t"
Jun 28 13:46:49 <bw-slugstien> 		  "ldr r0, [r1, #4]\n\t"
Jun 28 13:46:49 <bw-slugstien> 		  "bic r0, r0, #0xf\n\t"
Jun 28 13:46:49 <bw-slugstien> 		  "str r0, [r1,#4]\n\t"
Jun 28 13:46:51 <bw-slugstien> 		  "ldr r0, [r1, #0]\n\t"
Jun 28 13:46:55 <bw-slugstien> 		  "bic r0, r0, #0xf\n\t"
Jun 28 13:46:57 <bw-slugstien> 		  "orr r0, r0, #5\n\t"
Jun 28 13:46:59 <bw-slugstien> 		  "0: str r0, [r1, #0]\n\t"
Jun 28 13:47:01 <bw-slugstien> 		  "eor r0, r0, #0xf\n\t"
Jun 28 13:47:05 <bw-slugstien> 		  "b 0b");
Jun 28 13:47:07 <bw-slugstien> I'll send it in an email.
Jun 28 13:49:00 <[g2]> I think the thing to goggle is either a 0x2 or 0x4 for disk1 or disk2 leds
Jun 28 13:49:17 <[g2]> I'd have to see the traces ep1220 was referring to
Jun 28 13:49:30 <dyoung> goggle?
Jun 28 13:49:31 <bw-slugstien> I am.
Jun 28 13:49:33 <dyoung> Google?
Jun 28 13:49:34 <dyoung> Toggle?
Jun 28 13:49:46 <bw-slugstien> The regster is loaded with 0x5 and xor'd with 0xf.
Jun 28 13:50:11 <bw-slugstien> that will go back and forth between the disk leds.  And it will light the red/green alternatively.
Jun 28 13:50:17 <[g2]> heh goole
Jun 28 13:50:19 <[g2]> google
Jun 28 13:50:25 <bw-slugstien> am I missing something.
Jun 28 13:50:33 <bw-slugstien> boogle.
Jun 28 13:50:46 <bw-slugstien> Sending it in email.  Untested, but it compiles.
Jun 28 13:51:10 <[g2]> I guess those are separate lines to the LED and your hitting both
Jun 28 13:51:37 <[g2]> so off / orange / off / orange
Jun 28 13:52:29 <bw-slugstien> Right.
Jun 28 13:52:56 <[g2]> that'll work
Jun 28 13:53:44 <[g2]> did you send that to ep1220 too ?
Jun 28 13:53:58 <[g2]> cool thx
Jun 28 13:55:47 <dyoung> boggle
Jun 28 13:55:49 <dyoung> Dongle?
Jun 28 13:55:52 <dyoung> Doggle?
Jun 28 13:56:12 <[g2]> bw-slugstien, that' branh looks a little funny
Jun 28 14:04:42 <[g2]> I've gotta run out for a bit
Jun 28 14:04:43 <[g2]> bbl
Jun 28 14:04:52 <[g2]> THX for all the help
**** BEGIN LOGGING AT Tue Jun 28 16:39:15 2005
Jun 28 23:21:24 <jbowler-away> Am I missing something?  That code seems to be writing to the physical address of the GPIO within the loop, but writing the GPIO is very slow - it won't show the core clock speed at all.
Jun 28 23:23:49 <jbowler-away> mov r0, #0
Jun 28 23:23:58 <jbowler-away> 0: subs r0, r0, #1
Jun 28 23:24:01 <jbowler-away> bne 0b
Jun 28 23:24:59 <jbowler-away> Should take about 32s with a 266MHz core clock (2^33 instructions)
**** ENDING LOGGING AT Tue Jun 28 23:59:57 2005