**** BEGIN LOGGING AT Wed Aug 31 02:59:56 2005
Aug 31 04:49:21 <ulf_> hi, i still have problems with the flashchip using my wiggler jtag on a xscale board 
Aug 31 11:57:34 <ep1220> ka6sox-office: Did You get my e-mail ?
Aug 31 12:01:12 <[g2]> hey ep1220 !
Aug 31 12:01:30 <ep1220> hey [g2] !
Aug 31 12:08:25 <ep1220> [g2]: Did You see this: http://www.linuxdevices.com/news/NS7628968013.html
Aug 31 12:12:27 <[g2]> ep1220 yes I did see that a couple days ago
Aug 31 12:12:33 <[g2]> I didn't check the price though
Aug 31 12:12:45 <ep1220> http://www.linuxdevices.com/news/NS7628968013.html says it is 750$
Aug 31 12:13:04 <[g2]> that's what I thought it would be
Aug 31 12:13:04 <ep1220> Looks like the FTDIchip
Aug 31 12:13:13 <[g2]> the old one was $750
Aug 31 12:13:45 <[g2]> have you been following the slug progress much ?
Aug 31 12:14:09 <[g2]> fyi there's a debian BE and LE port
Aug 31 12:14:30 <ep1220> not carefully. But i read about the debian port
Aug 31 12:14:45 <[g2]> I'm running the BE port and it's pretty sweet
Aug 31 12:16:00 <ep1220> Is there an advantage running BE over LE ?
Aug 31 12:17:06 <[g2]> yes
Aug 31 12:17:20 <[g2]> the BE port uses the openslug kernel which can use the onboard ethernet
Aug 31 12:17:32 <[g2]> the LE port uses an external usb-ethernet adapter
Aug 31 12:17:44 <[g2]> there's only about 1800 packages in the BE port
Aug 31 12:18:07 <[g2]> but porting is really pretty straight forward
Aug 31 12:18:35 <[g2]> I built thttpd, postfix and some other stuff from source this morning
Aug 31 12:20:41 <ep1220> On Your own device: Do You have ethernet BE and LE ?
Aug 31 12:21:13 <[g2]> BE
Aug 31 12:21:37 <[g2]> I haven't run  LE (even though I've got a few usb-ethernet adapters)
Aug 31 12:21:59 <[g2]> from a security point-of-view I'd think BE is much safer
Aug 31 12:22:16 <[g2]> and LE is probably already 1000 x safer than x86
Aug 31 12:22:34 <ep1220> why?
Aug 31 12:22:51 <ka6sox-zzzz> ep1220, got the email..thaniks
Aug 31 12:22:58 <ka6sox-zzzz> and I have printed up the schematic
Aug 31 12:23:07 <ka6sox-zzzz> now putting it on the computer
Aug 31 12:24:17 <[g2]> schematics cool :)
Aug 31 12:24:31 <ep1220> ka6sox-zzzz: transfer to PCB/GEDA?
Aug 31 12:28:31 <ka6sox-zzzz> geda
Aug 31 12:29:05 <ka6sox-zzzz> because the M is not a standard part I'l have to hand lay out..but its fairly easy.
Aug 31 12:29:35 <ep1220> Just 40 pins ;-)
Aug 31 12:29:51 <ka6sox-zzzz> ya...the other one is 50 pins
Aug 31 12:30:59 <ka6sox-zzzz> *just* 50 pins :)
Aug 31 12:34:48 <ep1220> ka6sox-zzzz: I chose parts based on what i and the nearest electronic shop had "in stock"
Aug 31 12:35:27 <[g2]> ep1220 why is LE 1k X safer than x86 ?
Aug 31 12:35:59 <ep1220> yes
Aug 31 12:36:35 <[g2]> because there are > 600 million x86 boxes out there and all 99.9% of all the exploits are written for them
Aug 31 12:37:05 <ep1220> good argument :-)
Aug 31 12:37:14 <[g2]> mac are a lot safer just because they are PPC and only represent < 5% of the market
Aug 31 12:37:55 <[g2]> all the script kidies aren't trying to probe weird arches, they're probing the mainstream stuff
Aug 31 12:39:47 <ep1220> Someone should come up with a CPU which has a programmable unmangler in the prefetch queue.
Aug 31 12:40:04 <ep1220> So each CPU can have its own instruction set.
Aug 31 12:40:20 <ep1220> Also would solve problem of piracy
Aug 31 12:40:35 <[g2]> yeah transmeta did that :)
Aug 31 12:41:00 <ep1220> Damn, i though i could patent it
Aug 31 12:42:24 <ka6sox-zzzz> do it on FPGA's
Aug 31 12:45:41 <[g2]> hey we can't get JTAG going in FPGA's maybe we should start smaller :)
Aug 31 12:45:50 <[g2]> JTAG first, Processors 2nd
Aug 31 12:45:54 <[g2]> :))
Aug 31 12:47:03 <ep1220> Well it does not help against attacks like SQL injection, ...
Aug 31 12:49:46 <[g2]> well I don't know how much SQL SOHO sites will be accepting
Aug 31 12:51:01 <ep1220> arent there similar attacks against php and php based products ?
Aug 31 12:51:43 <[g2]> most of the attacks cause buffer overflows to get code running
Aug 31 12:52:13 <[g2]> an in those cases, it'll be the wrong arch
Aug 31 12:52:21 <ep1220> yea, For these it is a good protection
Aug 31 12:53:39 <[g2]> as far as the Loft goes the roots is on removable media and there's only .5MB flash which can all be quickly verified / reprogrammed from the JTAG header
Aug 31 12:56:19 <ep1220> I have to leave now. See You tomorrow
Aug 31 12:56:30 <[g2]> cheers
Aug 31 14:08:29 <prpplague> anyone have nand flash experience?
Aug 31 14:09:07 <[g2]> not I :(
Aug 31 14:09:49 <ka6sox> we use it at work.
Aug 31 14:11:24 <prpplague> ka6sox: any idea what kind of desktop programmer is used with them? or are they programmed in circuit with jtag?
Aug 31 14:16:20 <ka6sox> we program it with the running system.
Aug 31 14:16:48 <ka6sox> we use nor flash for the boot stuffs and use NAND flash for apps.
Aug 31 17:26:26 <ulf_> hi
Aug 31 18:31:07 <ulf_> hello again, had some problems with my wireless connection from my home to my office
Aug 31 18:33:50 <ulf_> anyway, hi g2 i checked out, that my jtag adaper works but i have some strange results
Aug 31 19:31:22 <[g2]> ulf_, what's that ?
Aug 31 19:31:46 <ulf_> how you mean?
Aug 31 19:32:52 <[g2]> you said you had some strange results
Aug 31 19:33:04 <[g2]> what was strange ?
Aug 31 19:33:19 <ulf_> yes
Aug 31 19:35:22 <ulf_> i erased a part for example "reaseflash 0x00001000 8" so then i readmem at the same adress the first 2048 bytes "readmem 0x00001000 2048 lala.output" and all is ffff...
Aug 31 19:35:28 <ulf_> sofare fine
Aug 31 19:35:53 <[g2]> nod.
Aug 31 19:38:15 <ulf_> now i flashmem at this adress some binary from a file for example flashmem 0x00001000 redboot.bin and after 30 min it stops with an error, now i compare the first part from the org. redboot.bin with on the flash
Aug 31 19:38:59 <ulf_> and it ist almost the same
Aug 31 19:39:29 <ulf_> after some rows i have a some fffff in it
Aug 31 19:40:07 <ulf_> i will show a part here:
Aug 31 19:41:09 <ulf_> 00001d0 e3a0 8452 e1c8 70b0 ee07 0f9a ee12 0f10
Aug 31 19:41:11 <ulf_> 00001e0 e1a0 0000 e24f f004 e3a0 ffff ffff ffff
Aug 31 19:41:12 <ulf_> 00001f0 ffff ffff ffff ffff ffff ffff ffff ffff
Aug 31 19:41:14 <ulf_> *
Aug 31 19:41:16 <ulf_> 0000220 e380 0001 e380 0c02 ee01 0f10 ee12 0f10
Aug 31 19:41:18 <ulf_> the org:
Aug 31 19:43:08 <ulf_> 00001d0 3020 3366 2030 6565 3231 3020 3166 0a30
Aug 31 19:43:10 <ulf_> 00001e0 3030 3030 6130 2030 3165 3061 3020 3030
Aug 31 19:43:12 <ulf_> 00001f0 2030 3265 6634 6620 3030 2034 3365 3061
Aug 31 19:44:17 <ulf_> its easy to see this with xxdif
Aug 31 19:44:56 <ulf_> so it is the same but somehow some rows are now correct written
Aug 31 19:47:56 <ulf_> i am sure the openjtag version  is not able to handle this chip
Aug 31 19:50:22 <ulf_> i do not know what kind of indian i have to use and i do not know whats about the top/bottom boot difference where is the start boot adress, the manual 23579c7.pdf is from the chip
Aug 31 19:51:47 <[g2]> what is the chip again ?
Aug 31 19:52:16 <[g2]> the flash chip ?
Aug 31 19:56:24 <ulf_> 29lv320db
Aug 31 19:56:28 <ulf_> amd
Aug 31 19:57:32 <[g2]> do you know if it's setup for 8-bit or 16-bit
Aug 31 19:58:01 <[g2]> it seems like the flash programming isn't working and needs to be fixed for the chip
Aug 31 19:58:21 <ulf_> yes
Aug 31 19:58:52 <ulf_> if you google for 23579c7.pdf
Aug 31 19:59:05 <ulf_> you will get direct the pdf
Aug 31 19:59:18 <[g2]> You're using a wiggler right ?
Aug 31 20:00:02 <ulf_> my jtag give "only 1x16 2x16 possible" when istart flashmem, yes a wiggler
Aug 31 20:00:09 <ulf_> selfmade
Aug 31 20:01:08 <ulf_> can i just mail you my jtag output for detect and so one?
Aug 31 20:01:33 <ulf_> or is there a mailinglist
Aug 31 20:01:44 <[g2]> you've identified the chip properly right ?
Aug 31 20:02:03 <[g2]> I think it's isolated to the flash programming algorithm
Aug 31 20:02:59 <ulf_> detectflash  gives output about 2 regions
Aug 31 20:03:20 <ulf_> Region 0:
Aug 31 20:03:22 <ulf_>                         Erase Block Size: 8192 B (8 KiB)
Aug 31 20:03:22 <[g2]> right so the JTAG is working
Aug 31 20:03:23 <ulf_>                         Number of Erase Blocks: 8
Aug 31 20:03:25 <ulf_>                 Region 1:
Aug 31 20:03:26 <ulf_>                         Erase Block Size: 65536 B (64 KiB)
Aug 31 20:03:28 <ulf_>                         Number of Erase Blocks: 63
Aug 31 20:03:32 <ulf_> i hope so
Aug 31 20:03:55 <[g2]> so it's just that the flash chip is supported
Aug 31 20:04:05 <ulf_> i think so
Aug 31 20:04:14 <[g2]> the question is where do you go from there
Aug 31 20:04:33 <[g2]> 1) add support for the chip yourself
Aug 31 20:04:47 <ulf_> i am not able to write such code
Aug 31 20:05:10 <[g2]> 2) find someone (like mabybe the jtag tool maintainer) to possibly update it
Aug 31 20:08:35 <ulf_> do you have writemem in your jtag tool
Aug 31 20:09:19 <ulf_> i am using debians jtag 0.5.1 i downloaded the sources but i get error messaged while compiling
Aug 31 20:13:17 <[g2]> well you'll have to figure out those errors
Aug 31 20:13:33 <[g2]> It looks like the code is in src/flash.c
Aug 31 20:19:46 <ulf_> ok i took the cvs checkout
Aug 31 20:21:49 <ulf_> hmm sorry for my stupid questions, now i have the all this folders in my folder where i made the checkout, but what i have to do now?
Aug 31 20:22:30 <ulf_> there is no chance to make a ./configure 
Aug 31 20:24:37 <[g2]> ./configure doesn't work for you ?
Aug 31 20:25:15 <ulf_> well i jumped into the jtag folder 
Aug 31 20:25:30 <ulf_> ahh ok i have to use automake
**** BEGIN LOGGING AT Thu Sep 01 02:16:41 2005
**** ENDING LOGGING AT Thu Sep 01 02:59:56 2005