**** BEGIN LOGGING AT Sat Sep 10 02:59:56 2005 Sep 10 08:15:27 hmm... is there anyone awake who's working on the openjtag project? i've been working on a jtag based debugger for arm systems for some time now, and i'd like to know at what point openjtag currently is - the wiki only mentions fairly general stuff Sep 10 08:16:15 vmaster: not much done here so far. Sep 10 08:16:36 I do have a prototype ofa FTDI2232C Jtag/USB IF Sep 10 08:16:46 Plus basic software. Sep 10 08:16:49 heh, that's what i'm working with, too Sep 10 08:17:06 heh Sep 10 08:17:20 Did You do some HW/PCB ? Sep 10 08:17:45 just a prototype on a breadboard Sep 10 08:17:57 dlp2232m eval module + voltage regulator that generates 3.3v Sep 10 08:18:03 same as me :-) Sep 10 08:18:50 I use XScale as "victim" for tests Sep 10 08:19:01 mhh, my software supports arm7 and arm9 targets Sep 10 08:19:23 well, arm7tdmi + arm720t, no arm7-s, and arm920t Sep 10 08:19:51 You do debugging ? Sep 10 08:19:51 but i felt a bit uncomfortable with the software i've written so far, so i decided to rewrite the whole thing Sep 10 08:19:55 yes Sep 10 08:20:01 GDB I guess Sep 10 08:20:12 a telnet interface and a gdb interface Sep 10 08:20:15 much like bdi2000 Sep 10 08:20:54 i'm currently extending the jtag interface, to allow support for boundary scan jobs, probably a svf player Sep 10 08:21:12 svf = ? Sep 10 08:21:18 serial vector format Sep 10 08:21:33 it's used to test boards, and to program cplds and fpgas Sep 10 08:21:51 here we are primarily into debugging and FLASH/FPGA programming Sep 10 08:22:22 did You roll your own SW ? or base on another project ? Sep 10 08:23:12 its written completely from scratch - i did look at jtager and arm9-jtag, but these projects had too many problems to serve as a solid base Sep 10 08:23:38 openocd.berlios.de - the page doesn't have much yet, but the latest version (alpha2) works fine for the above mentioned targets Sep 10 08:24:45 Which license ? Sep 10 08:24:47 gpl Sep 10 08:25:59 I was thinking GPL too, or maybe BSD Sep 10 08:26:36 i'm struggling a bit with some issues with the ftdi2232 and a fpga board with a fpga and a cpld in a daisy-chain Sep 10 08:27:15 reading the idcode using a wiggler (clone) works just fine - with the ftdi, i get bogus output Sep 10 08:27:24 works fine on my single-device arm targets though... Sep 10 08:27:33 So far i only used it on Single device in chain, too Sep 10 08:28:01 Did you try a lower clock ? Sep 10 08:28:12 down to a few khz Sep 10 08:29:12 Your SW is for linux ? Sep 10 08:29:32 i was thinking about problems with the load that needs to be driven... tms and tck are shared by both devices in the chain, but i lack the electrical knowledge Sep 10 08:29:35 yes Sep 10 08:29:46 it should be fairly simple to port it to windows/cygwin Sep 10 08:29:57 but that's zero priority for me Sep 10 08:29:59 Just asking,. as the Windows JTAG lib available from FTDI has a bug Sep 10 08:30:16 which can give strange results. Sep 10 08:30:19 ah, ok Sep 10 08:30:28 use libusb ? Sep 10 08:30:34 libusb + libftdi Sep 10 08:31:01 guess i'll try to get an oscilloscope Sep 10 08:31:24 Good idea. Sep 10 08:32:07 I am an EE. The FTDI should be able to drive 2 inputs in parallel Sep 10 08:32:30 I did not use libftdi, but wrote my own replacement Sep 10 08:32:50 (actually I started on Windows and then ported to Linux) Sep 10 08:33:38 Can You elimiante the CPLD from the scan chain ? Sep 10 08:35:18 hmm, no Sep 10 08:36:09 Which FPGA ? Sep 10 08:36:59 a xilinx virtex-2 Sep 10 08:37:46 the target is fine - my software supports wiggler-clones, too, and using it, everything is fine Sep 10 08:41:32 I do have a SPARTAN3 board here. must check if it has 2 devices in the chain. Sep 10 08:41:43 Then i could try reading the ID here. Sep 10 08:49:49 the ftdi datasheet mentions a high-drive mode - could that solve the problem? or would i risk damaging something? Sep 10 08:50:54 and if you're interested: http://mmd.ath.cx/thesis/ Sep 10 08:54:45 vmaster: I be back in 20minutes Sep 10 08:56:20 morning Sep 10 09:05:02 morning sox... Sep 10 09:05:15 (i mean ka6sox ;-) ) Sep 10 09:05:47 ka6sox: did you finally get your g+? Sep 10 09:08:54 I'm trying to upload a kernel image to ppcboot using loadb (kermit), but after a few fragments, transmission errors occur and the transfer aborts... any hints? Sep 10 09:11:00 with serial? Sep 10 09:13:52 yes Sep 10 09:14:27 vmaster: By enabling the high-drive mode you can not damage anything Sep 10 09:15:37 ah, okay, thank you Sep 10 09:15:41 i'll try that Sep 10 09:15:45 ka6sox: morning Sep 10 09:16:06 vmaster: Are You sure the libftdi is fully tested ? Sep 10 09:16:38 one need to be very carefull to get the FTDI send TMS at the time one wants ;-) Sep 10 09:17:16 vmaster: Do You have a schematic of Your FPGA/CPLD target ? Sep 10 09:17:38 If so check if there are pull-up/down resistros on the JTAG lines. Sep 10 09:17:53 s/resistros/resistors/ Sep 10 09:19:33 the libftdi works fine for single targets, and i've been able to download data at 25kbyte/s to an arm920t target Sep 10 09:19:47 if there were any problems, i guess i should have encountered them before Sep 10 09:20:57 the schematics doesn't show pull-downs Sep 10 09:21:17 and no pull-ups, either Sep 10 09:21:25 <[g2]> heh which schematics ? Sep 10 09:21:43 a fpga/cpld dev board i'm working with Sep 10 09:22:03 <[g2]> excellent. what's the board going to do ? Sep 10 09:22:27 vmaster: then likely it is not a drive problem. Sep 10 09:22:35 <[g2]> hey ep1220 ! Sep 10 09:22:51 [g2]: heh, nothing at the moment - i'm just using it as a target to debug my jtag code Sep 10 09:23:04 <[g2]> great! Sep 10 09:23:12 vmaster: the board is on 3.3V at JTAG ? Sep 10 09:23:15 hey [g2] Sep 10 09:23:17 <[g2]> I'm getting my prototype boards next week Sep 10 09:23:24 great Sep 10 09:23:39 <[g2]> I'll may have a little need for some JTAG tools very soon :) Sep 10 09:24:04 <[g2]> Although, I've got a connector and I'll probably be able to re-flash the .5MB bootflash Sep 10 09:24:22 vmaster: Your thesis is interesting. Sep 10 09:24:32 <[g2]> url ? Sep 10 09:24:43 vmaster: Is the schematic of the FTDI complete ? Sep 10 09:24:44 <[g2]> sorry if I'm butting in here Sep 10 09:24:51 yes Sep 10 09:25:02 <[g2]> yes I'm butting in ? Sep 10 09:25:08 nah, the schematic is complete ;) Sep 10 09:25:18 [g2]: http://mmd.ath.cx/thesis/ Sep 10 09:25:23 <[g2]> thx Sep 10 09:25:40 2comments on the schematic Sep 10 09:26:05 1) there should be a ceramic 47 or 100nf cap from VCCIOA/B to ground. Sep 10 09:26:24 2) SI/WUA should not be open but at 3.3V Sep 10 09:27:19 i haven't done the board myself, just fixed some bugs my professor made... let me check this Sep 10 09:31:20 there is a 10uF capacitor to ground - is that too much? Sep 10 09:31:55 i really have only basic ee knowledge... so i'm a bit lost Sep 10 09:32:01 vmaster: NO. that one is OK. but it's impedance is too high at higher frequencies Sep 10 09:32:19 ok, so an additional cap would be needed? Sep 10 09:32:31 yes. in parallel to the 10uF Sep 10 09:32:34 ok Sep 10 09:33:41 but it need to be a ceramic capacitor ! Sep 10 09:34:09 the 10uF cap can't filter out the High Frequencies..the Ceramic does. Sep 10 09:34:26 Do You use thru-hole or SMD ? Sep 10 09:34:38 thru-hole Sep 10 09:34:44 0.2inch Sep 10 09:36:04 <[g2]> vmaster is that your masters thesis ? Sep 10 09:36:23 diploma thesis Sep 10 09:36:44 vmaster: Your study is 3 or 5 years ? Sep 10 09:36:54 heh, 4 Sep 10 09:37:20 in germany, we used to have diploma Sep 10 09:37:35 [g2]: then it is something between bachelor and masters Sep 10 09:37:36 they're currently transitioning to a bachelor/master scheme Sep 10 09:37:38 yeah Sep 10 09:37:45 <[g2]> ahh.. thx Sep 10 09:38:05 <[g2]> On a glance it looks very good to me Sep 10 09:38:06 i'm about to start studiying for my master in october - it's a 1-year add-on Sep 10 09:38:19 <[g2]> and I think you're in the right spot Sep 10 09:40:21 vmaster: Do You have access to a digital scope or a LA? Sep 10 09:40:32 i can get one next week Sep 10 09:41:05 vmaster, your paper is good. Sep 10 09:41:13 thx :) Sep 10 09:41:47 i saw the options you're considering as jtag hardware Sep 10 09:42:19 amontec (the chameleon dongle) is working on a usb-replacement for their paralell port chameleon, which is going to have an fpga (spartan, iirc) Sep 10 09:42:41 the S3 board is relatively cheap but the interface takes it up too much. Sep 10 09:42:52 the new S3e should solve this problem. Sep 10 09:43:22 ah, the one that's delayed till decemeber? Sep 10 09:43:26 for higher performance I would still like to use the FPGA . Sep 10 09:43:33 vmaster, yes Sep 10 09:43:39 ok Sep 10 09:44:40 vmaster: BTW: Is Your Virtex board a commercial eval-board ? Sep 10 09:45:30 no. you can find it at fpga-dev.de Sep 10 09:45:43 Virtex2? Sep 10 09:46:05 i got it from ebay - the person that created it sold it on ebay for 99 euros, i couldn't resist Sep 10 09:46:25 virtex2 250k gates Sep 10 09:47:42 i always wanted to play around with fpgas, and currently it's nice to have something with two devices in the jtag scan chain, to debug my code Sep 10 09:48:10 most of my boards are 3 or more devices. Sep 10 09:48:18 combo of FPGA/CPLD Sep 10 09:49:36 initially i started working on an ARM debugger (all targets i haved had only one device) - right now i'm rewriting the code to support multiple jtag devices, probably boundary-scan features and such Sep 10 09:54:15 vmaster: It seems my Spartan3 has also 2 devices in the chain. Sep 10 09:54:29 So I can try my SW too ;-) Sep 10 09:56:20 ah, yeah, would be nice to see if it works for you Sep 10 09:57:02 I'l try on monday. Sep 10 09:58:48 hmm... i just enabled high-drive, and it seems to work Sep 10 09:59:11 good ! Sep 10 09:59:49 yeaaah... it works :) Sep 10 09:59:52 thx ep1220 Sep 10 09:59:59 np Sep 10 10:00:53 actually, was your idea to enable high-drive :-) Sep 10 10:01:46 yeah, but i didn't dare to enable it, as i had no idea if that could burn my hardware Sep 10 10:06:55 [g2]: yesterday ka6sox and I talked about making a PCB for the DLP2232M Sep 10 10:07:13 :) Sep 10 10:07:25 amontec wanted to make one, too... haven't heard from them for a while Sep 10 10:07:49 <[g2]> the did the chamealon ? Sep 10 10:07:53 yes Sep 10 10:08:08 i got in contacted with them when i tried to get some information about the raven Sep 10 10:08:14 <[g2]> that looks like a great idea from a couple years ago Sep 10 10:08:20 heh, yeah Sep 10 10:08:49 <[g2]> I think we are looking to do the same except open-source the sw and make the HW way cheaper Sep 10 10:09:07 <[g2]> and use current generation hw not vintage stuff Sep 10 10:09:32 the FTDI part is current tech. Sep 10 10:09:40 <[g2]> I got a raven the other day Sep 10 10:09:41 I am also unsure if the FTDI is faster than a Raven Sep 10 10:09:53 <[g2]> someone sent me one free Sep 10 10:10:01 <[g2]> along with a NIOS kit Sep 10 10:10:16 hmm, i achieved around 12kb/s ram download with the raven Sep 10 10:10:20 seems I know the wrong people :-( Sep 10 10:10:29 compared to 25kb/s using the ftdi2232 Sep 10 10:10:34 kbyte Sep 10 10:10:55 <[g2]> vmaster do you vhdl/verilog ? Sep 10 10:11:19 no, but i plan on learning it - haven't done anything with it yet Sep 10 10:12:06 <[g2]> do you know what those Virtex II boards cost ? Sep 10 10:12:32 i bought mine for 99 euros, but the five boards he sold on ebay were the last ones, i guess Sep 10 10:12:49 the virtex 2 is ~150$ alone Sep 10 10:12:52 <[g2]> is there a new design planned ? Sep 10 10:13:16 i don't know - i saw it on ebay, sent him the money, and got my board on tuesday Sep 10 10:13:22 <[g2]> heh Sep 10 10:14:32 <[g2]> well I'm really ready to get things rolling Sep 10 10:14:51 <[g2]> ep1220 has been a great driver Sep 10 10:15:07 <[g2]> my hat's off to him for all his great work Sep 10 10:15:31 to much honor Sep 10 10:15:38 s/to/too/ Sep 10 10:15:46 <[g2]> however, I see at least 3 major needs in the near future Sep 10 10:16:15 <[g2]> One .. I want to be able to ship real cheap hardware with my board which comes with a jtag header Sep 10 10:16:31 real cheap == wiggler clone Sep 10 10:16:58 <[g2]> two .. The NSLU2s really need cheap easy JTAG bootloader testing Sep 10 10:17:16 mhh, what's the NSLU2? Sep 10 10:17:26 <[g2]> three ... The Linksys RV series has a 20 pin JTAG layout... Sep 10 10:17:45 vmaster, its a NAS box that we have been hacking on for a year Sep 10 10:17:49 <[g2]> I'd like to start seriously hacking those boards after the Loft is up and running Sep 10 10:18:26 <[g2]> the NSLU2, Loft and Linksys Rv boxen are all IXP4xx base Xscale Sep 10 10:18:52 <[g2]> IXP420, IXP422 and IXP425 to be exact Sep 10 10:19:31 ah, nice Sep 10 10:19:32 425 has a VPN engine? Sep 10 10:19:36 USB2.0 to Ethernet? Sep 10 10:19:39 cool Sep 10 10:20:10 <[g2]> the Loft as the 422 that's got the crypto hw too Sep 10 10:20:16 <[g2]> Loft has Sep 10 10:21:16 very nice Sep 10 10:24:02 [g2]: the FTDI will not meet your need one Sep 10 10:24:47 <[g2]> ep1220 I'm interested in the FTDI but it's kinda a middle ground Sep 10 10:25:10 <[g2]> If we can build it pretty cheaply then I'd use that Sep 10 10:25:44 <[g2]> But we can buy cheap wigglers from digilent for like $12 bucks Sep 10 10:25:57 <[g2]> I haven't played with the USB version which is $19 Sep 10 10:27:25 the digilent USB does not give You reset and TRST Sep 10 10:27:34 but is OK for FLASH programming Sep 10 10:28:35 [g2]: unless You go for a few hundred units the FTDI will not come below 60-70$ Sep 10 10:28:49 ep1220, I still like the idea of using the icache to program the flash in a Xscale :) Sep 10 10:29:40 this will give You great performance. but need HW which controls reset and TRST Sep 10 10:29:58 <[g2]> ep1220 at those prices it just makes sense to go with an S3 build or just buy S3 dev boards Sep 10 10:30:41 g2: disagree. the S3 dev board plus USB is 200$ Sep 10 10:31:11 And this is no yet a JTAG Sep 10 10:31:40 does anyone know what is "inside" the digilent usb part? Sep 10 10:31:54 a cypress USB2 chip Sep 10 10:32:47 nice Sep 10 10:33:51 g2: there are other costs, like a USB vendor ID is 1500$ Sep 10 10:33:55 <[g2]> ep1220, I've been told that an S3 can drive line rate JTAG (10 Mbs scan change) via a parallel adapter Sep 10 10:34:10 <[g2]> it makes sense to me Sep 10 10:34:29 You mean connect to the parallel port ? Sep 10 10:34:49 <[g2]> I'm saying the host connection isn't the limiting rate Sep 10 10:35:11 <[g2]> and the new S3 board has ethernet memory on board for $150 Sep 10 10:35:25 I did some eval on S3, I can do 40-70Mhz ;-) Sep 10 10:35:41 <[g2]> on the scan chain ? Sep 10 10:35:46 yes. Sep 10 10:35:52 <[g2]> right.... Sep 10 10:36:08 <[g2]> so the limiting issues in my mind are: Sep 10 10:36:11 g2: but you still need JTAG headers Sep 10 10:36:13 <[g2]> 1) The FPGA programming Sep 10 10:36:23 <[g2]> 2) the interface to the host Sep 10 10:36:43 hi Sep 10 10:36:46 agree Sep 10 10:37:04 <[g2]> short term I may have some minor issues with JTAG Sep 10 10:37:19 <[g2]> my case with the Loft is pretty straight forward Sep 10 10:38:16 after some week without success i stoped working on jtaging the ixp425 based board. Sep 10 10:38:25 <[g2]> I've got 4Mb part which is only .5MB Sep 10 10:38:35 <[g2]> so I don't have a ton of reprogramming to do Sep 10 10:38:56 <[g2]> Redboot it probably already ported and working on the board Sep 10 10:39:04 <[g2]> s/it/is/ Sep 10 10:39:27 <[g2]> However, this is a *very* important item long-term open development Sep 10 10:39:38 <[g2]> and a "brick-free" envirionment Sep 10 10:40:19 <[g2]> ulf_k thanks for hanging around Sep 10 10:40:47 you are very welcome Sep 10 10:42:30 <[g2]> ulf_k you just need a flash programming update Sep 10 10:43:20 how you meen update? i can maybe work on a very expencive windows tool for example Sep 10 10:43:53 <[g2]> I mean you need the flash programming algorithms updated for the JTAG tool Sep 10 10:44:08 ahh yes Sep 10 10:44:15 <[g2]> or you need to just download a small program to memory Sep 10 10:44:41 <[g2]> It might be easy for someone like ep1220 or vmaster to update the jtag tools to allow memory writes Sep 10 10:44:54 <[g2]> then we'd be able to download programs to the memory Sep 10 10:45:02 well my openjtag is not able to write mem Sep 10 10:45:12 i saw a patch for it in the cvs Sep 10 10:45:17 <[g2]> that's the capability I'm talking about use adding Sep 10 10:45:27 <[g2]> s/use/us/ Sep 10 10:45:36 <[g2]> if it's in CVS then all the better Sep 10 10:45:52 <[g2]> we should sign up for the jtag ML or get on the forum Sep 10 10:46:50 one big question i have, can you look on this website, there are 3 ways of plugs, the 14 and 20 pin, i know, but also one 8 pin version, here the link: Sep 10 10:46:54 http://hri.sourceforge.net/tools/jtag_faq_org.html Sep 10 10:48:03 ok my board has a not printed 20 pin jtag i put that plugs on it and tried all the time, now i saw that there is one factory made 8 pin plug Sep 10 10:48:42 the same as shown in the faq, with one missing an 5 Sep 10 10:51:38 so my question what is pld programming? Sep 10 10:52:08 pld = Programmable logic device (AKA: PAL;GAL;CPLD;FPGA;..) Sep 10 10:53:28 do i need for this a special connector or can i use the wiggler adapter Sep 10 10:56:26 [19:43] < [g2]> It might be easy for someone like ep1220 or vmaster to update the jtag tools to allow memory writes Sep 10 10:56:32 memory writes for xscale? Sep 10 10:56:39 <[g2]> nod Sep 10 10:56:58 <[g2]> ep1220 has written to the mini-I cache and booted off it Sep 10 10:57:22 <[g2]> that's a significant milestone in my book Sep 10 10:57:30 yeah Sep 10 10:57:38 xscale debugging is somewhat different from other ARMs Sep 10 10:57:56 <[g2]> If we just added loading the mini-I cache or the full I-cache we could load a bootloader with serial and boot it Sep 10 10:58:01 <[g2]> APEX for example Sep 10 10:58:28 <[g2]> We'd only need to bring up serial, memory, and the ability to flash Sep 10 10:58:43 do you know "jeelie"? Sep 10 10:58:59 <[g2]> actually... just serial and memory as we could download additional code and run it over the serial Sep 10 10:59:11 <[g2]> don't know jeelie Sep 10 10:59:16 <[g2]> should I ? Sep 10 10:59:26 <[g2]> Do you know bewoolie ? Sep 10 10:59:30 <[g2]> beewoolie ? Sep 10 10:59:45 ah, jelie Sep 10 10:59:47 http://lap.epfl.ch/dev/arm/jelie/ Sep 10 10:59:57 <[g2]> http://wiki.buici.com/twiki/bin/view/Main/ApexBootloader#IXP42x_and_the_Linksys_NSLU2_aka Sep 10 10:59:58 an open source xscale jtag debugger Sep 10 11:00:18 <[g2]> that's sounds very nice :) Sep 10 11:00:38 g2: JMunakra mentioned this one some time ago Sep 10 11:01:12 they use the ezUSB Sep 10 11:02:42 <[g2]> great so using jellie with a wiggler would work assuming IXP4xx hardware is supported Sep 10 11:02:51 it is not Sep 10 11:03:21 but as they're both xscale, it shouldn't require too much to get it work Sep 10 11:03:40 <[g2]> exactly :) Sep 10 11:28:01 pld programming: does this strange little chip called "lattice lc4032v" has something to do with this? Sep 10 11:30:05 yes. this is a CPLD Sep 10 11:30:16 aha ok Sep 10 11:30:48 can you tell me a bit more about, please? Sep 10 11:32:18 Do You have a schematic of the board You are using ? Sep 10 11:33:24 i can send you a picture, i am still working on a final infopage with all this stuff Sep 10 11:34:36 picture of the PCB ? Sep 10 11:41:15 stupid 24h reconnect from provider Sep 10 11:41:53 i hate this, i have to set a cron to reconnect at 7 in morning Sep 10 11:42:42 what TZ are you in ulf? Sep 10 11:42:56 well ep1220 what is a PCB? Sep 10 11:43:11 circuit board Sep 10 11:43:50 ohh all your shortcuts i guess timezone, haha germany Sep 10 11:44:35 CEST Sep 10 11:44:57 okay...didnt' htink it was 7am in CEST Sep 10 11:45:23 it is not :-) Sep 10 11:45:32 it is 8:46pm Sep 10 11:45:35 here its 8pm Sep 10 11:45:55 CEST is eastern timezone +6h, iirc Sep 10 11:46:40 oh...wait. Sep 10 11:46:41 you are all from us? Sep 10 11:47:02 I am GMT -8 Sep 10 11:47:18 ok, CEST is GMT+1 Sep 10 11:47:33 yes Sep 10 11:47:43 by the way, is it allowed to present pdf file from the fcc on a own website for information? Sep 10 11:48:20 the FCC database is supposed to be public domain Sep 10 11:48:29 but not always. Sep 10 11:48:53 there *might* be somethings that they keep but you shouldn't be able to get anything from there that isnt' public. Sep 10 11:49:11 I'm assuming you mean Federal Communications Commission. Sep 10 11:49:24 yes Sep 10 11:49:40 the pdfs are public Sep 10 11:49:46 on the fcc website Sep 10 11:49:56 are you looking at a circuit board picture? Sep 10 11:50:23 well the circuit board picture i made by my self Sep 10 11:50:47 is that posted somewhere? Sep 10 11:50:55 but the wireless cards on this device are shown in some pdfs from dlink on the fcc website Sep 10 11:51:18 ulf_k_: if the pdf is public on the fcc site, put a link to the original location on your page - that way you're on the safe side Sep 10 11:51:45 good plan Sep 10 11:52:14 yes normaly but now you can not find this fcc site any more Sep 10 11:52:31 archive.org maybe Sep 10 11:52:31 what was the pdf of? Sep 10 11:54:15 ok, give me about an hour to setup all this, i am still weeks sitting here and thinking of putting all this on my website Sep 10 11:54:35 k Sep 10 11:55:44 but first a cool beer, you have to know since 2 days im in my new office, the old was attacked from the rats ;) Sep 10 11:56:29 <[g2]> ulf_k_ where is your web site ? Sep 10 11:56:34 and im so happy to finish the old office story after 3 years Sep 10 11:56:35 <[g2]> as in URL ? Sep 10 11:58:32 ka6sox: back to FTDI ;-) Sep 10 11:58:33 about my project http://www.wlanhain.de but its not updated since half a year, and it is in german only, but my girlfriend translated it already, she is from the states Sep 10 11:59:08 I plan to add serial and level-converters Sep 10 11:59:22 maybe 4 GPIO pins (?) Sep 10 11:59:34 okay...is that in addition to the SSE stuff? Sep 10 11:59:39 yes Sep 10 12:00:06 multi headed hydra....cool Sep 10 12:00:25 serial is 3.3V only (?) Sep 10 12:00:30 that would be a useful tool. Sep 10 12:00:38 I think so. Sep 10 12:00:39 JTAG is 1.2 to 3.3V Sep 10 12:01:11 (?)was more: do you need another voltage as well ? Sep 10 12:01:47 3.3v serial (before level shifters) is very good. Sep 10 12:01:52 5v is unnecesary Sep 10 12:02:25 I did not plan level-shifters on the serial (RS232) Sep 10 12:02:41 k Sep 10 12:02:47 then 3.3v is still good. Sep 10 12:03:30 5V on JTAG is an issue for You ? For anyone else listening. Sep 10 12:04:01 trying to remember if I have anything that uses 5v jtag Sep 10 12:08:05 open point: Which JTAG header ? 14, 20pins ? ARM, MIPS,.. More than one ? Sep 10 12:08:14 more than one Sep 10 12:08:29 7 digilent 14 and 20 would be nice. Sep 10 12:09:05 have you seen the faq from hri Sep 10 12:09:12 http://hri.sourceforge.net/tools/jtag_faq_org.html Sep 10 12:09:29 the hri project is great Sep 10 12:10:49 ulf_k_: Thx for the URL Sep 10 12:11:29 you are welcome Sep 10 12:11:38 ka6sox: I think i try to use thru-hole parts wherever possible. Sep 10 12:11:49 guess, size is not so important. Sep 10 12:11:49 sounds easy to build. Sep 10 12:12:41 right, so everyone who does not want to pay for building can do it himself Sep 10 12:23:48 very ince Sep 10 12:24:28 er nice Sep 10 12:25:08 I'll buy a couple of blank boards...:) Sep 10 12:25:59 :-) Sep 10 15:55:28 someone stiff awake? Sep 10 15:55:57 yeah Sep 10 16:03:31 i an finished with updating website and put a picture from the xscale based accesspoint dwl-7000 Sep 10 16:03:45 here the link: http://www.wlanhain.de/morewireless/hardware/dwl-7000/ Sep 10 16:07:26 ok, and what was your question regarding this? Sep 10 16:10:57 some days ago i had a conversation with g2 about my jtag problem on this board, i use the 20pin jtag, yesterday i saw on the jtag faq website from hri 3 ways of jtag 14 pin 20 pin or 8pin for pld Sep 10 16:11:42 and this board has a lattice CPLD Sep 10 16:11:47 yeah Sep 10 16:12:06 the 8-bit header is the lattice isp layout Sep 10 16:12:17 so how do i use the 8 pin interface with what kind of hardware and what kind of tools? Sep 10 16:13:21 i guess this is different to the 20 pin jtag with wiggler adapter i use with my parallelport Sep 10 16:13:40 what do you want to do? do you want to program the pld? or do you want to work with the processor? Sep 10 16:14:00 the signals are more or less the same, on the 20 pin header Sep 10 16:14:05 i what to write to the flash Sep 10 16:14:36 ok, the signals are almost the same Sep 10 16:14:54 the 20-pin arm header has reset signals that the 8-pin header misses Sep 10 16:15:12 so d i use still my wiggler adapter? Sep 10 16:15:43 it depends on how the components are wired on the board Sep 10 16:15:49 jtag devices can be put in a chain Sep 10 16:16:15 vmaster, yes but a lot of things have the digilent connector. Sep 10 16:16:20 so it should be included ;) Sep 10 16:17:12 included where? Sep 10 16:18:00 ulf_k_: www.intel.com/design/iio/ devtools/iq80310/lattice_ispdownload.pdf that's the layout of the lattice header Sep 10 16:20:58 and there's the layout of the embedded-ice connector (20-pin): http://www.arm.com/support/Embedded-ICE%20Adaptor%20Schematic.pdf Sep 10 16:24:51 sorry i don't understand all this :( i will make i little summary: i use a selfmade par port adapter to 20 ping jtag and use jtag from openwince to access to the board, this works somehow, because i get infos back from the board when givving the command detect and detectflash 0, so far so good but i can not write maybe read as well i do not really know Sep 10 16:26:40 ah, okay Sep 10 16:29:15 oh..niever mind... Sep 10 16:32:57 so this strange errors i get while flashing written stuff is comparing from the original i have continuous parts where f's written instead of real content Sep 10 16:34:43 and how the other connection possibility can maybe work without this errors while writing to the flash, so what should i do now, can i just plug my jtag adapter in the correct pin layout to the 8 ping plug instead of the 20 pin plug Sep 10 16:34:49 an erased flash is all ones, so continous parts with only ffs is an erased region Sep 10 16:35:27 this isn't a matter of the jtag connection, if the jtag tools were able to identify the chip and the flash Sep 10 16:36:14 well the the flash chip is not really supported Sep 10 16:36:33 it is a am29lv320 and only 160 and 640 are supported Sep 10 16:36:58 but erasing, and reading are passible Sep 10 16:38:25 when reading some parts from the flash it is correct i hope, at least there are no continuous parts with fff Sep 10 16:41:06 ka6sox: have you seen the dwl7000 picture Sep 10 16:42:56 ulf_k_: it's likely that you'll have to change the code in amd.c to match your flash chip Sep 10 17:02:42 ulf not yet. Sep 10 17:02:47 do you have them? Sep 10 17:03:14 yes i have the cvs soure Sep 10 17:03:40 libbrux/flash/amd.c Sep 10 17:05:03 I'm asking about the pictures Sep 10 17:05:10 oh too late, i see Sep 10 17:05:39 yes: http://www.wlanhain.de/morewireless/hardware/ dwl-7000 Sep 10 17:39:46 i have to go home its almost 3 in the morning **** ENDING LOGGING AT Sun Sep 11 02:59:56 2005