**** BEGIN LOGGING AT Tue Oct 25 02:59:58 2005 Oct 25 07:58:36 oh great... i've spent a day or two debugging a problem with my debugger and an arm7tdmi-s (lpc2294) - i wasn't able to debug the chip out of reset - today someone from rowley replied to the lpc newsgroup that this is a generic problem with all lpc2xxx devices... the philips guys just told me that they didn't know about any problem with the reset lines... Oct 25 07:59:08 hehe Oct 25 07:59:10 gotta love errata Oct 25 08:00:20 got a reply from ftdi today, looks like they fixed the deadlock problem i experienced :) Oct 25 08:05:32 <[g2]> ep1220 sounds like you've got boards :) Oct 25 08:09:18 [g2]: yes Oct 25 08:10:23 the module is detected on USB and serial is working Oct 25 08:10:57 however digikey sent me a 5V regulator though i ordered a 3.3V Oct 25 08:11:47 the box was labeled correctly, but the parts inside were different :-( Oct 25 08:12:19 took me some time to organize a replacement and install it Oct 25 08:12:43 must check if the level-shifters have been damaged Oct 25 08:32:43 <[g2]> bummer about the part mix up :( Oct 25 08:33:36 <[g2]> can you send me some pics ? Oct 25 08:44:37 [g2], I'm looking for your addy and I'll send them Oct 25 08:47:52 <[g2]> thx Oct 25 08:49:06 on its way to you. Oct 25 08:51:13 hmm... ftd2xx still dead locks... :( Oct 25 09:05:19 [g2], did you get em? Oct 25 09:29:55 morning ep1220 Oct 25 09:30:18 morning Oct 25 09:30:28 I have the regulator here :) Oct 25 09:30:44 good for You :-) Oct 25 09:30:55 picked it up when I got the BOM. Oct 25 09:31:20 So digikey sent them to You and not to me ;-) Oct 25 09:31:44 bummer...I ordered 2 weeks ago. Oct 25 09:32:04 me too about this time Oct 25 09:32:23 i got a replacement from LT, different pinning but managableat 3 pins :-) Oct 25 09:33:16 will see how long it takes them to send a replacement Oct 25 09:33:28 doing the 'twist' to make it work? Oct 25 09:33:57 yes; VIN-GND-VOUT vs GND-VOUT-VIN Oct 25 09:34:18 yep...doing the twist... Oct 25 09:35:21 the voltage regulator is up too, DC Voltage as calculated, did not see instability Oct 25 09:41:10 excellent **** BEGIN LOGGING AT Tue Oct 25 12:55:50 2005 Oct 25 17:48:01 ka6sox-office: ping? Oct 25 17:49:02 pong Oct 25 17:49:05 whee Oct 25 17:49:14 i have to interface two different clock domains Oct 25 17:49:17 wazzup Oct 25 17:49:29 and i thought you might be able to lend me a hand Oct 25 17:49:41 could be! Oct 25 17:50:18 i have a 50mhz clock for some logic, and 1.8432mhz for an uart Oct 25 17:50:21 the uart works fine Oct 25 17:50:42 the clocks aren't derived from each other Oct 25 17:50:50 yep Oct 25 17:51:01 so, what i thought was.. Oct 25 17:51:25 have two t flipflops Oct 25 17:51:33 one of them driven by clock 1, other one by clock 2 Oct 25 17:51:36 xor their Q outputs Oct 25 17:52:00 if that is 1, the 1-deep 8-bit fifo is in the 'full' state, otherwise it's 'empty' Oct 25 17:52:12 does that make sense? Oct 25 17:52:18 (i'm trying to solve this generically) Oct 25 17:53:02 you want to syncronize the 50mhz to 1.8432? Oct 25 17:53:16 i want the 50mhz logic to be able to send stuff over serial, and receive stuff Oct 25 17:53:22 so two ways Oct 25 17:54:31 give me 2 minutes here. Oct 25 17:54:34 np! Oct 25 17:54:43 today is my no sleep day Oct 25 17:54:45 :) Oct 25 17:54:56 ugh Oct 25 18:03:00 if you use overflow then it makes sense. Oct 25 18:03:06 (or a carry bit) Oct 25 18:03:07 'overflow' Oct 25 18:03:09 ? Oct 25 18:03:29 8bit counter with "overflow" or carry bit (so that you can chain them) Oct 25 18:04:08 well Oct 25 18:04:09 when I get home on my dev system I can look at the incantation. Oct 25 18:04:11 actually, i have two t-flipflops Oct 25 18:04:21 that will do. Oct 25 18:04:21 XORed they are the 'fifo status' indication (empty/full) Oct 25 18:04:24 and a separate 8 bit register Oct 25 18:04:34 that 8 bit register is a 'holding area' for TX/RX bytes Oct 25 18:04:36 just treat them as fifo's Oct 25 18:04:41 well Oct 25 18:04:43 my fifo is 1 deep Oct 25 18:05:33 same with mine...I should send you some code I did for handling a 50mhz bus talking to a ~712khz bus Oct 25 18:05:42 okay Oct 25 18:05:50 since it's not a totally crazy idea, i'll try to implement it Oct 25 18:05:50 and the busses were different sizes too. Oct 25 18:05:57 not crazy Oct 25 18:06:01 the two t flipflops was the easiest i could come up with Oct 25 18:06:04 different clock domains suck Oct 25 18:06:14 treat them separatly Oct 25 18:06:17 yeah Oct 25 18:06:18 and flag them Oct 25 18:06:25 if you want deeper fifos i guess you have to use gray coding or something Oct 25 18:06:46 so you would signal the TX buffer (to the uart) and say that you have a byte to send Oct 25 18:06:58 when its done is sends back the "done' flag Oct 25 18:07:03 yes, that's the idea Oct 25 18:07:12 the sender and receiver have an 'enable' Oct 25 18:07:17 and likewise for the RX Oct 25 18:07:23 50mhz clock up while enable active -> byte gets loaded into fifo Oct 25 18:07:34 you have to have "flow control" with that big of a clock difference" Oct 25 18:07:39 1.8432mhz clock up while enable active and fifo is full -> byte gets unloaded Oct 25 18:07:50 the XOR of the two t flipflops is the 'fifo full' signal Oct 25 18:07:52 exactly Oct 25 18:07:57 works for me! Oct 25 18:08:02 the TX keeps enable high until the load is successful Oct 25 18:08:04 okay! Oct 25 18:09:36 * lennert implements Oct 25 18:10:08 you send me your code too!! Oct 25 18:10:13 :) Oct 25 18:10:14 and i'll look too! Oct 25 18:10:20 i have a subversion tree that has all my crap in it Oct 25 18:10:32 not in a public place yet, i couldn't get svnweb to work Oct 25 18:10:43 (any recommendations for something like svnweb?) Oct 25 18:10:57 svk is what I'm looking at for s3projects. Oct 25 18:11:53 sovuk Oct 25 18:12:51 i'll have a look Oct 25 18:12:56 SVN::Web was dependency hell Oct 25 18:13:06 ka6sox-office: i have supervga pong now Oct 25 18:13:13 sweet! Oct 25 18:13:21 ka6sox-office: finally got the clock manager thingy in the spartan to work Oct 25 18:14:19 the best pixel clock rate for 640x480 turned out to be 50.000MHz times 17/24 :) Oct 25 18:14:37 i.e. 35.416MHz-ish Oct 25 18:15:32 fast. Oct 25 18:26:53 ka6sox-office: for 1024x768 in 80Hz it's about 77MHz Oct 25 18:27:56 ka6sox-office: my vt100 emulator calculates pixels 8 at a time so it doesn't really matter Oct 25 18:28:05 ka6sox-office: (vt100 emulator's display part is done) Oct 25 18:35:48 currently fixing Vservers...so I'll be a bit :) Oct 25 18:36:20 <[g2]> lennert are you using the block ram at all ? Oct 25 18:36:33 [g2]: for the display buffer, yes Oct 25 18:36:44 [g2]: and for font storage Oct 25 18:37:00 <[g2]> and the UART FIFO ? :) Oct 25 18:37:08 uart fifo is just a bunch of flipflops Oct 25 18:37:12 no block ram Oct 25 18:37:31 <[g2]> I'm suggesting a small 8 / 16 byte fifo Oct 25 18:37:54 <[g2]> ring buffer with a 3 bit or 4 bit register Oct 25 18:37:57 that can in theory be added fairly easily, yes Oct 25 18:38:15 it's mostly useful if you want to interface it with a cpu core Oct 25 18:38:24 (which is what i'll be doing on the virtex board :) Oct 25 18:39:04 <[g2]> I'd think you'd want a wider interface for the virtex cpu Oct 25 18:39:19 it's a win to be 16450-compatible Oct 25 18:39:35 <[g2]> 16550 ? Oct 25 18:39:47 or that Oct 25 18:39:51 anything 8250-derivative Oct 25 18:40:10 <[g2]> well the 450s and 550 have 14 byte fifo iirc Oct 25 18:40:21 <[g2]> and thresholding on the int generation Oct 25 18:40:28 could be, yes Oct 25 18:40:48 response times for a cpu core are more variable Oct 25 18:41:03 for what i'm using it for right now, response time is not an issue and thus a single byte fifo suffices Oct 25 18:41:41 <[g2]> oh you're kicking ass, I'm just wondering where you are headed :) Oct 25 18:41:58 <[g2]> and wondering what the real underlying issues are Oct 25 18:42:33 [g2]: other people are doing good work on the jtag front but i'll be trying that anyway, just for fun :) Oct 25 18:43:02 <[g2]> well there's no shortage of good work to be done in my mind Oct 25 18:43:09 <[g2]> the more the merrier Oct 25 18:43:17 always enough asses to kick, you mean? Oct 25 18:43:19 <[g2]> doing good work that is Oct 25 18:44:01 everyone here is kicking major ass Oct 25 18:45:08 <[g2]> IMHO we're in the final stretch of the open boxen Oct 25 18:45:55 <[g2]> this JTAG piece is the last key and the JTAG debugging is the icing on the cake Oct 25 18:47:28 [g2], but the ixp4xx gate mask is not open sourced :) Oct 25 18:47:48 <[g2]> heh Oct 25 18:48:09 some really has to do the open-source LEG Oct 25 18:48:12 s/some/someone/ Oct 25 18:48:13 <[g2]> there's a guy around here that does X-rays for $25-30 Oct 25 18:48:29 xrays of chips? Oct 25 18:48:41 <[g2]> it's an x-ray machine Oct 25 18:49:00 not sure how useful that is for chips Oct 25 18:49:02 <[g2]> dunno the rs Oct 25 18:49:06 <[g2]> dunno the res Oct 25 18:49:27 in any case, we don't need to look at intel's stuff, we'll just design something better :) Oct 25 18:49:48 <[g2]> did you see the PPC announcement ? Oct 25 18:50:01 nope/ Oct 25 18:50:47 <[g2]> http://www.linuxdevices.com/news/NS7626583293.html Oct 25 18:51:03 <[g2]> won't be till late next year Oct 25 18:51:14 <[g2]> but they've got a good idea Oct 25 18:52:03 24 serdes! Oct 25 18:52:45 <[g2]> lennert wets pants Oct 25 18:53:07 i want an fpga with 24 gige ethernet ports Oct 25 18:53:19 (at an affordable price) Oct 25 18:54:19 <[g2]> I'd think a PC with 2 10G PCI-E cards would be close enough Oct 25 18:54:33 not as fun Oct 25 18:54:39 nor as powerful Oct 25 18:54:56 <[g2]> but _way_ cheaper Oct 25 18:55:07 <[g2]> that's the affordable part Oct 25 18:55:15 sure, but it's not as if i have a real need to do 25 gigabit routing Oct 25 18:55:23 (at the lowest possible cost) Oct 25 18:55:28 just want more toys to play with Oct 25 18:55:32 toys toys toys Oct 25 18:57:19 okay, time to go to work Oct 25 19:05:03 <[g2]> :) Oct 25 19:05:19 <[g2]> so do you pull an all-night once a week ? Oct 25 19:14:08 * dyoung-web looks for wanker repellant. Oct 25 19:36:43 [g2]: kind of, yeah Oct 25 19:36:51 dyoung-web: whom are you trying to repell? Oct 25 19:36:59 [g2]: sometimes twice :) Oct 25 19:37:35 [g2]: today i have to pick up wife from the airport at 9am, which is a time that i haven't been awake at for a long long time now Oct 25 19:37:55 [g2]: and i forgot to do some stuff at work, so i decided to go back to work (at 4am :) and just stay up Oct 25 19:40:33 <[g2]> lennert well godspeed and safe driving Oct 25 19:40:49 okay, that one was my fault. Oct 25 19:40:58 "wheres my prompt" Oct 25 19:41:07 because I forgot to install their shell. :/ Oct 25 19:41:34 <[g2]> heh Oct 25 19:41:48 [g2]: you can't kill much when you're by bicycle Oct 25 19:42:06 [g2]: i don't even have a car.. Oct 25 19:42:14 wear lots of blinky lights? Oct 25 19:42:32 <[g2]> are there two seats on the bike ? Oct 25 19:42:51 * [g2] thinks it'd get cold in the winter Oct 25 19:43:59 [g2]: one seat :) Oct 25 19:44:24 [g2]: well, we're used to that here.. anyway, it never gets really cold here, we just have the North Sea wind to deal with Oct 25 19:47:16 <[g2]> ahh... newlyweds :) Oct 25 19:50:45 okay lennert: I'm home. Oct 25 19:51:00 where should I look for your files? Oct 25 19:57:19 ka6sox-away: i don't actually have them in a publicly accessible place yet Oct 25 19:57:31 ka6sox-away: i can send you a tarball of my current svn tree Oct 25 19:58:38 ka6sox-away: after i finish mutilating this 'ere windows 2000 server, that is Oct 25 20:01:45 lennert cool! Oct 25 20:01:49 I'll add it :) Oct 25 20:05:33 has anyone spoken to dyoung-web? Oct 25 20:07:47 okay, let me get to that Oct 25 20:10:07 oh this is so damn VILE Oct 25 20:10:30 what i'm doing to this windows box is beyond words.. i love it Oct 25 20:15:41 ow ow ow owwwww Oct 25 21:29:12 ka6sox-away: http://www.wantstofly.org/~buytenh/vhdl/fifo.vhd Oct 25 21:29:24 ka6sox-away: i didn't try synthesizing it yet, but does it look approx. okay? Oct 25 21:31:33 hang on, reorganising Oct 25 21:32:15 I never worried about the states...just used flags.... Oct 25 21:32:34 they are flags here.. Oct 25 21:32:45 when I wrote to the fifo I just told the next process to start and when it was finished just signal Oct 25 21:32:47 but a_state='0' b_state='0' and a_state='1' b_state='1' both mean empty Oct 25 21:32:53 I agree. Oct 25 21:33:13 but its much simpler logic to just signal when thru. Oct 25 21:33:33 can you reload? Oct 25 21:33:39 yep Oct 25 21:34:31 there ya go...much easier to read. Oct 25 21:34:44 try synthesizing this and see where it blows up :) Oct 25 21:34:50 (doesnt' look like it will) Oct 25 21:35:25 yeah, i'll test Oct 25 21:35:40 i'll use slide switches as inputs and leds as outputs Oct 25 21:36:00 ah....similar to what you were going to have dyoung do? Oct 25 21:36:01 :) Oct 25 21:36:07 sssssh :) Oct 25 21:36:13 he he Oct 25 21:36:25 hahahahahaha Oct 25 21:37:00 psssst...dyoung-web: use this as a starting place...(don't tell lennert) Oct 25 21:37:28 (i don't care if dyoung copies someone else's vhdl, 'cause that way he'll also learn how it's done) Oct 25 21:37:58 yes but I want proper semaphores :) Oct 25 21:40:28 ka6sox-away: how do you mean? Oct 25 21:41:09 j/k Oct 25 21:41:30 when you reorged it became clear... :) Oct 25 21:41:37 hehe Oct 25 21:41:52 the solution wasn't clear to me until i implemented it Oct 25 21:45:54 'tis almost time for me to go Oct 25 21:46:57 go...lets see...this is a no sleep night? Oct 25 21:47:00 7am? Oct 25 21:47:06 yeah Oct 25 21:47:19 have to pick up other half from the airport round 9 Oct 25 21:47:30 oh yeah...wednesday! w00t Oct 25 21:47:50 :) Oct 25 21:47:57 double you zero zero tee Oct 25 21:51:34 ka6sox-away: i think there's still a problem if wr_state toggles before rd_port does Oct 25 21:52:13 ka6sox-away: i think wr_state should be delayed one write clock Oct 25 21:52:49 it can become metastable if you are looking at rising_edge for both. Oct 25 21:52:58 yes Oct 25 21:53:05 that's the case i'm worried about Oct 25 21:53:36 you can always look at falling edge too! Oct 25 21:53:41 but well.. that'd reduce the performance of the fifo to half.. Oct 25 21:53:49 ka6sox-away: falling edge where? Oct 25 21:54:09 ka6sox-away: you want wr_state to activate on the falling edge? Oct 25 21:54:23 ka6sox-away: what if there is a valid falling edge _before_ the rising edge? Oct 25 21:54:50 rd_state xor wr_state can go to zero just after a rising wr_clock edge Oct 25 21:55:10 in which case the falling edge would set wr_state, and the next rising edge would set rd_port Oct 25 21:55:14 doesnt' matter you are only looking at level. Oct 25 21:55:36 ? Oct 25 21:56:05 woosh.. that's the sound of ka6sox-away going over my head Oct 25 21:56:11 distracted here.... Oct 25 21:56:15 np Oct 25 21:56:16 1 minute... Oct 25 22:05:14 i'm thinking just to pipeline 'rd_state xor wr_state' in the reader Oct 25 22:05:23 signal blah : std_logic; Oct 25 22:05:28 blah <= rd_state xor wr_state; Oct 25 22:05:40 if rising_edge(rd_clock) and rd_enable = '1' and blah = '1' Oct 25 22:05:41 ... Oct 25 22:06:12 hmmmm Oct 25 22:06:27 i should also export "rd_state xor wr_state" as fifo_full :P Oct 25 22:06:37 you could. Oct 25 22:08:08 new version uploaded that exports fifo_full Oct 25 22:08:33 whoops, should have been an inout Oct 25 22:08:35 okay I need to take care of my wife. Oct 25 22:08:49 signals dont care Oct 25 22:08:59 okay Oct 25 22:09:05 i'll run soon, so catch you later Oct 25 22:09:08 thanks for your help Oct 25 22:10:19 np Oct 25 22:11:08 new version uploaded Oct 25 22:11:15 this delays fifo_full by one read clock Oct 25 22:11:53 will stare at it a bit more on the train Oct 25 22:28:07 ka6sox-away: this version is kickass Oct 25 22:33:14 cool! Oct 25 23:25:18 morning Oct 25 23:25:27 ya..I am always here :) Oct 25 23:25:38 except when I'm not. Oct 25 23:25:56 maybe the PC is right beside Your bed :-) Oct 25 23:31:28 heh, mine is - but still there are hours when i simply sleep Oct 25 23:31:59 me too...but its about my bed time here GMT-7 Oct 25 23:32:33 this is my lappy and thats where it spends a lot of time. **** ENDING LOGGING AT Wed Oct 26 02:59:58 2005