**** BEGIN LOGGING AT Thu Nov 17 02:59:56 2005 Nov 17 04:53:04 how many protocol over JTAG exist ? like EJTAG for MIPS Nov 17 05:11:23 key2: i wouldn't call EJTAG a "protocol" Nov 17 05:11:58 it has no meaning for anything else than mips debugging Nov 17 05:12:20 same goes for ARM, there's a specific way of debugging for arm7/9, 10, 11, cortex Nov 17 05:12:34 xscale is a different story, too Nov 17 05:12:44 powerpc has it's own way of debugging Nov 17 05:14:17 then there's pld in-system programming Nov 17 05:14:35 again, this differs among vendors, chip families Nov 17 05:15:29 there's a standard (ieee 1532) that's meant to unify isp through jtag for plds Nov 17 05:28:58 ok Nov 17 05:29:11 and Openjtag is meant to make a tool for all of them ? Nov 17 05:37:41 you "just" have to define a jtag interface that's high-level enough to offload all the latency-sensitive stuff to the hardware Nov 17 05:39:23 vmaster: how is your jtag built into fpga doin Nov 17 05:39:23 ? Nov 17 05:39:38 haven't had time to work on that lately Nov 17 05:42:59 basically all it could do is a read/write/readwrite ? Nov 17 05:45:39 that's the cpld interface i've been working on, yes Nov 17 05:45:53 it's meant to interface with a EPP parallel port, so latency isn't an issue Nov 17 05:46:30 ok but basically you just say do a Write throught the EPP and it does it ? Nov 17 05:46:39 why not using a uC Nov 17 05:47:29 it's not necessary for the parallel port - a usb device would have to use a uC or pfga Nov 17 05:47:32 *fpga Nov 17 14:59:49 ka6sox-office: any virtex2 pro experience? Nov 17 15:00:07 ka6sox-office: how can it be that the DCUADDRACK signal on the ppc405 PLB is asserted on the same cycle as the DCUREQUEST signal? Nov 17 15:07:00 lennert, in about 3 weeks I'll know that...after my course. Nov 17 15:11:01 okay Nov 17 15:11:09 (i'll know it before you :) Nov 17 15:12:07 it just doesn't make any sense, you cannot ack a request on the same clock cycle Nov 17 15:24:39 the ppc405 is actually quite easy to understand Nov 17 15:40:16 lennert: the ppc405 is the powerpc ? Nov 17 16:38:13 it _seems_ like you can't implement an SMP system with the two ppc405 cores in the v2pro because the PLB isn't cache coherent.. Nov 17 16:40:24 lennert: so it's possible to put a linux for PPC in the virtex2pro ? Nov 17 17:02:38 * lennert does the virtex2 pro dance of joy Nov 17 17:03:22 lennert ? Nov 17 18:13:43 * lennert like the ppc instruction set Nov 17 18:13:55 it's even more regular than ARM's Nov 17 20:51:08 <[g2]> quite orthogonal Nov 17 20:52:24 <[g2]> lennert so what was the dance of joy for ? SMP ? Nov 17 20:53:20 <[g2]> or are you just happy with your new toy Nov 18 00:17:46 because i think i understood the most important parts of the ppc ref guide Nov 18 00:18:07 i'm on a mission to replace all the evil proprietary xilinx ip with free variants... **** ENDING LOGGING AT Fri Nov 18 03:00:04 2005