**** BEGIN LOGGING AT Sun Dec 18 02:59:56 2005
Dec 18 07:25:38 <lennert> there's no way to have xst infer a DDR MUX, right?
Dec 18 07:25:45 <lennert> at least, i can't seem to get it to do that
Dec 18 07:30:12 <vmaster_> heh, guess you're the only one in this channel who would know what to do with a DDR MUX ;)
Dec 18 07:32:23 <lennert> hmm :)
Dec 18 08:57:29 <lennert> btw, in case anyone reads the hoplite JBits tutorial, the diagrams are wrong in places
Dec 18 08:57:56 <lennert> caveat lector
Dec 18 09:05:03 <[g2]> lennert R0X0Rz
Dec 18 09:05:11 <[g2]> congrats btw
Dec 18 09:05:48 <[g2]> lennert so you're looking to do IP routing witn FPGAs for speed ?
Dec 18 09:22:09 <lennert> hehe
Dec 18 09:22:21 <lennert> well, that's one thing i would eventually like to look into
Dec 18 09:22:35 <lennert> not for speed but just for fun
Dec 18 09:23:09 <lennert> it's quick enough on the ixp
Dec 18 09:24:45 <[g2]> the routing is not quick enough on the ixp ?  don't the 2350s run faster ?
Dec 18 09:25:14 <[g2]> A CAM chip is the answer for routing table lookups right ?
Dec 18 09:25:28 <lennert> the routing _is_ quick enough on the ixps
Dec 18 09:25:46 <lennert> you can pipeline memory references so you can do pretty crazy stuff and still get wire speed performance
Dec 18 09:25:47 <[g2]> ah
Dec 18 09:26:22 <lennert> i don't see the point of doing it in an fpga (which just complicates things) apart from making things hard on yourself (and at times i like to make things hard on myself)
Dec 18 09:27:29 <[g2]> we did ingress and partial egress in FPGA several years ago
Dec 18 09:28:02 <[g2]> we had about a dozen high-end FPGA guys and I was the lone NP guys with the Vitesse
Dec 18 09:28:41 <lennert> there's an fpga between the gige interfaces and the ixp2400 on the radisys enp2611 board, and you can use it for some processing, but to do everything in the fpga seems a bit of a bad idea especially since the ixps are relatively cheap
Dec 18 09:29:07 <[g2]> well this was 5+ years ago
Dec 18 09:29:25 <lennert> admittedly, xilinx's high-end fpgas (the ones that cost $12k) have a bit more high-speed transceivers than the ixps do
Dec 18 09:29:36 <[g2]> We had multipel GigE in the chassis and supported 1Million subs
Dec 18 09:32:01 <lennert> at what company was that?
Dec 18 09:32:32 <[g2]> a startup they spend 60M over several years
Dec 18 09:32:42 <lennert> any product? :)
Dec 18 09:32:50 <[g2]> product was all done and ready
Dec 18 09:32:57 <[g2]> no market :(
Dec 18 09:33:05 <lennert> ah
Dec 18 09:33:13 <[g2]> 3G never really arrived
Dec 18 09:33:15 <lennert> "it's the market's fault!" :)
Dec 18 09:33:21 <lennert> "3G" ?
Dec 18 09:33:29 <lennert> you mean, as in UMTS/W-CDMA 3G?
Dec 18 09:33:30 <[g2]> 3G wireless
Dec 18 09:33:33 <lennert> right
Dec 18 09:33:33 <[g2]> nod
Dec 18 09:33:37 <lennert> well
Dec 18 09:33:40 <lennert> it's slowly arriving now :)
Dec 18 09:33:52 * lennert has a 3G phone
Dec 18 09:33:55 <[g2]> it's been slowly arriving for years :)
Dec 18 09:34:40 <lennert> GSM protocols are really baroque
Dec 18 09:34:47 <[g2]> heh
Dec 18 09:35:35 <lennert> another project i've been thinking about is a GSM jammer :)
Dec 18 09:36:12 <[g2]> I think ppl already sell them.. for theaters etc.
Dec 18 09:36:22 <lennert> yeah, i mean, not as a commercial product
Dec 18 09:36:32 <lennert> as a kind of hobby thing
Dec 18 09:36:36 <[g2]> Ah....
Dec 18 09:36:46 <[g2]> I'd go for the SDR
Dec 18 09:36:55 <[g2]> then you could handle it all :)
Dec 18 09:37:06 <[g2]> the _soft_ BTS or whatever
Dec 18 09:37:07 <lennert> yeah
Dec 18 09:37:14 <lennert> software defined radio
Dec 18 09:37:23 <lennert> base transceiver station? :)
Dec 18 09:37:28 <[g2]> that's something the FPGA would be helpful with
Dec 18 09:37:33 <[g2]> yeah
Dec 18 09:37:36 <lennert> just generate white noise and mix it with the appropriate carrier
Dec 18 09:37:40 <lennert> indeed
Dec 18 09:37:57 <lennert> and surprise surprise, my virtex board has a triple 150MSPS 8bit D/A converter
Dec 18 09:38:20 <lennert> it's really a VGA DAC, but you don't have to use it for VGA, eh? :)
Dec 18 09:38:30 <lennert> 3x75MHz of bandwidth is plenty
Dec 18 09:39:10 <lennert> the problem is only that i'm generating ideas faster than i can implement them.. :)
Dec 18 09:39:21 <[g2]> welcome to the club :)
Dec 18 09:39:57 <[g2]> so is the DDR interface on the Big Vertex board or can the S3 do that too ?
Dec 18 09:40:19 <[g2]> S3e maybe ?
Dec 18 09:41:36 <lennert> the s3 also has ddr
Dec 18 09:42:00 <lennert> i need the ddr mux for accessing the dual set of flipflops in every IOB
Dec 18 09:42:17 <lennert> (each iob has two {input,output,tristate} flipflops, where the second set is only used for ddr)
Dec 18 09:42:42 <[g2]> is that the on chip Block RAM ?
Dec 18 09:42:48 <lennert> nope
Dec 18 09:42:49 <[g2]> not off chip DDR memory
Dec 18 09:42:52 <lennert> IOB = input/output block
Dec 18 09:43:04 <lennert> the bits of logic that connect the pins to the logic inside the chip
Dec 18 09:43:15 <[g2]> right
Dec 18 09:43:26 <lennert> check out the sp3 datasheet (ds099.pdf) page 9
Dec 18 09:43:38 <lennert> that sort-of shows the IOB structure (but is incomplete)
Dec 18 09:45:21 <lennert> the hoplite JBits tutorial has a floorplan on p18 but that one's incorrect, even
Dec 18 09:50:09 <[g2]> so one can actually to DDR memory terminations with S3 ?
Dec 18 09:50:30 <[g2]> I guess the DCI help with terminations
Dec 18 09:50:51 <lennert> you can hook an s3 up to ddr ram, yeah
Dec 18 09:51:00 <lennert> what signaling do they use again.. sstl?
Dec 18 09:51:20 <[g2]> dunno
Dec 18 09:51:43 <[g2]> so many signalling types (and so many protocols) and so little time :)
Dec 18 09:51:48 <lennert> yeah :)
Dec 18 09:52:30 <lennert> the way the signaling standards are mapped into bits makes no sense at all
Dec 18 09:53:26 <lennert> some signaling standard choices produce identical .bit files, too
Dec 18 09:53:36 <[g2]> I think it's half history from the evolution of product lines and half Enlightenment
Dec 18 09:53:59 <lennert> LVTTL 2mA and LVCMOS33 2mA produce the exact same bit pattern, by the way
Dec 18 09:54:03 <lennert> s/by the way/for example/
Dec 18 09:54:15 <lennert> so if you have a .bit file, you can't be 100% sure what signaling standards have been used
Dec 18 09:54:27 <lennert> LVCMOS25 6mA is identical to LVCMOS33 8mA
Dec 18 09:54:50 <lennert> LVTTL 4mA and LVCMOS33 4mA are identical
Dec 18 09:54:51 <lennert> etc
Dec 18 09:55:17 <lennert> i think the bit patterns control individual transistors
Dec 18 09:55:39 <lennert> but i can't really guess how they are connected just from the bit patterns
Dec 18 09:56:09 <lennert> dci is another mystery for now
Dec 18 09:57:10 <[g2]> yeah I've got tons to learn in the EE dept. too
Dec 18 09:57:19 <lennert> http://svn.wantstofly.org/vhdl/utils/decode_bit.c dumps .bit files in hex format, frame-by-frame
Dec 18 09:57:25 <lennert> [g2]: yeah... :-/
Dec 18 09:59:55 <[g2]> lennert the other day you suggested just writing to the GPIO register in a big loop to measure the timing right ?
Dec 18 10:00:00 <lennert> yeah
Dec 18 10:00:08 <lennert> i found the datasheet for the southbridge on my via epia board
Dec 18 10:00:12 <lennert> (which has 8 exposed GPIOs)
Dec 18 10:00:26 <lennert> i still have to look into that though
Dec 18 10:00:38 <[g2]> I wanted to try the same thing on the Loft
Dec 18 10:00:52 <lennert> okay
Dec 18 10:00:59 <[g2]> I'll have to dig up the assembler instructions
Dec 18 10:01:02 <lennert> so you want me to write the loop so that you can run it? :)
Dec 18 10:01:11 <lennert> you don't really have to do it in assembler
Dec 18 10:01:32 <lennert> let me hack that up
Dec 18 10:02:22 <[g2]> C8004000  is the address of the GPIOs
Dec 18 10:02:43 <lennert> yeah
Dec 18 10:02:48 <lennert> IXP4XX_GPIO_GPOUTR is at offset 0x00 from that
Dec 18 10:03:07 <[g2]> page 395 in the ixp42x Dev manual
Dec 18 10:03:21 <lennert> or include/asm/arch-ixp4xx/ixp4xx-regs.h :D
Dec 18 10:05:53 <lennert> ok, this should work
Dec 18 10:07:18 <lennert> http://www.wantstofly.org/~buytenh/ixp4xx_gpio_twiddle.c
Dec 18 10:07:48 <lennert> i've commented out the for-loop
Dec 18 10:07:54 <lennert> can you run that to see if it gives sane results?
Dec 18 10:09:12 <[g2]> sure
Dec 18 10:10:23 <[g2]> we really want to be reading from 0xc8004008 though
Dec 18 10:10:32 <[g2]> 0 offset is for the config
Dec 18 10:11:21 <[g2]> gpio[2]
Dec 18 10:11:32 <lennert> offset 0x00 is IXP4XX_GPIO_GPOUTR
Dec 18 10:11:37 <lennert> and gpio_line_set writes to IXP4XX_GPIO_GPOUTR
Dec 18 10:12:04 <lennert> offset 0x08 is the input register, it says here
Dec 18 10:12:06 <[g2]> right and that sets up whether the pins are Input/Tristate or Output
Dec 18 10:12:24 <[g2]> right and 0x8 are the input values
Dec 18 10:12:27 <lennert> no, that's gpio_line_config
Dec 18 10:12:43 <lennert> input/output is set by IXP4XX_GPIO_GPOER, which is at offset 0x04
Dec 18 10:12:50 <lennert> either that or the linux defines are all wrong :)
Dec 18 10:13:30 <[g2]> right
Dec 18 10:13:37 <[g2]> 0x0 is the output
Dec 18 10:13:46 <[g2]> 0x4 is the output enbale
Dec 18 10:13:52 <[g2]> 0x8 is the input values
Dec 18 10:13:55 <lennert> yeah
Dec 18 10:14:10 <[g2]> so your code is correct for writing output
Dec 18 10:14:10 <lennert> confusing intel docs, i bet
Dec 18 10:14:15 <lennert> yeah
Dec 18 10:14:23 <[g2]> but you are reading
Dec 18 10:14:27 <lennert> i read it once
Dec 18 10:14:33 <[g2]> nod
Dec 18 10:14:38 <lennert> and then write it a million times
Dec 18 10:14:46 <lennert> i read it because i want to make sure i don't fsck up the machine :)
Dec 18 10:15:00 <lennert> it's allowed to read from the output register, no?
Dec 18 10:15:10 <[g2]> nod
Dec 18 10:15:13 <lennert> (it doesn't say in the header file)
Dec 18 10:15:23 <lennert> okay
Dec 18 10:15:26 <lennert> so so so
Dec 18 10:15:29 <lennert> how fast is it? :)
Dec 18 10:15:38 <[g2]> but we want to just write a value that drives the lower pins
Dec 18 10:15:52 <lennert> well, for a timing test it doesn't matter what you write, does it?
Dec 18 10:16:11 <lennert> if you have a 'scope you can toggle a gpio and check the frequency
Dec 18 10:16:14 <[g2]> yeah as it will drive some of those lines
Dec 18 10:16:30 <lennert> but how many cycles the gpio write takes doesn't depend on what you write
Dec 18 10:16:47 <[g2]> no but I'm saying the hw may be unhappy
Dec 18 10:16:49 <lennert> the bulk (99.999%) of the overhead is getting the write to the other side of the chip
Dec 18 10:16:55 <lennert> well
Dec 18 10:17:08 <lennert> we're only writing what was already there, don't we?
Dec 18 10:17:20 <lennert> and if a gpio if configured as input, writing to the output register shouldn't change that?
Dec 18 10:17:41 <[g2]> Ok... that's fair.... 
Dec 18 10:17:55 <lennert> the ixp4xx doesn't have a "write a 1 to clear" or "write 1 to set" register.. else i would have used that and written just zeroes to it
Dec 18 10:20:32 <lennert> so so so
Dec 18 10:20:33 <lennert> how fast is it? :)
Dec 18 10:20:50 <lennert> (or did it blow up?)
Dec 18 10:22:00 <[g2]> setting up now
Dec 18 10:31:30 <[g2]> booting almost there :)
Dec 18 10:31:46 <lennert> :)
Dec 18 10:32:35 <[g2]> I've been playing with bootp
Dec 18 10:32:43 <[g2]> and the current setup is for that
Dec 18 10:33:35 <[g2]> Ok it runs
Dec 18 10:35:53 <[g2]> Ok
Dec 18 10:36:50 <lennert> so so so
Dec 18 10:36:51 <[g2]> .05s for the 1M version
Dec 18 10:36:53 <lennert> how fast is it? :)
Dec 18 10:37:05 <lennert> how fast is the CPU?
Dec 18 10:37:10 <[g2]> 533
Dec 18 10:37:22 <lennert> that's kind of impossibly fast
Dec 18 10:37:27 <lennert> can you make it 16M ?
Dec 18 10:37:29 <[g2]> it takes .01 for the program
Dec 18 10:37:34 <[g2]> sure
Dec 18 10:37:55 <lennert> you're sure you uncommented the for-loop? :)
Dec 18 10:37:56 <lennert> try 16777216
Dec 18 10:38:33 <[g2]> I did 16* that number
Dec 18 10:38:37 <[g2]> literally 16*
Dec 18 10:38:39 <lennert> that'll work
Dec 18 10:38:41 <lennert> 16*1048576 = 16777216
Dec 18 10:39:05 <[g2]> I'm sure the compiler optimized it out :) preprocessor anyway
Dec 18 10:39:11 <lennert> well, no
Dec 18 10:39:15 <lennert> cause it's a volatile pointer
Dec 18 10:39:20 <lennert> it's not allowed to optimise it away
Dec 18 10:39:30 <[g2]> I meant the 16*
Dec 18 10:39:34 <lennert> oooh, yeah
Dec 18 10:39:36 <lennert> yeah, sure :)
Dec 18 10:39:50 <[g2]> .760s
Dec 18 10:39:53 <lennert> compiler will do that for you
Dec 18 10:40:07 <lennert> hmmm
Dec 18 10:40:20 <lennert> can you try 1024M loops?
Dec 18 10:40:32 <[g2]> easy peasy :)
Dec 18 10:40:34 <lennert> (1024*1048576 = 1073741824)
Dec 18 10:41:03 <lennert> if the 0.760s figure is accurate, you can bitbang the gpios at 10MHz
Dec 18 10:41:14 <Trou> hi guys, i'm looking for EJTAG v2.0 spec, does anyone have them ?
Dec 18 10:41:28 <lennert> after that, try doing 16M reads in a loop (instead of writes)
Dec 18 10:41:31 <lennert> Trou: sorry, nope
Dec 18 10:41:50 <[g2]> I don't have one but the #openwrt guys play with EJTAG
Dec 18 10:42:02 <Trou> yup, already asked there
Dec 18 10:42:17 <Trou> looks like noone has them :(
Dec 18 10:42:38 <[g2]> there were a couple guys doing EJTAG
Dec 18 10:42:44 <[g2]> I'm not sure who
Dec 18 10:42:49 <Trou> yeah, lightbulb mainly
Dec 18 10:43:08 <Trou> but he wasn't seen there since almost a month and doesn't answer to mails :x
Dec 18 10:43:09 <[g2]> and some software are written up on the sveasoft forum
Dec 18 10:43:26 <[g2]> yeah lightbulb was doing that a year+ ago
Dec 18 10:43:29 <vmaster> key2 talked a lot about ejtag
Dec 18 10:43:29 <Trou> ah ?
Dec 18 10:43:39 <Trou> i'm going to check the sveasoft forum
Dec 18 10:43:46 <vmaster> isn't the ejtag specs available from mips?
Dec 18 10:43:56 <[g2]> 48.390s for 1024M
Dec 18 10:43:58 <Trou> it is, but only v 3.10
Dec 18 10:44:05 <Trou> i found 2.60 on google but no 2.0
Dec 18 10:44:31 <lennert> [g2]: ok, so you can bitbang at about 11MHz
Dec 18 10:44:44 <lennert> [g2]: can you try reads now?
Dec 18 10:44:58 <vmaster> try two writes and one read
Dec 18 10:45:09 <[g2]> sure x = gpio[2] ?
Dec 18 10:45:20 <lennert> [g2]: for example
Dec 18 10:47:02 <Trou> no luck on sveasoft, thanks anyway :)
Dec 18 10:48:10 <[g2]> reads appear to be way slower or there's an error
Dec 18 10:48:17 <lennert> reads _are_ way slower
Dec 18 10:48:24 <lennert> 20x, easily
Dec 18 10:48:36 <lennert> since the chip stalls on them
Dec 18 10:49:07 <[g2]> so then the writes problaby don't really run at that rate then
Dec 18 10:49:31 <lennert> they do..
Dec 18 10:49:54 <lennert> i'm pretty sure you'll see a 11MHz square wave if you toggle one of the gpios
Dec 18 10:49:55 <[g2]> 2m25.160s
Dec 18 10:50:11 <lennert> [g2]: for 16M reads?  or 16M (write+write+read)s ?
Dec 18 10:50:18 <[g2]> 1024M
Dec 18 10:50:29 <lennert> 1024M reads or 1024M (write+write+reads)s ?
Dec 18 10:50:42 <[g2]> just read
Dec 18 10:50:49 <[g2]> x = gpio[2]
Dec 18 10:50:55 <lennert> ok
Dec 18 10:51:01 <lennert> 7396953 per second
Dec 18 10:51:21 <lennert> so reads are 72 cycles each and writes are 26 cycles each
Dec 18 10:51:30 <lennert> still pretty good
Dec 18 10:51:49 <lennert> so write+write+read is 124 cycles
Dec 18 10:51:55 <[g2]> well if we can really drive at 11M that's ok for programming :)
Dec 18 10:52:02 <lennert> 4.2MHz if you are shifting something out
Dec 18 10:52:12 <lennert> and 10.25MHz if you're not shifting anything out
Dec 18 10:52:22 <lennert> give or take
Dec 18 10:52:26 <lennert> not bad at all
Dec 18 10:54:50 <[g2]> THX
Dec 18 10:54:58 <[g2]> for the program
Dec 18 10:55:04 <[g2]> and the help :)
Dec 18 10:55:06 <lennert> np
Dec 18 10:55:19 <[g2]> I've got 5 GPIOs on the Loft
Dec 18 10:55:24 <lennert> now it's up to you to hack up a jtag daughterboard :)
Dec 18 10:55:41 <[g2]> I don't need one
Dec 18 10:55:51 <[g2]> It's 5  or 6 wires
Dec 18 10:55:59 <lennert> yeah
Dec 18 10:56:06 <[g2]> plus tying the ground together
Dec 18 10:56:14 <lennert> are they at the right level though?
Dec 18 10:56:20 <lennert> (what level is jtag, anyway?)
Dec 18 10:56:24 <lennert> (3.3?  2.5?)
Dec 18 10:56:30 <[g2]> I think it's 3.3
Dec 18 10:56:34 <[g2]> I'll have to check
Dec 18 10:56:53 <[g2]> but I should be able to have one Loft JTAG another
Dec 18 10:57:08 <[g2]> if I've got enogh pins with 5
Dec 18 10:58:10 <lennert> TCK, TMS, IN, OUT and maybe TRST
Dec 18 10:58:47 <lennert> s/IN/TDI/;s/OUT/TDO/ of course
Dec 18 10:58:57 <[g2]> of course :)
Dec 18 10:59:38 <[g2]> I could probably cut the SCL line for the I2C chips and pick up 2 more (SDA and SCL) if need bot
Dec 18 10:59:41 <[g2]> s/bot/be/
Dec 18 11:00:00 <lennert> 5 should be enough
Dec 18 11:00:13 <[g2]> that's sweet
Dec 18 11:01:00 <[g2]> I've to a 6 pin flying lead from DigilentInc that plugs onto the board header for $4.95
Dec 18 11:01:19 <[g2]> all 5 pins are GPIO 0-4
Dec 18 11:01:55 <[g2]> well wonderful news and great work
Dec 18 11:02:11 <[g2]> I've got to get lunch (the family is eating)
Dec 18 11:02:17 <[g2]> THX again
Dec 18 11:02:22 <lennert> have a nice meal
Dec 18 11:02:26 <lennert> talk to you when you get back :)
Dec 18 11:12:01 <vmaster> using a 533mhz cpu to do jtag bitbanging is _cruel_ ;)
Dec 18 11:13:23 <vmaster> a 60mhz lpc (arm7) is faster - 2 cycles per read or write
Dec 18 11:14:33 <lennert> GPIOs are integrated into the main datapath?
Dec 18 11:18:03 <lennert> yeah, it's a bit of a rude solution :)
Dec 18 11:19:28 <[g2]> vmaster the lpc (Philips) run @ 60Mhz and can do GPIO in 2 instructions ?
Dec 18 11:20:13 <vmaster> yes, the lpcs run at 60mhz and do one gpio access every two cycles
Dec 18 11:20:28 <vmaster> i measured 15mhz when toggling one bit
Dec 18 11:20:31 <[g2]> how many GPIOs are there
Dec 18 11:20:35 <vmaster> dozens
Dec 18 11:20:49 <vmaster> depending on the chip and package
Dec 18 11:20:50 <[g2]> what do they cost ?
Dec 18 11:20:56 <[g2]> any URLs ?
Dec 18 11:21:06 <vmaster> olimex has a lot of lpc boards
Dec 18 11:21:10 <vmaster> olimex.com
Dec 18 11:21:28 <vmaster> there's even one with a usb 2.0 device port, iirc
Dec 18 11:23:42 <vmaster> what i don't know is how much help the usb device port requires from the processor, like servicing interrupts and so on
Dec 18 11:24:07 <[g2]> thx
Dec 18 11:24:10 <[g2]> bbiab
Dec 18 11:30:21 <vmaster> A device with a very versatile synchronous serial interface would be nice - something that would allow you offload the serializing - it's just 'expensive' doing that in software
Dec 18 11:30:28 <vmaster> *to
Dec 18 11:30:58 <vmaster> motorola/freescale have SSIs capable of what JTAG needs, iirc
Dec 18 11:31:06 <vmaster> the bdi uses one of these
Dec 18 11:31:24 <lennert> the Abba-tron? :)
Dec 18 11:31:35 <vmaster> yep
Dec 18 11:52:23 <vmaster> mhh... the SSC on Atmel's SAM chips should work, but they have no high-speed peripherals, only full-speed
**** ENDING LOGGING AT Mon Dec 19 02:59:58 2005