**** BEGIN LOGGING AT Mon Jan 16 02:59:58 2006 Jan 16 06:07:30 morning folks Jan 16 06:08:10 * GyrosGeier enjoys the afternoon Jan 16 06:08:25 * vmaster considers having a after-lunch nap Jan 16 06:09:02 same as vmaster :) Jan 16 06:09:38 ka6sox, ka6six-office: ping Jan 16 06:09:59 * prpplague wishes it was still sunday Jan 16 06:10:09 * prpplague doesn't like mondays Jan 16 06:17:18 * GyrosGeier got up at 4:30 today, so he's feeling a bit tired already Jan 16 06:18:24 that's because 4:30 is 4 hours too early Jan 16 06:19:09 * vmaster tries hard not to get up before the sun is up Jan 16 06:22:36 i normally prefer to work from like 10am to 9pm but the company i work for really doesn't revolve around those time frames Jan 16 08:40:33 ka6sox, ka6sox-office: ping Jan 16 09:00:39 [g2]: just got an answer from my XJTAG assistant Jan 16 09:00:53 It costs GBP 9000 Jan 16 09:01:07 but they do good deals for academic institutions Jan 16 09:01:23 it runs at about 10Mhz, which means all the balloon2 test take < 10 seconds Jan 16 09:01:30 The good bits are: Jan 16 09:01:50 - a live 'XJAnalyzer' view of all the pins with customisable watches and Jan 16 09:01:51 manual twiddling, pulsing and so on Jan 16 09:01:56 - completely automated testing for shorts and opens as far as possible Jan 16 09:02:04 - a very cunning level of abstraction of boards into reusable devices Jan 16 09:02:05 via a slightly unpleasant language, XJEase. Jan 16 09:02:41 (so XJEase lets you easily write a suite of tests at a reasonably high level) Jan 16 09:14:28 * [g2] hugs wookie Jan 16 09:14:40 <[g2]> oops Jan 16 09:14:44 * [g2] hugs wookey__ Jan 16 09:15:57 <[g2]> wookey__ I've got a FGPA based approach that will run at 10MHz clock rate Jan 16 09:16:15 <[g2]> well I've got access to one :) Jan 16 09:17:29 <[g2]> I think the netlist processing will take some work, but I think it's all pretty straight forward Jan 16 09:17:57 <[g2]> it'll also take a little while to get the graphics pretty, but they'll work Jan 16 09:19:40 <[g2]> 10 seconds seems kinda fasts Jan 16 09:19:52 <[g2]> s/fasts/fast/ Jan 16 09:19:53 [g2] meant: 10 seconds seems kinda fast Jan 16 09:20:45 <[g2]> you are checking for shorts but are you bringing up external devices ? Jan 16 09:21:00 <[g2]> or doing that with SW tests Jan 16 09:22:31 <[g2]> wookey__ In my mind there are a couple target areas to address Jan 16 09:23:27 <[g2]> 1) is the capabilities to address the functional testing and it can start out custom to start, i.e., a V3 or V2 board and it's hand crafted Jan 16 09:24:11 <[g2]> 2) General tools like the 'analyzer' that allows testing on things like PXA27x chips or IXP42x chips Jan 16 09:24:37 <[g2]> 3) the tool generators that build it all and automate it all Jan 16 09:24:57 <[g2]> 4) extensions to special cases that 3) can't address Jan 16 09:32:21 hmm Jan 16 09:33:20 http://www.minford.ca/html/mf1500aadapter.html i have one of these , not got round to trying it out as yet , but think it uses the jtag method Jan 16 09:34:53 the interesting part of any JTAG adapter is not the hardware, but the software libraries it uses on the target Jan 16 09:35:10 the hardware can be easily built, e.g. with the FTDI chips Jan 16 09:35:26 its a simple little circuit using a 74hc244 and some resistors Jan 16 09:36:55 maybe ok for most jtag stuff but think it would be a bit slow for the real time pin state display Jan 16 09:40:06 thinking about it from a tools point of view , was reading a artical recently on the xbox380 linux project , Jan 16 09:40:59 they were using xilinx devices configured to form a logic analizer allowing high speed opperation Jan 16 09:42:12 guess maybe it could be posible to use a fpga itself with some interface like usb or ethernet to allow the unit to opperate at a faster speed than 10mhz Jan 16 09:42:50 AchiestDragon, the biggest problem with both USB and Ethernet is its RTT Jan 16 09:43:38 AchiestDragon, that's why a sane controller will be able to do bulk transfers on its own, without help from the host Jan 16 09:44:29 AchiestDragon, ideally, the block sizes are very large, or there is some kind of windowing technique (i.e. asynchronous error reporting) Jan 16 09:44:35 using a ram buffer and some trigger signal detection , detecting a time slice and beeing able to analize a period of time is as useful as a continus readout Jan 16 09:47:30 and unless the jtag will opperate at number of i/opins * i/o clock your not going to get a true readout of the pin state , that would put the jtag spec above the chips max ferquancy Jan 16 09:48:22 you're usually not interested in a true readout - if you are, you use a logic analyzer Jan 16 09:48:34 true Jan 16 09:51:54 <[g2]> GyrosGeier there are several kernel hackers in here and plenty of sw types Jan 16 09:52:24 <[g2]> IMHO there are 2 main roadblocks Jan 16 09:52:41 i guess GyrosGeier comes from the "debug" side of jtagging Jan 16 09:53:03 <[g2]> 1) Access to cheap fast JTAG hw which is why this group is formed Jan 16 09:54:41 well, even for the profiling side of JTAG you want an intelligent board Jan 16 09:54:58 <[g2]> 2) the programming skills and tools for the FPGA that's probably used in one Jan 16 09:55:46 <[g2]> So I think 1 well be significantly moved forward in the next few weeks Jan 16 09:56:22 <[g2]> and I think that we are getting closer to 2 or there may be a basis for start with a roadmap allowing updates Jan 16 09:57:11 1 is a problem that there are a number of easy solutions to if 2 can be made to work with them Jan 16 09:58:00 <[g2]> AchiestDragon I'm talking about 10Mhz+ capable devcies that are cheap Jan 16 09:58:26 [g2]: it's not only the tck rate, but the interface provided to the software layer Jan 16 09:59:00 http://www.opencores.org/projects.cgi/web/ethdev/overview vmaster you are absolutely right, however it's < $20 gets you an extra 600K gates so that's not really the issue Jan 16 09:59:24 <[g2]> the issue is the code associated with those 600K gates Jan 16 09:59:40 ohhh Jan 16 09:59:49 thers a usb fpga open hardware project on there also Jan 16 10:00:22 <[g2]> I've talked to the vendor that builds the Loft boards Jan 16 10:00:46 <[g2]> They can also build a little FPGA device. Jan 16 10:01:10 having a fpga programed for the task would program other fpga devices , and could posiblay offer some i/o configured as logic analizer inputs for use also Jan 16 10:01:13 it might be the sanest idea to get a Cypress or something like that to do the USB side and provide intelligence, and do only really time-critical stuff in the FPGA Jan 16 10:01:50 <[g2]> I had preliminary discussions Friday and it's possible to have devices in the not too distant future as it's pretty simple Jan 16 10:02:02 which is what Amontec have done Jan 16 10:02:14 (minus the USB stuff) Jan 16 10:02:35 <[g2]> one approach discussed was the CY068 and S3 Jan 16 10:02:40 or this http://www.opencores.org/projects.cgi/web/maxii-evalboard/overview Jan 16 10:04:34 i have been working on a fpga board http://www.whipy.demon.co.uk/fpga1.zip , but Jan 16 10:05:38 just had a major system crash and the windows box with my cad on is down , and lost the data , so got to restart Jan 16 10:07:31 but should be easy enough to come up with a custom pcb for jtag prgramming test using a fpga , and get it posted on open cores , if i can get windos to reinstall on the machine Jan 16 10:08:17 <[g2]> AchiestDragon I think putting the code on OC is a great idea Jan 16 10:08:51 <[g2]> However, it don't think OC has the stuff we are looking for (I may be totaly wrong) Jan 16 10:09:24 <[g2]> I'm not looking to get a big group discussing lots of different capabilities (we've done that here for quite some time) Jan 16 10:09:50 <[g2]> I'm interested in building a product that I can use, another friend can use for his boards, and wookey__ with the V3 Jan 16 10:10:01 i'm mainly hardware design rather than software , and want to learn how to program fpga's , but like you seem to have found cost is the problem Jan 16 10:10:41 <[g2]> well I think the BDI solutions and Abatron are like $2500 US Jan 16 10:10:52 <[g2]> then each processor family is more Jan 16 10:11:14 you get one processor family with the 2500 Jan 16 10:11:16 yea Jan 16 10:11:18 <[g2]> Like 1.5K for ARM, another for Xsclae etc... Jan 16 10:11:23 as well as the laugterbach Jan 16 10:11:36 the pc104 board i am doing is so i can play arround with a cyclone 2 device on my arm sbc Jan 16 10:11:38 but there's a lot more to the bdi2000 than just the hardware Jan 16 10:12:10 the target specific debugging logic is a lot work Jan 16 10:12:21 and they support almost every possible arm core for example Jan 16 10:12:25 <[g2]> vmaster absolutely there's a lot more Jan 16 10:13:08 the bdi's hardware is cheap - a 68332, a small cpld (32 macrocells or so), some flash and a bit sram Jan 16 10:13:24 <[g2]> but in my mind, a key reason this high speed professional wall hasn't been torn down is that there weren't devices avialable for the sw guys and hobbiest to go make it work Jan 16 10:13:49 definitely Jan 16 10:13:51 the problem is bga packages Jan 16 10:14:04 <[g2]> vmaster you are right about the target specific stuff, but there are 100s of devs Jan 16 10:14:14 <[g2]> there's like 5 ARM guys in here Jan 16 10:14:39 <[g2]> beewoolie is already working on the debug stuff Jan 16 10:14:52 ok so you can solder down a bga package with a toaster oven at home , but theres a 40% fail rate when you get good at it Jan 16 10:15:07 <[g2]> I think the XScale is about perfect as it works for IXP4xx and PXA27x Jan 16 10:15:33 and multilayer pcbs are not cheep and not easy to make at home Jan 16 10:15:41 <[g2]> AchiestDragon I can have these build and tested professionally Jan 16 10:15:57 <[g2]> then everyone gets a "known good" device" Jan 16 10:16:10 so can i , but theres a need for some that can be built at home Jan 16 10:16:12 <[g2]> and in the long run it saves tons of time and money Jan 16 10:16:34 AchiestDragon: if someone wants to build a jtag adapter at home, he uses a wiggler style parport interface Jan 16 10:17:28 for production then upto 16 layer pcbs and bga packages with 1700+ pads np , but for home use there are still alot of std surface mount devices that can be used Jan 16 10:18:33 the cyclone 2 in a 240pin qfp can be hand soldered with little problems at home , if you know how Jan 16 10:19:12 heh, i wont bother building this myself if g2 is able to have it built for $20 Jan 16 10:21:08 for a jtag progaming then i guess a device in a 64 or 100 pin quad flat pack could be used , and probabaly on duble sided pcb , so looking at £8 to £10 for a single 1 of pcb (would probabaly get 10 for that price ) Jan 16 10:22:31 plus the £ for the device and other components , in 1 offs would make it about £40 , in production guess around £15 dependent on the fpga cost Jan 16 10:22:53 what density do you get in 64 or 100 pin packages? Jan 16 10:23:22 on the fpga Jan 16 10:23:25 yeah Jan 16 10:24:03 ? i know thay do some in that , but i have been looking at bigger devices Jan 16 10:26:55 whats needed ? Jan 16 10:27:29 i guess you'll need one of the bigger devices with enough on-chip ram bits, or external ram Jan 16 10:27:41 no matter how clever your design is, you'll need quite large buffers Jan 16 10:27:57 external ram is going to be a better option Jan 16 10:28:19 yeah, but then a 2-layer pcb wont suffice, right? Jan 16 10:29:55 2 layers may be ok , will check that , depends on layout Jan 16 10:30:37 my point is this: for versatile 10mhz jtagging, a "simple" design wont be enough Jan 16 10:31:20 <[g2]> vmaster I'm thinking CY068 USB 2.0 device for host communications Jan 16 10:31:29 <[g2]> 600 or 1M gate S3 Jan 16 10:31:45 <[g2]> Jtag onboard for the FPGA and CY loading Jan 16 10:31:57 <[g2]> maybe 1 MB SRAM Jan 16 10:32:21 <[g2]> I guess ideally dual ported Jan 16 10:32:38 <[g2]> that would serve as buffers Jan 16 10:32:57 mhh, driving the fpga at twice the speed would be cheaper Jan 16 10:33:12 dual ported ram is expensive, isn't it? Jan 16 10:33:23 <[g2]> I dunno if any onboard storage for the FPGA is needed Jan 16 10:33:31 <[g2]> vmaster dunno cost Jan 16 10:34:28 <[g2]> We need to put a Bill of materials together with costing estimates Jan 16 10:34:46 i was thinking something like a sdram , say 32mb 8 or 16 bit device Jan 16 10:35:23 <[g2]> AchiestDragon that's great, but I think it's overkill Jan 16 10:35:35 although theres more ram there than needed , but the devices are cheeper than smaller dual port version Jan 16 10:35:36 s Jan 16 10:35:52 <[g2]> in my mind, the problem with the OC stuff is it's very large gate wise Jan 16 10:36:22 <[g2]> I think we just need to look at the BW and timing a little Jan 16 10:36:48 <[g2]> the CY068's can sustain nearly USB 2.0 rates, lets say 30MBs Jan 16 10:37:21 <[g2]> so we probably don't need dual-port SRAM Jan 16 10:37:26 <[g2]> at least initially Jan 16 10:37:29 yes , but remeber jtag devices are dasiy chained so when doing something like a board test you may be testing 5 or more devices Jan 16 10:38:02 <[g2]> AchiestDragon right, and that's limited by TCLK and the FPGA right ? Jan 16 10:38:17 yes Jan 16 10:38:29 <[g2]> the shift chain on the IXP42x is 497 498 Jan 16 10:39:23 <[g2]> we need to start defining the OPs (operations) on the FPGA for given processors/families Jan 16 10:39:50 <[g2]> and some general JTAG stuff that's applicable to all Jan 16 10:40:22 <[g2]> there are two specific applications from my perspective Jan 16 10:40:37 <[g2]> 1) post-build board testing Jan 16 10:40:43 <[g2]> 2) General board testing Jan 16 10:41:09 <[g2]> I think in case 1) you know exactly what you want to test and are optimizing it Jan 16 10:41:28 <[g2]> it's a question of cost/time for how much you trade off Jan 16 10:42:34 <[g2]> I"m looking to provide myself, wookey__ and others that want to build boards with a mechansim that helps driver down the cost of those boards and drives up the quality Jan 16 10:42:55 <[g2]> clearly that provides value to many Jan 16 10:44:37 looking at the data for the cyclone devices the bigest 144pin tqfp packaged device is a ep2c8 that has 8,256LE's and about 200k ram & 26 multiplyers Jan 16 10:46:17 there is a smaller 100 pin tqfp cyclone2 with 2,910 LE's and about 72k ram , no multipliers Jan 16 10:46:33 ram size in bits not bytes Jan 16 10:49:32 the ep2c8t144c7 costs us$23.1 in 1 offs from altera thats the 144pin device Jan 16 10:50:41 AchiestDragon: xilinx has some major advantages: lennert and ka6sox Jan 16 10:52:54 ha Jan 16 10:52:57 k Jan 16 10:53:23 they know the devices and the toolchain Jan 16 10:55:38 just that the xilinx devices 1 seem a bit power hungry , 2 cost more , 3 there tools are free but with a limit on the max device size , altera tools are free for all models they do Jan 16 10:56:04 although some of the xilinx devices are cool Jan 16 10:59:04 <[g2]> AchiestDragon since many ppl are already on the Xilinx horse it'll be hard go get everyone to switch :( Jan 16 10:59:22 well np Jan 16 11:04:34 something like a xc3s250e is avalable in a tqfp 144pin package , 250k system gates , 5,508LE's 200kbits ram should do Jan 16 11:09:32 infact this with some diferent software should do http://warmcat.com/milksop/filtror.html Jan 16 11:13:57 he's got a good page showing how to solder the devices in also http://warmcat.com/milksop/soldering.html Jan 16 11:17:51 his pcb is dubble sided with ram on there also , bit of reworking of it to provide buffered jtag outputs sourced from the fpga and something along the lines of that should do the job Jan 16 11:18:33 and mabe add usb if needed rather than parallel port Jan 16 11:27:17 soldering that fine of a pitch is a PITA Jan 16 11:27:22 although that uses a clpd , so may be better using a true fpga , so it can be reprogramed Jan 16 11:27:57 CPLDs are faster but a LOT smaller. Jan 16 11:29:06 the method he shows for soldering works i know someone that uses it all the time , i prefer solder paste and a hot air gun Jan 16 11:29:50 that works nice...I have the Hot Air machine too. Jan 16 11:34:01 :) yes , btw the hot air guns (the type used as hot air paint strippers ) work fine also and dont cost the hobbiest anything like that of the hot air solder stations Jan 16 11:34:36 mine was about $300 with all the nozzles but it worth it. Jan 16 11:35:17 AchiestDragon, what are you looking to do? Jan 16 11:37:41 i'm trying to build a robot , but its a long project , as i need to coordinate 40 servo motors with balance feedback i'm planning on useing a fpga as the logic for the balance feedback and i/o from the cpu Jan 16 11:38:47 but as the fpga is going on a 4 layer pcb i endup with a min order of 5 pcb's so want to make the fpga board sutable for other uses Jan 16 11:42:41 so end result will be a robot , but there is quite a few offshoot projects from it that will do other things also Jan 16 11:43:42 AchiestDragon, interesting!! I'm into robotics too. I'm using the slug as my controller. Jan 16 11:44:01 started from me looking at this http://warmcat.com/milksop/soldering.html open hardware project Jan 16 11:44:30 there seems to be little activity there , and im not too hapy with there design Jan 16 11:44:45 so im starting a new one from scratch Jan 16 11:46:13 the only requirements i have set is it has to make and bring me coffee , although the make coffee bit maybe just to retreve the cup from a coffee vending machine Jan 16 11:46:56 Keep in mind that the easiest part is the hardware! Software is much tougher! Jan 16 11:47:21 and terain excludes use of wheels or tracks , so it has to walk Jan 16 11:47:23 yes Jan 16 11:47:38 ouch! Jan 16 11:47:52 You might need vision then. Jan 16 11:48:20 software is a diferent matter , although no time limit on how long it will take Jan 16 11:48:36 that helps. Jan 16 11:48:55 you might want to look into behaviour based methods. that's what I'm using. Jan 16 11:49:22 vision well maybe , ultrasonic rainge finders , gps electronic compas ,and some environment mapping functions Jan 16 11:49:25 Much more robust in a real world environment than your typical beginner's if-else-then/loop coding method. Jan 16 11:50:09 vision in the form of video is deceptive , distance ranging can generate terain mapps a lot easyer Jan 16 11:50:17 none of them are 100% reliable which makes it harder so the tough part is to integrate them together (sensor-fusion) Jan 16 11:51:01 yeah, but they each have advantages. Jan 16 11:51:38 well using a 200mhz arm micro , and upt to 4 cyclone 2 fpga boards doing hardware implimented functions Jan 16 11:51:52 nice. Jan 16 11:52:15 some of the vision stuff lends itself well to hardware implementation. Jan 16 11:53:12 theres also wifi link to a remote system and the only plans for camara vision is just for remote monitoring of it Jan 16 11:56:01 i have some good algorithoms for the motors and a sequencer that is adaptive to its environment Jan 16 11:56:49 nice. homebrew or? Jan 16 11:57:15 its a long term project for 2 reasons , 1 its going to take a long time to sort the software , and 2 i have to save up for the bits as i am going along Jan 16 11:57:27 homebrew Jan 16 11:58:32 I'd be interested in seeing some of your work. Jan 16 11:59:44 http://www.whipy.demon.co.uk , part of the project , in that its the cnc machine i designed and built so i can make the parts for the robot Jan 16 12:00:18 nice Jan 16 12:00:29 mine is at http://robotics.no-ip.org Jan 16 12:01:53 ohh, nice, that cnc machine Jan 16 12:07:45 back later.... Jan 16 12:16:34 I've started writing together what a generic JTAG interface could look like: http://openocd.berlios.de/web/?page_id=22 Jan 16 12:16:50 interface as in "supported functionality" Jan 16 12:23:00 ok silly question time , is that the site for this project ? Jan 16 12:23:51 mhh, no, that's the site for my project Jan 16 12:24:12 k Jan 16 12:24:40 well next silly question is there a site for this project yet Jan 16 12:25:09 openjtag.net Jan 16 12:25:37 ty Jan 16 12:26:40 maybe worth the site link beeing put in the chan topic Jan 16 12:35:17 hmm Jan 16 12:37:50 k reading that site gives me a better idea of where the project is at Jan 16 12:38:46 The wiki hasn't been updated lately sorry Jan 16 12:39:02 np Jan 16 12:40:36 although i would be tempted to use a fpga rather than a clpd , in that there is more future scope for the board then Jan 16 12:41:27 and posibilaty of extra funtions , alternete configuration is posible with little effort Jan 16 12:45:12 things like allowing software reconfiguration to allow for diferent jtag pinouts ( assuming the buffers used can support this also ) Jan 16 12:45:47 would help where a non standard jtag pinout is used Jan 16 12:47:29 it could also allow for it to be reconfigured to act as a isp unit (ok so diferent software ) but makes it more of a universal device Jan 16 12:49:05 remembering that a hobbiest that uses jtag for testing and development programming , usualy has a need to do isp and maybe flash reprogramming , and i2c eprom reprogramming Jan 16 12:50:44 allthough the software here is just for the jtag side if the unit has the capablilay its can be left for future implimentation or for others to write the other functions that may be posible from it Jan 16 12:53:05 and the advantage that the one unit could be capable of more than a single function for verry little extra is a good point that i tink needs to be looked at even if its not imediatly going to include software support Jan 16 12:56:10 has the dongle been built yet , is the design set or still in flux ? Jan 16 13:28:19 AchiestDragon, the interface looks good to me...we are working on the software and a FPGA board for allowing additional functionality Jan 16 23:11:45 ~lart ka6sox Jan 16 23:11:45 * purl beats the living hamstercrap out of ka6sox Jan 16 23:11:53 heh **** ENDING LOGGING AT Tue Jan 17 02:59:58 2006