**** BEGIN LOGGING AT Tue Jan 17 02:59:58 2006 Jan 17 03:01:49 vmaster_: are you on by chance? Jan 17 03:03:27 ho hum Jan 17 08:01:13 yawn Jan 17 08:01:38 don't start taht Jan 17 08:01:44 or we will all be yawning Jan 17 08:05:19 too late Jan 17 08:05:24 need coffee Jan 17 08:05:29 need more coffee Jan 17 08:05:32 bbl Jan 17 08:05:44 * prpplague hand ByronT a cup of dark coffee Jan 17 08:06:21 dark?!? only dark?!?! if the spoon can't stand up by itself in the middle, I don't want it! Jan 17 08:06:33 coffee needs to be crunchy Jan 17 08:06:36 mmmm Jan 17 08:06:44 more like cut it with a pair of scissors after finish pooring Jan 17 08:06:47 now I'm back from the coffee maker Jan 17 08:07:18 I have thought about using coffee grinds like a tobacco dip Jan 17 08:07:29 thick and Sweet. Jan 17 08:07:39 like when I was in brazil Jan 17 08:08:17 thats what they serve on the boats going up and down the Amazon. Jan 17 08:11:40 ahhhhhh Jan 17 08:11:47 I can feel my eyes dilating Jan 17 08:12:23 crunchy coffee... breakfast of champions Jan 17 08:13:11 heh Jan 17 08:13:16 hi ByronT Jan 17 08:13:25 morning Jan 17 08:13:41 round2 Jan 17 08:13:54 how'd things go yesterday? Jan 17 08:14:06 he still hasn't opened his eyes Jan 17 08:14:13 we will see if he does today ;) Jan 17 08:14:28 yesterday was a cryfest. Jan 17 08:14:39 but doctors said everything went well? Jan 17 08:15:44 I can only imagine - parenthood seems to be payback for all the times that our parents told us that we were doing something and it hurt them and we laughed at it Jan 17 08:19:21 we shall see if it went well or not Jan 17 08:19:25 I'm not sure yet Jan 17 08:20:12 I have to leave in 10 minutes so let me get my second cup down and get things moving on at least 1/2 the cylinders. Jan 17 08:20:23 back about 1.5hrs Jan 17 08:20:26 talk at ya later Jan 17 08:20:45 ka6sox: got a new critter in the house? Jan 17 08:24:04 prpplague, got a 4yr old who had eye surgery yesterday morning Jan 17 08:24:34 oh shoot Jan 17 08:24:43 ka6sox: anything major? Jan 17 08:25:55 prpplague: just a general note... "minor surgery" is surgery to anyone not related to oneself... ;) Jan 17 08:28:29 ByronT: i see Jan 17 08:35:40 <[g2]> hey lennert I'm behind on my write-up :( Jan 17 08:37:27 [g2]: :-( Jan 17 08:37:34 prpplague, he had surgery for lazy eye Jan 17 08:37:39 ahh Jan 17 08:38:03 <[g2]> lennert I'll get to it late today or tomorrow Jan 17 08:38:04 ka6sox: wish i could get a surgery for my sons "lazy ass" Jan 17 08:38:23 <[g2]> the good thing is things are moving along Jan 17 08:38:50 [g2]: looking forward Jan 17 08:52:52 prpplague: rotfl Jan 17 08:54:28 wookey__: hehe, trying to break him of it early Jan 17 09:08:04 wookey__: don't suppose to met up with pb_ very often since you guys are in the same neighborhood Jan 17 09:08:15 s/to/you Jan 17 09:08:21 * prpplague needs more coffee Jan 17 09:46:36 prpplague: we meet occaisionally, and at events of one sort or another. Last year we were on the same project and met loads Jan 17 09:46:59 actually, no year before - bloody hell - where does the time go? Jan 17 09:47:18 wookey__: ahh , hehe, it definetly disappears rather quickly Jan 17 10:02:16 has anyone got the schematics for the proposed interface ? Jan 17 10:27:16 they might be in CVS Jan 17 10:27:29 check out the openjtag CVS at SF.net Jan 17 10:28:19 k Jan 17 10:29:09 hi; ka6sox: just wanted to tell you I sent a summary of our discussion (adding SDRAM on NSLU2) to nslu2-linux, #10838. ok? Jan 17 11:30:25 been having a think , with a xilinx xc3s250 it should be posible to use a ip core for the usb rather than needing a ftdi chip and as the xc3s250 has configerable i/o then should be possible to set the i/o voltage levels Jan 17 11:31:58 xc3s200 you mean? Jan 17 11:32:03 so the jtag interface module would just need a usb buffer , fpga and sdram chip and a config device , and the usual other bits like conectors and psu Jan 17 11:32:07 or xc3s400 Jan 17 11:32:15 i don't think there is a -250 Jan 17 11:32:23 (but i could be mistaken..) Jan 17 11:33:26 well the xilinx site in the data says 250 but that could be a missprint as the closest i have the footprint and part info for in dxp is the 200 Jan 17 11:35:41 http://direct.xilinx.com/bvdocs/publications/ds312.pdf this says they do 100, 250, 500, 1200 and 1600 vesions but doesnt match what is avalable Jan 17 11:35:57 the datasheet for the spartan3 is ds099.pdf Jan 17 11:36:29 this is the spartan3e Jan 17 11:36:37 yes Jan 17 11:36:38 different beast Jan 17 11:36:40 k Jan 17 11:36:41 xc3s250e, not xc3s250 Jan 17 11:36:45 okay Jan 17 11:38:00 althoug in a 100 pin package the pinouts are the same for the 100 and 250 versions , just internal capacaty thats diferent Jan 17 11:38:26 that's the same in any fpga Jan 17 11:38:35 there are typically 2 or 3 capacities for the same pinout Jan 17 11:38:43 and 2 or so pinouts for a single capacity Jan 17 11:38:47 so that you have an upgrade path Jan 17 11:40:27 well with a 32mb *8bit sdram theres 33 i/o pins to play with Jan 17 11:41:45 so 2 for the usb , 2 that are going to endup on a bank with a set volatage as other pins on it need 3.3v Jan 17 11:42:12 leaving 4 banks to play with Jan 17 11:43:48 so could manage jtag on one bank leaving 3 banks so could even suport an alternate host i/f like parallel port Jan 17 11:44:34 or rs232 with the right buffers , or maybe use the extra inputs for logic analizer functions Jan 17 11:50:44 the only xilinx fpga i have had an indepth look at is the vertex pro xc2vp20 , that allowed a function that part of the device could be reprogramed while the rest was opperational Jan 17 11:51:11 partial reconfig Jan 17 11:51:19 yes Jan 17 11:51:25 i have some xilinx cplds, an xc3s200 and an xc2vp30 Jan 17 11:51:43 do you know if the smaller parts do Jan 17 11:55:23 the sp3 can do partial reconfig, i think Jan 17 11:55:28 but i'm not 100% sure -- check ds099 Jan 17 11:55:40 k Jan 17 12:02:10 the only disadvantage i can see in using a fpga , is the inital programming of the config for the board , since this is a jtag test and programming device its a bit bad if you need to build a programmer to program it in the first instance Jan 17 12:03:00 use a prom.. Jan 17 12:03:12 or do usb firmware download Jan 17 12:03:47 still need a prom programer , usb download would be a better option but would still need a usb chip Jan 17 12:04:58 you can progam xilinx proms with jtag Jan 17 12:05:56 catch 22 , how do you initaly program your jtag programmer with jtag ? when that is the only programmer you have Jan 17 12:06:22 you let someone else make the board Jan 17 12:06:45 that's like saying that c sucks because the c compiler is written in c -- you download someone else's binary Jan 17 12:07:39 well i gues if your building this board then you may already have a means to program the device Jan 17 12:07:57 you should.. Jan 17 12:44:56 if it offers both usb and parallel port options for linking it to a pc then it could be initaly programmed up using the parallel port Jan 17 13:28:53 hey beewoolie-afk - missed you for about 5 minutes this morning Jan 17 13:33:24 vmaster: Jan 17 13:33:41 vmaster: I was just wondering if you would be on so late...my time. Jan 17 13:33:49 I have a question about your openocd project. Jan 17 13:34:32 heh, it was 11am for me, so yeah, usually i would be on Jan 17 13:35:40 I was reading the arm9tdmi.c file and found something that I couldn't explain. Granted, that my overall comprehension of the code is limited. Jan 17 13:36:04 beewoolie: hey hey bud Jan 17 13:36:08 beewoolie: whats cookin? Jan 17 13:36:15 In arm9tdmi_examine_debug_reason(), there is a call to jtag_add_dr_scan without calling jtag_execute_queue afterward. Jan 17 13:36:20 Is this OK? Jan 17 13:36:26 prpplague: yo. Jan 17 13:36:47 yeah, the second dr scan doesn't have to be executed immediately Jan 17 13:37:01 i'm trying to build command buffers as large as possible for the ft2232 Jan 17 13:37:30 I wondered because it references a stack variable as an output, but the function returns before it can be processed. Jan 17 13:38:05 out values are copied Jan 17 13:38:21 out is host->device Jan 17 13:38:27 I mean outputs *from* the target. Jan 17 13:38:47 the in_value of all three fields is set to NULL Jan 17 13:38:55 before the second dr_scan Jan 17 13:39:57 OK. I see what you mean. The fact that debug_reason is a reference made me think that it was returning a value. Jan 17 13:40:23 ah, i see Jan 17 13:41:51 the output values are copied inside jtag_add_dr_scan, so the calling code doesn't have to take care about this any more Jan 17 13:49:51 the ftdi 2232 has a eeprom interface , that can be configured over the usb , is wondering if theres a way to trick it into using a bigger device that could initalize a fpga with a bit of crafty interfacing Jan 17 13:50:19 prpplague: Are you back to some dev work? Jan 17 13:50:25 I"ve looked at that...the algorithm isn't avalilable for it (as far as I can tell) Jan 17 13:50:32 beewoolie: yep, actually testing apex now Jan 17 13:50:56 AchiestDragon, I only have a windows config program. Jan 17 13:51:05 Have you tried enabling the MMU? Jan 17 13:51:27 will it run in wine ? Jan 17 13:51:39 AchiestDragon, haven't tried Jan 17 13:52:21 I plan on having the FPGA separate from the interface Jan 17 13:52:29 and if possible using Ethernet Jan 17 13:52:41 ala BDI Jan 17 13:52:56 k Jan 17 13:53:16 so 2 difernt hardware methods Jan 17 13:54:02 the interface board that ep1220 designed should be used as it provides all the various voltage/connector configurations. Jan 17 13:54:29 the S3e board will be used for Memory/Programming/Breakpoint stuff Jan 17 13:54:46 is that using the dlp 40 pin dip module Jan 17 13:55:21 there is a connector on the S3e board that should be easy to adapt to the 40pin DIP Jan 17 13:56:33 brb Jan 17 13:56:47 prpplague: the I'm curious of the MMU enabling code works on your targets. Jan 17 13:56:54 k, personaly from past experiances i would use the chip , but not take advantage of the evaluation module , evaluation modules have a habit of only beeing avalable for a short time , 6 months to 2 years Jan 17 13:57:04 beewoolie: ahh Jan 17 13:57:12 beewoolie: i'll have to test that tomorrow Jan 17 14:01:24 bbl Jan 17 14:01:50 AchiestDragon, by that time we could move on to a "custom" board Jan 17 14:02:05 a custom board would be very expensive for prototyping. Jan 17 14:02:18 (the interface is "custom" so we still need that. Jan 17 14:02:21 ) Jan 17 14:02:35 not too bad , it can be done easy Jan 17 14:03:20 about £15 for a 100*160mm pcb (dubble sided ) in 1 offs Jan 17 14:03:57 and it looks like you could get 4 or more on a pcb that size Jan 17 14:05:42 if 4 layers are needed , in the next 4 to 5 months i am getting a 4 layer pcb made for another project only using 100mm*100mm so have 60*100mm left for another project atm Jan 17 14:06:01 back in 30 mins Jan 17 14:06:51 AchiestDragon, cya then Jan 17 16:03:02 vmaster: I've got another question for you if you're listening. Jan 17 16:03:29 AchiestDragon, ping? Jan 17 16:03:42 2 mins ,,, pong Jan 17 16:04:32 yop Jan 17 16:04:37 lennert: there ? Jan 17 16:04:44 k ,,back Jan 17 16:09:53 someone has tryed to run a linux on a xilinx (xc2VP30) ? Jan 17 16:11:56 yes , afik , it will run linux , with the right hardware config , that has a ppc core built in Jan 17 16:13:46 there was on of there evaluation boards that ran linux using one in that series of fpga's Jan 17 16:15:03 down side was there tool set for configureing the fpga the free ones did not support the vertex pro chips so a $4000 for the software that would Jan 17 16:21:16 ya...there is cheaper but I'm looking at "other" cores. Jan 17 16:21:27 Leon :) Jan 17 16:27:18 ka6sox-office: if the design is funtional using the eval boards im willing to redo the pcb artwork so its a compleate single custom board option , and should be able to build 1 or 2 test versions of it Jan 17 16:28:51 AchiestDragon: what do you use for makin pcb ? Jan 17 16:29:30 been having a quick look and may be able to get it into 50mm*50mm ( for a fpga version with sdram ) on 4 layers , and easy within 60*100 on dubblesided Jan 17 16:30:02 AchiestDragon: yeah but what software do you use for makin you pcb? Jan 17 16:30:05 protel dxp , for the cad , i use a company called ecp circuts to make them Jan 17 16:30:17 ecp circuit ? Jan 17 16:30:21 they solder bga ? Jan 17 16:30:36 no but make upto 16 layer pcbs Jan 17 16:30:38 AchiestDragon, thanks. Jan 17 16:31:25 theres another company that i would use for assembly , but for 1 or 2 i would probablay assemble them myself , unless bga Jan 17 16:31:33 AchiestDragon: and how do you wanna solder a BGA on it Jan 17 16:31:47 and what about BGA :) Jan 17 16:31:50 i could do the rest Jan 17 16:31:55 but I don't have a BGA oven Jan 17 16:32:08 was not planning to use a bga Jan 17 16:32:11 but Jan 17 16:32:23 you know virtex that is not BGA ? Jan 17 16:32:25 with PPC in it ? Jan 17 16:32:41 AchiestDragon, BGA isnt' fun Jan 17 16:32:53 we did BGA PPCs Jan 17 16:33:49 http://www.seattlerobotics.org/encoder/200006/oven_art.htm < this works for bga packages , but expect a 40 to 60% fail rate Jan 17 16:34:00 AchiestDragon: so you think I would be able to run a Linux using both PPC of the xc2vp30 (http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P) Jan 17 16:34:03 ? Jan 17 16:34:32 so no good for the 1700 pad bga packages as it could prove expesive Jan 17 16:35:17 thay manage to run multiple cores in the ps3 in linux Jan 17 16:35:24 well 299 is not that expensive Jan 17 16:35:50 it's hardcore right ? Jan 17 16:35:59 AchiestDragon, I don't think we need to spend that much! Jan 17 16:36:10 I wasn't going to go HardCore. Jan 17 16:36:19 the Dev system is toooo much Jan 17 16:36:42 in the vertex yes its hard core , but we dont need anything that big for this project Jan 17 16:37:03 hard core for the internal ppc's that is Jan 17 16:37:22 what project :) Jan 17 16:37:26 AchiestDragon: Looks like a great use for JTAG verification Jan 17 16:37:55 and the rocket i/o would be tops for logic analizer also Jan 17 16:38:18 AchiestDragon: what's the project :) share Jan 17 16:38:18 1 to 2Ghz on 6 to 24 chans Jan 17 16:39:13 that was scrapped about 3 years ago , because there was no way to get the software to reconfig it on open source Jan 17 16:39:55 the WebPack is a LOT better now. Jan 17 16:39:57 and xilinx had no plans to relece the free web tools with a vretex pro capablility Jan 17 16:40:13 they have V4 capability now Jan 17 16:42:12 i designed a board that used a vertex pro 2vp20 that had one ppc core , some external fast syncronus ram 256mb at 800mhz and some i/o , with a compact flash for fpga config and system o/s bootup Jan 17 16:42:57 the board was to be 6 layers , and be open hardware , but the software problem and a hardware suplyer proble stopped it Jan 17 16:43:50 the ram was made by micron , but was in pre production samples at the time , micron got bought out and the ram got discontinued Jan 17 16:45:17 so a large redesign , i was on version 0.9 at the time , allong with a personal problem i susspended futher development , Jan 17 16:45:46 the 2vp20 was £700 in 10 offs at the time , so there cheaper now Jan 17 16:46:10 is the S3e good enough? Jan 17 16:46:19 or do we need the Virtex? Jan 17 16:46:41 since then i found the cyclone 2 and that seems good for the price and with the free tools Jan 17 16:47:14 for just jtag guess a small spartan2 or 3 should do the job Jan 17 16:48:48 we want to build something that replaces a BDI2000 (at a hobbiest price :)) Jan 17 16:49:06 it dosent need to run a o/s , it basicaly needs to opperate as a serial buffer to the host , so the host can pre load contents to ram , and once loaded its just blasted into the device Jan 17 16:49:09 I'd like it to be about $250 Jan 17 16:49:29 do you have a link for the bdi2000 Jan 17 16:50:07 abatron AG Jan 17 16:50:08 AchiestDragon: vhdl or verilog ? Jan 17 16:51:02 http://www.abatron.ch/ Jan 17 16:51:38 me , not managed ether yet , still working on desining a hardware platform , but dxp lets me enter in schematic form , and get the idea of both Jan 17 16:52:30 AchiestDragon: where you from ? Jan 17 16:52:38 uk Jan 17 16:52:49 k Jan 17 16:54:04 by the way, someone knows a solution for reading/programming a flash rom onboard Jan 17 16:54:09 without unsoldering it from the board ? Jan 17 16:54:36 like something you plugg on the flash rom and it touches all its pins ? Jan 17 17:13:24 key2: best current method is jtag. Jan 17 17:13:51 It does, in effect, what you say by applying signals to the system busses. Jan 17 17:28:53 most systems use eather jtag or some other form of isp to do that , for production reasons there programmed after the board is assembled Jan 17 17:29:20 and can be reprogrammed the same way Jan 17 17:30:28 although jtag is often used , some do not stick to the standard jtag header pinouts Jan 17 17:36:57 wb Jan 17 20:41:31 ka6sox: yo Jan 17 20:42:14 ka6sox: rilly close to being able to write flash Jan 17 20:42:20 sweet! Jan 17 20:42:44 For some reason, I'm unable to read from the bus. Jan 17 21:30:56 :) Jan 17 21:31:02 AchiestDragon: Hey. Jan 17 21:31:12 hi Jan 17 21:31:30 so if we use a combination of both a uC and FPGA then we can solve the problems of HID and speed. Jan 17 21:32:21 plus posible stand alone use of the unit Jan 17 21:32:27 FPGA for handling the JTAG (at up to 40mhz) Jan 17 21:32:27 yeah. Jan 17 21:32:48 and something like an ARM(X) to handle the HID and high level stuffs. Jan 17 21:32:50 CPU with OS for the comfortable chair. Jan 17 21:33:07 Plus it can be a wireless router! Jan 17 21:33:09 okay I would say that most here are more comfortable with Linux Jan 17 21:33:11 debian arm Jan 17 21:33:16 And it can play movies and MP3's! Jan 17 21:33:23 debian arm works. Jan 17 21:33:32 so arm7 or arm9 Jan 17 21:33:49 I think that an arm7 would be sufficient. Jan 17 21:34:03 However, the cost difference at this level should be negligible. Jan 17 21:34:14 We aren't doing a pixster. Jan 17 21:34:17 best to use a standard bus for the interface between the FPGA and the main board. Jan 17 21:34:27 like PC104 or something like that. Jan 17 21:35:08 we have discussed the TS7200 before and it has the power/price/interfaced Jan 17 21:36:10 ARM9/8MB Flash/32MB RAM/CF Jan 17 21:36:26 and PC104 Jan 17 21:36:41 also USB as well as 10/100 Ethernet Jan 17 21:37:11 so building a sufficiently powerful yet relatively inexpensive box is doable with that configuration. Jan 17 21:37:12 Does the tsXXXX have USB client? so we can plug into a notebook that way? Jan 17 21:37:26 I think its host only Jan 17 21:37:35 2* rs232 a lcd and keypad ports Jan 17 21:37:43 doesn't look like it. Jan 17 21:37:59 No lcd. Jan 17 21:38:05 lcd connector Jan 17 21:38:06 it is host but i know that there are cables that let you use usb host to host Jan 17 21:38:15 and DIO as well Jan 17 21:38:23 I don'tsee LCD on the spec page. Jan 17 21:38:27 (which could be used as Keypad. Jan 17 21:38:46 Of couse there are lots of PC104 options. Jan 17 21:38:48 click on image detail Jan 17 21:39:00 and look 6PM on board Jan 17 21:39:28 it suppots the interface for the small lcd modules based on the hitachi chipset , from 1 line 8 charicters to 4 lins 40 charicters Jan 17 21:39:47 It isn't metioned on the data sheet. Jan 17 21:40:09 Oh. I see what you're talking about. That's usually just I2C. Jan 17 21:40:10 it is in the manual Jan 17 21:40:28 A real TFT LCDpanel needs more pins. Jan 17 21:40:35 http://www.embeddedarm.com/Manuals/TS-7200_Rev1.4.htm#LCDHeader Jan 17 21:40:49 its just enough for a Standalone solution. Jan 17 21:41:24 OK. I'm not sure how usefulthat will be except to display the clock speed and some blinken lights. Jan 17 21:41:34 These DIO pins have 100 KW bias resistors biasing these inputs to a logic ?1? Jan 17 21:42:01 let me stand away from these Resistors if they have 100 kiloWatts on them. Jan 17 21:42:13 good thinking Jan 17 21:42:17 lol Jan 17 21:44:13 with a S3/Cyclone 2 part on the FPGA board there will be enough room for the Chain Control/Chain Scan/SDRAM control/PC104 Control/and maybe even VGA :) Jan 17 21:44:53 the pullups and use is documented in the manual they allow a keypad swich matrix to be connected directly without external components while not interfearing with alternate use of the port if you wish Jan 17 21:45:08 :) Jan 17 21:45:09 What would be kinda cool is if we could do some sort of logic-analyzer setup with it. Jan 17 21:45:21 okay so this is what we are looking for. Jan 17 21:45:29 its reasonable in cost too. Jan 17 21:45:59 BBIAW. Gotta take care of something... Jan 17 21:46:08 k Jan 17 21:46:37 the TS-7200-32 is only $149 (minus the CF card) Jan 17 21:47:02 so tftp and telnet should be a given Jan 17 21:48:25 yes , telnet , and tftp are pre installed in the onboard flash Jan 17 21:48:31 That's really cheap. DOH, I'm really going... Jan 17 21:48:45 ...soon apex, too... Jan 17 21:50:49 nite beewoolie Jan 17 21:51:44 if we had to we could use the RTlinux kernel. Jan 17 21:52:11 then we would be assured high performance on the JTAG> Jan 17 21:53:35 I would think that the CF would mostly be used for holding images and captures from using somthing like gdb Jan 17 21:54:22 AchiestDragon, is the toolchain the CrossTool one from Dan Kegel? Jan 17 21:55:42 yes , although the one supplied has the correct patches for the ts7200 Jan 17 21:56:45 the 256mb cf image that you can download from embbeded arm has a full debian arm distro with all the tools Jan 17 21:57:39 sweet Jan 17 21:57:44 that image can be installed on a cf card , usb memory stick or usb hdd , and boot from any is posible Jan 17 21:58:00 so is there a native toolchain too? Jan 17 21:58:43 * ka6sox thinks about USB HD's attached for building if necessary. Jan 17 21:58:56 although i find for development a usb hdd is best as you can set up a swap partition that helps with memory hungry apps like apt-get and python Jan 17 21:59:26 where 32mb ram is not enough Jan 17 21:59:44 I've got 2 Xscale armeb buildd boxes running and they swap too darned much with only 32MB Jan 17 22:00:31 especially with cc1plus Jan 17 22:00:59 i compile everything for the ts7200 on it , as i get problems on my linux box if i install the cross tools Jan 17 22:01:09 okay Jan 17 22:01:28 so we could just host the toolchain natively on the TS Jan 17 22:01:34 yes Jan 17 22:01:35 that would work too. Jan 17 22:01:54 I have been using CF's as main HD's for about 3 years with no ill effects. Jan 17 22:02:09 (I use LOTS of RAM to overcome the lack of swap. Jan 17 22:02:19 but when I first started we only had 128MB. Jan 17 22:02:47 with mini-ITX form factor. Jan 17 22:03:05 the TS7200 should be able to do what we need. Jan 17 22:03:08 the only down side for the ts7200 is ram , its not easy to expand it Jan 17 22:03:34 for this app it should be plenty Jan 17 22:03:45 (development is another story :)) Jan 17 22:04:32 the pc/104 only has a 1mb address space , so the sdram on the fpga will need pageing but not a big problem Jan 17 22:05:20 * ka6sox remembers paging on the 6809 Jan 17 22:05:29 :) Jan 17 22:05:36 we could get 128KB Jan 17 22:06:38 okay that driver will be the biggest PITA. Jan 17 22:06:41 remembers stacking 4114 ram chips and wireing the ce inputs seperate to dubble memory capacaty also Jan 17 22:07:03 we did that with 2114's also Jan 17 22:07:24 much before Surface Mount :) Jan 17 22:07:31 yes Jan 17 22:09:12 this gives me much to chew on (and might just cause a little insomnia :)) Jan 17 22:10:01 lol its 5:10 am here bed time for me soon been up all night Jan 17 22:11:01 sorry to keep you up! Jan 17 22:11:03 :) Jan 17 22:11:45 sounds like we both need sleep. Jan 17 22:11:57 I've been up way too early the last 2 days. Jan 17 22:17:52 sleep well Jan 17 22:18:14 night Jan 17 22:35:20 ka6sox: I don't see any reason to do development on the target. Jan 17 22:35:59 The cross development tools are excellent. With an NFSmount, everything we care about can be done on a fast X86 host except for running the jtag software. Jan 17 22:36:47 in fact, I've never seen the allure of developing on these small targets. Jan 17 22:37:13 Oncethe system is booted, we will see thay 32MiB is really quite fat for running our application. Jan 18 00:18:19 beewoolie: okay, i'm listening Jan 18 00:18:37 hey Jan 18 00:18:53 hang on Jan 18 00:23:11 OK. Still there? Jan 18 00:23:24 yeah Jan 18 00:23:48 I'm mastering the arcane magic of ARM9 JTAG. Jan 18 00:24:09 I want to read from the bus. Jan 18 00:24:22 But I only get zeroes. Jan 18 00:24:47 mhh... how did you enter debug state? Jan 18 00:24:54 What documentation did you work from when you worked out the details of ARM JTAG? Jan 18 00:25:07 Yeah. I've stopped the core with a debug RQvia EmbeddedICE. Jan 18 00:25:35 And I can tell that I am restarting the code and then getting control back by watching for the SYSCOMP bit. Jan 18 00:26:16 i used the arm datasheets (all of them, not a single one is remotely complete) Jan 18 00:26:22 and a lot of trial-and-error Jan 18 00:27:05 I've been working from the 922 datasheet. Jan 18 00:27:30 "read from the bus" means you want to read fro memory? Jan 18 00:27:37 I'll look at some others. I've been under the impression that the arm7's and arm9's are either compatible or very close to the same. Jan 18 00:27:37 or a mmapped peripheral? Jan 18 00:27:45 Both. Jan 18 00:27:50 yeah Jan 18 00:28:04 I want to be able to write flash. And I want to read from the CPU internal registers. Jan 18 00:28:50 The CPU has SRAM and I cannot even read from that. Jan 18 00:29:00 But, I've only used sysspeed instructions. Jan 18 00:30:00 okay, you've scanned a LDM into the core with sysspeed low, followed by a NOP with sysspeed high? Jan 18 00:30:49 Right. Jan 18 00:31:02 After each one, I go to the Idle state to clock the CPU. Jan 18 00:31:38 okay, make sure you're spending exactly one cycle in r-t-i Jan 18 00:31:38 Then, I load a restart instruction, go back to Idle and wait for the EmbeddedICE status to go SYSCOMP. Jan 18 00:31:52 Yeah, that's true, too. Jan 18 00:32:10 okay, i guess syscomp is immediately high again? Jan 18 00:32:13 What happens if I am passing through Idle once the system goes back to running. Jan 18 00:32:21 I haven't timed it. Jan 18 00:32:41 I'm using a parallel port adapter, so I cannot get that close to the speed of the system. Jan 18 00:32:53 I know that if I forget the syspeed bit, it doesn't come back. Jan 18 00:33:07 yeah, that's what i mean - by the time you read it, it's already high Jan 18 00:33:12 dbgack too? Jan 18 00:33:19 Which reminds me...the documentation on scanchain 1 is really poor. Jan 18 00:33:39 Yeah. I check for both, but the docs make it clear that DBGACK should stay high. Jan 18 00:33:56 ...in order to allow for proper cycle accounting. Jan 18 00:34:30 The docs for scanchain 1 make it seem like the DD fieldis in the MSB bits, but it isn't. Jan 18 00:34:53 Is there something in the text that explains this, or is this just one of those anomolies? Jan 18 00:35:44 one of the arm9 datasheets explains it Jan 18 00:35:45 BTW, I can tell that the LDM instruction is working because it increments the index register. Jan 18 00:35:50 ah, okay Jan 18 00:35:54 I'm going to look for one of them. Jan 18 00:35:58 Like the 926? Jan 18 00:36:08