**** BEGIN LOGGING AT Wed Feb 08 10:59:58 2006 Feb 08 12:16:34 hmm, pci , that would mean a bigger fpga but loose the cpld's and 4 layer pcb so expencive Feb 08 12:18:02 mini pci , ok so for 1 most laptops have one for the wifi so its sort of used Feb 08 12:20:08 pcmia now may be posible but would mean a bga , 4 or 6 layer pcb (at least at that size the cost is not going to be mega expencive Feb 08 12:21:06 Your/Our PC104 solution seems to be good for the immediate need. Feb 08 12:21:11 but the pcmia housing may be , and it would sort of preclude home assemby Feb 08 12:21:16 we can rethink PCI later. Feb 08 12:23:51 if it was not for the fact that it would mean having to use a bga and a 4 to 6 layer pcb , pcmia would be a better choice , as it would allow laptop use and pc use Feb 08 12:33:43 https://portal.fciconnect.com/portal/page?_pageid=335,1577673&_dad=portal&_schema=PORTAL&language=EN < do the pcmia card parts like the conectors /covers etc Feb 08 12:36:04 and recon the price saving in a smaller pcb would cover the extra cost of the caseing needed Feb 08 12:49:27 pci can be a bit inpractial as with a 2' cable lenth on the jtag cable that is going to need a system box on the bench along with everything else Feb 08 12:52:58 the fci search breaks my browser. Feb 08 12:53:05 but I'll take your word for it. :-) Feb 08 13:52:10 if i only put suport for one ram chip , modified the voltage select so that it was programable rather than links , and removed the level translators and have the fpga i/o bank handle that then it would fit on a pcmcia card Feb 08 13:56:18 its just that it will require a diferent way for us to initalise the fpga :s Feb 08 14:12:14 actualy if we dont need a 1.2v logic level option for jtag a pcmcia version my be posible , with some buffers , and may be able to get the jtag top speed to 200Mhz but still only 100 for the la Feb 08 14:15:07 but there may be a better option , if the la functions where droped , and use a couple of large clpd's then it may be posable to impliment it with a 200mhz jtag top speed , in a pcmcia card Feb 08 14:15:44 but thats going to need 3 bga devices Feb 08 14:17:16 it depends on how many microcels the tjag / ram and pcmiabus i/f needs Feb 08 14:19:11 have to admit i like the idea of a pcmcia jtag debug/tester/programmer Feb 08 14:36:31 hmm 300mhz max jtag could be possible Feb 08 14:39:27 in a lot of ways think it makes better sence than a pc104 version , in that it does not require a pc104 sbc , and can work with 99% of all laptops and all pc's with a pcmcia adaptor Feb 08 14:41:48 its the construction requireing bga that will be the biggest problem , so that is going to need it being manfactured as a assembled unit Feb 08 14:43:22 but recon that it may fit within the $250 price range Feb 08 15:25:09 interesting Feb 08 15:26:01 the connector for the PCMCIA care would be the most difficult challenge Feb 08 15:26:34 the Dongle manufacturing might be interesting. Feb 08 15:28:05 nothing says that the card can't be longer than the std one (I'e seen some PCMCIA cards that are 2" longer. Feb 08 15:50:13 one solution might be to create a card that is wider outside of the slot. Feb 08 15:50:42 * ka6sox thinks out loud Feb 08 15:50:50 hmm Feb 08 15:51:50 morning Feb 08 15:51:55 coffee coming up. Feb 08 15:52:49 actualy don think that the probem is needing to extend the board Feb 08 15:53:22 imho its connectorization. Feb 08 15:53:54 there are sutable connectors that can be used for the cable that will fit well into the end of a pcmcia card Feb 08 15:55:29 k Feb 08 15:55:39 since jtag seems to use 3.3v or 2.5v most of the time with 1.8v beeing rare do we need 1.2v support Feb 08 15:56:23 the faster procs use lower voltages to get the speed up and keep the power down. Feb 08 15:57:47 in the future more and more will be going to 1.8v and even 1.2v because of speed issues. Feb 08 15:57:51 k, Feb 08 15:58:34 we have been talking about 240mhz and with double edge clocking we might even be able to do 480mb/sec Feb 08 15:59:05 but even so, and may be better , to mount the buffers on the jtag head , Feb 08 15:59:14 agreed Feb 08 16:00:22 basicaly make the pcmcmia with a 3.3 or other output (whatever gives the fastest rate , and then the buffers on the head can be set to whatever Feb 08 16:00:26 the PCMCIA spec is for 3.3v intercace. Feb 08 16:00:36 ? Feb 08 16:01:22 and is that a 33mhz bus? Feb 08 16:01:27 i need to read the pcmcia spec's after finding that there's 2 Feb 08 16:01:44 I know of pcmcia and pccard. Feb 08 16:01:51 i guess i missed something, what would be the benefit of going through a pcmcia slot? Feb 08 16:02:14 think its a mini version of the something on the lines of pci Feb 08 16:02:25 if there's one interface that everyone has, it's usb or ethernet, imho Feb 08 16:02:34 i know theres a 5v and 3.3v Feb 08 16:03:14 the problem with both of those is that we need a Processor in the Pod Feb 08 16:03:33 (usb/ethernet) Feb 08 16:03:38 and it drives up the cost. Feb 08 16:03:43 lennert: true , but you could say pci also , but that exludes laptops , and you can get a pcmcia to pci adaptor for a pc Feb 08 16:03:55 cheaply Feb 08 16:04:10 and most laptops have a pcmcia Feb 08 16:04:25 the problem that the POD helps is getting keeping the cables short. Feb 08 16:04:27 so to use this card on my desktop i have to get a pcmcia adapter Feb 08 16:05:26 yes Feb 08 16:05:43 ethernet/usb are more ubiquitous. Feb 08 16:07:01 the problem with the buffer cards is the HOT plugging. Feb 08 16:07:09 yes , but the cost penalty for using a ethernet means a local cpu that adds well a ts200 to the cost Feb 08 16:07:24 7200 Feb 08 16:07:29 agreed Feb 08 16:08:23 and although the cost of a pcmcia may be a bit higher it can still be cheaper than the pc104 board and a ts7200 Feb 08 16:08:27 building a all FPGA solution with ethernet (external) is very costly (a huge chip) and still have to put in a sof core. Feb 08 16:08:39 s/sof/soft Feb 08 16:09:32 going to push it towards $300 for the system with cables/adaptersl. Feb 08 16:09:47 back in a bit Feb 08 16:11:17 and the main problem with a pcmia cost is the pcb , that would need to be 4 layer , the components used are not going to cost any more than we would currently be using on the pc104 card Feb 08 16:12:03 and think that it may be arround the $170 mark , Feb 08 16:13:12 there are a number who will want the pod even at the higher cost. Feb 08 16:13:27 for a number of reasons Feb 08 16:14:02 familiarity/ethernet/ closer to target/ stand alone capability/ etc Feb 08 16:14:34 yes Feb 08 16:15:28 but guess a laptop with one fitted could get close to the target Feb 08 16:19:13 and if you think about it a laptop is stand alone and self powered and portable Feb 08 16:20:11 well if the device is pcmcia based, there is no reason you couldn't insert it into an embedded device and use it from there Feb 08 16:20:54 the advantage i feel that it could offer is a cross platform driver Feb 08 16:21:07 you could just as well take one of these cheap wireless ap's that have a pcmcia slot inside and shove it in Feb 08 16:23:06 back in 30 Feb 08 16:23:44 AchiestDragon: NO, get back here now! Feb 08 16:43:53 :) Feb 08 16:44:01 cya laters guys..off to work! Feb 08 17:17:14 ~seen beewoolie Feb 08 17:17:25 beewoolie was last seen on IRC in channel #openjtag, 6d 8h 28m 56s ago, saying: 'later.'. Feb 08 17:17:30 ~seen beewoolie-afk Feb 08 17:17:32 beewoolie-afk was last seen on IRC in channel #openjtag, 4d 10h 45m 27s ago, saying: 'NN'. Feb 08 18:19:26 back Feb 08 18:30:41 well i could work out the schematics and pcb for a pcmcia version , then we have two options ether make one or the other or both but can decide that later Feb 08 18:31:55 at least with 2 designs done we will be able to evaluate the costs of each Feb 08 18:37:27 think the software is going to be easyer if its all on one machine also Feb 08 18:50:55 ka6sox-office: ping Feb 08 20:20:59 ok so theres the 16bit pcmica and the 32bit cardbus version , support for both should be possible , but as pcmica is 5v and card bus 3.3v then the problem is how to get a jumper onto a pcmica card Feb 08 20:35:39 <[g2]> anyone know rs232 range ? Feb 08 20:36:07 -12V +12V ? Feb 08 20:36:16 where -12V is a logical '1' Feb 08 20:36:21 and +12V is a logical '0' Feb 08 20:36:25 very confusing at first Feb 08 20:37:07 but +-5v should mostly do, afaik Feb 08 20:37:29 <[g2]> I see a -5.5v Feb 08 20:37:31 my ts7250 generates +/- 4.8V, even Feb 08 20:38:15 <[g2]> so if I say 5V is VCC then I might see a signal on the level shifter Feb 08 20:39:05 <[g2]> or if I just plug the -5.5V and GND right ? Feb 08 20:43:13 EPARSE Feb 08 20:46:51 <[g2]> Ok cool Feb 08 20:46:53 <[g2]> thx Feb 08 20:49:23 [g2]: can you please rephrase what you said? Feb 08 20:57:56 [g2]: did i piss you off? Feb 08 20:58:16 <[g2]> lennert no sorry not at all! Feb 08 20:58:31 <[g2]> I just got the 1st boot log from the dsm-g600 Feb 08 20:58:41 <[g2]> RedBoot and kernel log Feb 08 20:58:50 <[g2]> sorry I was distracted Feb 08 20:59:00 ok, np Feb 08 20:59:04 i was just afraid i pissed you off Feb 08 20:59:19 i'd be glad to answer your question but i didn't get what you meant Feb 08 20:59:41 <[g2]> lennert you'd have to use my nuts as a trampoline to start annoying me Feb 08 20:59:48 lol Feb 08 21:00:03 <[g2]> so back the issue Feb 08 21:00:27 <[g2]> the signals are already level shifted to -5.5V Feb 08 21:00:41 <[g2]> hence no extra parts are required Feb 08 21:00:56 i guess that's a safe-ish assumption Feb 08 21:00:57 <[g2]> I just connected the GND pin to GND 5 on the DB-0 Feb 08 21:01:04 <[g2]> s/-0/-9/ Feb 08 21:01:05 [g2] meant: I just connected the GND pin to GND 5 on the DB-9 Feb 08 21:01:16 2, 3, 5 is all you need Feb 08 21:01:28 <[g2]> and the TX pin from the board to Pin 2 Feb 08 21:16:23 generating +- 5v for rs232 works , but it depends on distance , the originlal +- 12v was used because the teminal could be up to 250' away from the processor so voltage drop over the cable was a problem Feb 08 21:18:37 the original full rs232c standard was a nightmare , there was 2 async ports and a syncronus plus 20ma loop modes on the 25way d type Feb 08 21:21:29 i worked out one day that you needed a set of 4096 possible cables to ensure that you had the right configureation , thats before you include the baud rate and start stop bit combinations Feb 08 21:43:27 hmmm, ok so a tight fit but how does this sound Feb 08 21:46:31 both logic analizer and jtag functions as the AzTag pc104 board , on a pcmia / cardbus , but with a top speed of 200mhz in logic analizer mode , and possabaly 300 in jtag Feb 08 21:48:02 down side is the use of 4 devices in bga packages Feb 08 21:50:46 although i feel the cableing could cause problems above 170mhz Feb 08 21:54:39 <[g2]> lennert FYI http://forum.openwrt.org/viewtopic.php?id=4338 is the RedBoot and kernel log at the bottom Feb 08 21:55:41 dsm/ Feb 08 21:55:41 ? Feb 08 21:58:29 <[g2]> D-link box Feb 08 21:59:07 <[g2]> GigE, 64MB 266 IXP425, 16MB Flash, MiniPCI, IDE 2 USB 2.0 ports $149 for Rev A Feb 08 21:59:12 <[g2]> Rev B is PPC :( Feb 08 21:59:34 right Feb 08 21:59:49 * lennert wonders why they changed to ppc Feb 08 22:00:49 which ppc chip? Feb 08 22:05:56 <[g2]> Dunno Feb 08 22:06:07 <[g2]> It's probably on the forum or web Feb 08 22:07:16 <[g2-lap]> we should add this page to the wiki http://hri.sourceforge.net/tools/jtag_faq_org.html Feb 08 22:28:22 http://www.whipy.demon.co.uk/pcmcia.pdf Feb 08 22:29:50 [g2-lap], you have the power to add that. **** BEGIN LOGGING AT Thu Feb 09 00:23:39 2006 Feb 09 00:45:24 http://nslu2-linux.thestuffguy.com/gallery/dsmg600 Feb 09 00:45:26 http://nslu2-linux.thestuffguy.com/gallery/dsmg600revb Feb 09 00:46:00 XPC8241LZP200B Feb 09 00:47:18 I returned the RevA because it was $10 less than the lude, but the lude came with the 160G disk Feb 09 01:09:07 i worked with the 8241 at my old job Feb 09 01:09:37 a bit long in the tooth - note the datecode is 0332! Feb 09 02:41:00 canse why they changed it though , theres a significant component count diference between the two , that will save on manufacturing costs in the long run Feb 09 02:41:25 /canse / can see Feb 09 09:51:32 ka6sox: ping **** ENDING LOGGING AT Thu Feb 09 10:59:56 2006