**** BEGIN LOGGING AT Wed Feb 15 10:59:56 2006 Feb 15 12:07:29 ka6sox pong Feb 15 12:08:32 ka6sox: ping Feb 15 12:19:38 ka6sox: what's the address space size on PC/104? Feb 15 12:21:55 i'm guessing 1MB ? Feb 15 12:27:02 16 bits 64k Feb 15 12:27:47 its limited by the i/o pins that where avalable on the fpga Feb 15 12:28:01 well, i'm wondering in general Feb 15 12:28:16 as the ts7250 seems to have 22 PC/104 address lines which seems a bit too much Feb 15 12:29:52 actualy the ts7200 has a odd address scheem in that one address range is for 8 bit accesses and one for 16 it works out that in each range there is a 1mb address space Feb 15 12:31:32 the fpga access is all done in 16bit mode , the jtag for the fpga is done in the 8 bit access Feb 15 12:34:47 rember the i/o map and memory access register space for the fpga is all to be in the 64k range Feb 15 12:35:41 ts7200 is kind of an odd board in general Feb 15 12:35:49 do you have the ts7200 or the ts7250? Feb 15 12:36:01 ts7200 Feb 15 12:37:58 so are you supposed to do 32bit cycles in the 8/16 bit pc/104 ranges? Feb 15 12:38:05 that would explain why those ranges are 4M large each Feb 15 12:38:07 the aztag board has a board select for its address space so it should be possible to have upto 16 boards although 3 would be real max , as theres only 3 interupt lines Feb 15 12:39:06 i have the ts7250 for a project unrelated to jtag Feb 15 12:43:14 i think the main diference betwen the ts7250 and the ts7200 is the 7200 has a cf port where the 7250 has some onboard flash Feb 15 12:45:42 think both would work with the aztag but the c/f could be useful for the software to reside in ,, altough a usb memory stick or usb hdd would work for that just as well Feb 15 12:51:12 the 7250 has 32m of nand flash, yes Feb 15 13:15:35 hi prpplague Feb 15 13:24:49 hey Feb 15 13:59:38 "The other DIO pins have 100 KW bias resistors biasing these inputs to a logic “1”." Feb 15 13:59:56 my ts7250 has 4 100KW resistors Feb 15 14:00:06 you think i could use it to heat my house? Feb 15 14:05:32 Probably. Feb 15 15:29:22 * ByronT_ is back after 3h27m: home! Feb 15 18:18:47 morning Feb 15 18:20:47 lennert: remind me to bring my personal Chiller when I go to your house. Feb 15 18:26:37 ka6sox-office: actually, it seems the heating is broken, it's damn cold inside Feb 15 18:35:21 das bee in the house Feb 15 18:35:39 doodz Feb 15 18:36:47 beewoolie-afk: whats cookin? Feb 15 18:36:56 yo! Feb 15 18:36:58 Still working on the JTAG software. Feb 15 18:37:12 I got a response from the FTDI folks that explains what I didn't understand. Feb 15 18:37:30 beewoolie-afk: cool Feb 15 18:37:31 Of course, their documentation does say something about it, but I was too stubbron to believe. Feb 15 18:38:35 what..you have experienced doco that doesn't match reality? Feb 15 18:39:12 beewoolie-afk: what item was it? Feb 15 18:39:26 It's that I just cannot believe it. Feb 15 18:39:40 do tell Feb 15 18:39:42 The FTDI protocol uses a bit-by-bit encoding for sampling. Feb 15 18:40:22 When we want to drive a signal for a rising TCK pulse, such as TMS or TDI, we want to change the state of that signal on the falling pulse. Feb 15 18:40:32 That's how I've written all of the parallel port code. Feb 15 18:40:39 Well, they cannot do it that way. Feb 15 18:41:15 If we want to change the state of the TDI line on a falling TCK, we must start TCK low. Feb 15 18:41:40 Their opcode has a peculiarity in that they drive the first output bit before clockin the first bit in. Feb 15 18:41:55 But that means that there won't be time for the value to settle at very high clock rates. Feb 15 18:42:21 I don't think that's an issue since they cannot go faster than 6MHz, but I haven't checking the timing. Feb 15 18:42:32 what I really need is an LA to examine the signals. Feb 15 18:42:45 beewoolie-afk, give us time :) Feb 15 18:42:51 were working on it! Feb 15 18:43:08 :-) Feb 15 18:43:21 Their protocol also doesn't play well with TMS. Feb 15 18:43:36 We must drive TMS 7 times if we use the opcode to do so. Feb 15 18:43:55 To make matters worse, I have to use that opcode one cases Feb 15 18:43:59 s/cases/case Feb 15 18:44:54 The bottom line is that their protocol is not very efficient. They made some naive choices. Feb 15 18:45:21 Even considering that their protocol isn't just for JTAG, there are things that could have been done much more cleanly. Feb 15 18:45:38 The cost is extra bytes in the stream. Feb 15 19:02:08 I'm wondering if they were just padding out since the USB frame is soo big Feb 15 19:02:28 IMHO, these are oversights in the design. Feb 15 19:02:50 If I am going to perform a very large data transfer to the device, it doesn't matter how big the frame is. Feb 15 19:03:03 true Feb 15 19:03:04 Especially, the TMS one. Feb 15 19:03:08 yes Feb 15 19:03:21 It means that I have to find ways to burn up TMS transitions. Feb 15 19:03:32 ugh Feb 15 19:03:56 Moreover, I don't know the final state after a DR command until that command is completed. Feb 15 19:04:11 But I would have to drive the TMS bits as part of the read. Feb 15 19:04:33 It turns out that there is a convenient loop in Pause, so I can always send the TAP there after reading the regisgter. Feb 15 19:04:51 It looks like the code is working, now. Feb 15 19:05:01 w00t Feb 15 19:05:05 Yeah. Feb 15 19:05:39 I need to finish testing of the JTAG higher-level routines, but once the driver works, the rest should all fall out Feb 15 19:16:22 <[g2]> ain't this a treat! Feb 15 19:16:31 <[g2]> beewoolie-afk during the day Feb 15 19:17:08 :-) Feb 15 19:17:10 Morning even Feb 15 20:57:56 hi dwery-zzzz ;) Feb 15 20:58:04 NAiL: hi :) Feb 15 20:58:10 I've been told you've a question... Feb 15 20:58:16 haha Feb 15 20:58:17 yes Feb 15 20:58:31 Do you know the answer? :-P Feb 15 20:58:33 Anyway Feb 15 20:58:36 me not Feb 15 20:58:37 but Feb 15 20:59:03 you must know Feb 15 20:59:09 that people in this channel Feb 15 20:59:11 huh? Feb 15 20:59:26 masters Feb 15 20:59:30 the jtag foo :) Feb 15 20:59:41 hehe Feb 15 21:01:47 But, what I really want to know is whether or not it is possible to get the "bits" out of a CPLD on the DS101 pcb. Feb 15 21:02:09 i think you must name the cpld maker and model :) Feb 15 21:02:35 yes, it's a lattice LC4032V Feb 15 21:02:43 (75-10I) Feb 15 21:03:34 ok, now you have to meditate a couple of days and then the answer will come Feb 15 21:03:36 maybe :) Feb 15 21:04:01 I know ;) Feb 15 21:04:10 if it were a xilinx spartan3 .bit file i could probably help Feb 15 21:04:21 but alas Feb 15 21:04:35 hehe Feb 15 21:05:27 dwery-zzzz: Anyway, there's gotta be something in the original source that can help... Feb 15 21:05:37 I've been looking at the diff for two days now :-P Feb 15 21:06:22 eheh.. it's not easy... Feb 15 21:07:11 aha Feb 15 21:07:56 look at this snippet: http://pastebin.com/556558 Feb 15 21:08:58 If I understand it correctly, it "inits" CD0 (ie, 0x500000000) Feb 15 21:09:08 ie, the exp. bus Feb 15 21:09:38 Is this the code I've been tearing out my hair to find? Feb 15 21:10:03 (please say yes, and mean it! ;) Feb 15 21:11:18 let's switch channel, as this is no more jtag :) Feb 15 21:11:26 ah, yes Feb 15 22:50:34 * fishhead thinks it's time to leave freenode for good, he has had enough of the bullshit Feb 15 22:56:51 ok, everyone just stfu about how I am, or why I want to leave, that shouldn't have been a global /me earlier Feb 15 23:02:51 ? Feb 15 23:06:27 don't worry... Feb 15 23:06:35 this guys is kinda....ya know Feb 15 23:11:41 what? Feb 15 23:34:21 lennert: Do you know much about endianness on the ixp? :) Feb 15 23:39:22 a bit :) Feb 15 23:40:00 I might have an endianness issue accessing the expansion bus Feb 15 23:56:36 shoot Feb 15 23:57:02 Nah, I'll try getting it running in BE first. There's still something missing I think. Feb 15 23:57:13 okay Feb 15 23:57:29 getting ixp2000 running in LE is still on my list Feb 15 23:58:15 yeah. I can get everything working except the DoC (and network, since the mac address is stored in flash) Feb 15 23:58:26 but mine's a 420, not 2000 ;) Feb 15 23:59:37 :) Feb 15 23:59:51 the ts7250 has the MAC in flash too, wonder how i'm supposed to get that out Feb 16 00:00:07 well, it's not DoC is it? ;) Feb 16 00:01:11 no, it's friggin NAND flash with docs on _where_ the data/control/busy registers are but not what the format of the control register is Feb 16 00:01:36 heh, that's bright Feb 16 00:06:21 lennert: Where are these docs? Feb 16 01:33:12 beewoolie-afk: the TS-7250 docs at www.embeddedarm.com Feb 16 01:35:46 lennert: Hmm. I don't have time to look through all of it at the moment. Feb 16 01:35:53 I was just wondering about their NAND interface. Feb 16 01:36:04 I'd like to support NAND flash IO in the JTAG application. Feb 16 01:38:59 beewoolie-afk, get the 7200 instead...more flexibility Feb 16 01:39:00 :) Feb 16 01:39:08 :-) Feb 16 01:43:11 * NAiL is running out of ideas Feb 16 01:43:20 lennert: It looks like they don't wire the JTAG port on the CPU. Feb 16 01:43:38 Or am I missing something about the schematic? Feb 16 01:43:48 lemme checki Feb 16 01:43:50 on the ts7200 only the cpld is wired Feb 16 01:44:08 I'm looking at the 7250. Feb 16 01:44:26 It's kinda screwy. Feb 16 01:47:55 NAND flash isn't so hard to interface with Feb 16 01:50:23 you know how NAND works? (if not, read http://www.dataio.com/pdf/NAND/Toshiba/NandDesignGuide.pdf.pdf) Feb 16 01:50:40 I've written a NAND driver for APEX. Feb 16 01:50:41 then, there are basically three registers in the ts7250 implementation -- data, control and status Feb 16 01:50:48 data is what you read/write from/to Feb 16 01:50:49 I just wanted to see how they implemented it Feb 16 01:50:53 control has the nCS bit, the ALE and CLE Feb 16 01:51:01 It may be moot since we don't have control over the CPU's scan chain. Feb 16 01:51:08 right Feb 16 01:51:16 A damn shame. Feb 16 01:51:19 you need to be able to do byte reads/writes to three different locations in the 32bit memory map Feb 16 01:52:21 beewoolie-afk: hey, write DoC support for APEX too ;) Feb 16 01:52:43 NAiL: I'd be glad to...if I had something with DoC on it. Feb 16 01:52:53 yeah Feb 16 01:53:24 IIRC, DoC isn't much more than I already have. Feb 16 01:53:59 It's got a built-in checksum thingy. And there is a documented format for the extra page bytes. Feb 16 02:09:36 I just get a kernel panic on the first write to the DoC Feb 16 02:10:17 Whoops Feb 16 02:11:02 yeah... Trying to figure out why, but not I'm not getting much further Feb 16 02:11:57 I've never used the kernel DoC driver. Feb 16 02:12:07 I only ever used the binary module implementation. Feb 16 02:12:34 ah Feb 16 02:14:09 I've got a 2.4-kernel where the driver works, but the drivers are wildly different from the ones in the 2.6-kernel. Feb 16 02:14:59 I've never tried the 2.6 stuff. I did this work several years ago, on an X86 embedded target. Feb 16 02:33:26 ka6sox-office: A feature request. Feb 16 02:33:32 k Feb 16 02:33:40 I'd like to be able to do back-to-back transfers with the FPGA implementation. Feb 16 02:33:51 There should be no need to delay clock cycles between each operation. Feb 16 02:34:10 This will probably require that the TCK line be driven high by default. Feb 16 02:34:23 I write this because the FTDI cannot do this. Feb 16 02:34:41 According to ep1220, there are several clocks between each opcode. Feb 16 02:35:10 In addition, it has to wait for a half cycle setup time for each write opcode because they default to a low clock. Feb 16 02:40:23 hmm Feb 16 02:40:36 okay I'll put that in. Feb 16 02:40:40 (I want it anyways!) Feb 16 02:41:17 is the lack of JTAG on the ts72xx going to be a problem? Feb 16 02:41:42 no Feb 16 02:41:47 not an issue Feb 16 02:42:03 we are not going to replace the bootloader at this time. Feb 16 02:42:12 says you. Feb 16 02:42:36 I said *(we)* and that does NOT include you! ;) Feb 16 02:43:09 I'd have to actually see one before I make the statement that we can't do it. Feb 16 02:43:29 I don't know ;) Feb 16 02:45:41 but I will work with it when I get one. Feb 16 02:50:50 back in a bit...work calls :( Feb 16 02:51:04 :-) Feb 16 02:51:50 ok, it crashes when trying to write to 0xc4860000 Feb 16 02:53:34 That is an evil address. Feb 16 02:54:12 ? Feb 16 02:54:38 because it makes it crash? ;) Feb 16 02:58:27 C4. Explosive Feb 16 02:58:43 well the ram on the hat board routes ok , needs 5 layers though so got 5 layers and 1 gnd plane layer Feb 16 02:58:47 86 -> slang for 'the trash' Feb 16 02:58:55 Explosive trash! Feb 16 02:59:27 http://www.whipy.demon.co.uk/hatpcb.pdf Feb 16 03:05:36 AchiestDragon: rockin Feb 16 03:14:40 heh.. Feb 16 03:14:43 274 /* Feb 16 03:14:43 275 * bad_mode handles the impossible case in the vectors. If you see one of Feb 16 03:14:46 276 * these, then it's extremely serious, and could mean you have buggy hardware. Feb 16 03:14:50 277 * It never returns, and never tries to sync. We hope that we can at least Feb 16 03:14:53 278 * dump out some state information... Feb 16 03:14:54 yay. Feb 16 03:15:50 That's when I get when it tries to write Feb 16 03:39:47 <[g2]> beewoolie-afk lennert tells the the 7250 support the boot from serial option Feb 16 03:39:57 Handy. Feb 16 03:39:58 <[g2]> so replacing the bootloader is trivial Feb 16 03:40:11 <[g2]> it's on the Cirrus dev boards and the glomation Feb 16 03:40:17 I'm also interested in testing the JTAG adapter we're building. :-) Feb 16 03:40:25 <[g2]> me too Feb 16 03:40:36 <[g2]> the glomation board has a 20-pin JTAG Feb 16 03:40:48 I replied to your reply. Feb 16 03:41:00 <[g2]> I saw that Feb 16 03:41:26 <[g2]> were you just restating your issue ? Feb 16 03:41:49 Just clarifying that the bit in question is bit 1 and not bit 0 as you wrote. Feb 16 03:43:14 <[g2]> Ah... I think I just cut-n-pasted Feb 16 03:47:38 ttfn Feb 16 06:14:59 yawn Feb 16 06:15:10 missed bee...later Feb 16 10:56:22 indeed, jtag pins on ts72xx aren't brought out ;( **** ENDING LOGGING AT Thu Feb 16 10:59:56 2006