**** BEGIN LOGGING AT Mon Mar 20 10:59:57 2006 Mar 20 14:22:21 is it possible with a virtex2 that has 2 powerpc in it, to run a linux that uses both proc ? Mar 20 14:25:45 key2: no Mar 20 19:09:51 p2-mate: why not ? Mar 20 19:12:46 key2: the 405 does not support cache coherency between processors Mar 20 19:29:55 sux Mar 20 19:30:04 so it's possible to run 2 separated linux ? Mar 20 19:30:31 yes Mar 20 19:30:35 that should be possible Mar 20 19:31:56 and since the two PPC are hardcore, there is no way to make a cache coherence I guess Mar 20 19:32:10 hardcoded Mar 20 19:32:18 I don't think so no Mar 20 19:32:38 p2-mate: u've already ran a linux on a xilinx ? Mar 20 19:33:12 key2: yes Mar 20 19:33:29 on what board ? Mar 20 19:33:33 digilent one ? Mar 20 19:33:35 ml403 Mar 20 19:34:04 not on that one no Mar 20 19:34:14 but it shouldn't make much difference Mar 20 19:34:14 but that should also be possible right ? Mar 20 19:34:18 sure Mar 20 19:34:42 how many PPC in the ml403's xilinx Mar 20 19:34:42 ? Mar 20 19:34:50 only 1 Mar 20 19:35:07 like the blackdog Mar 20 19:35:59 a collegue has done ecos and linux on dual core xilinx fpga. I don't know on which board though Mar 20 19:36:27 p2-mate: mmmmm virtex Mar 20 19:36:52 lennert: yep :) Mar 20 19:36:58 well what else :) Mar 20 19:37:19 * lennert still needs to do some serious stuff with his v2pro board Mar 20 19:37:30 all i did so far was an fm transmitter with the 8bit vga dac :P Mar 20 19:37:30 lennert: which board do u have ? Mar 20 19:37:39 lol Mar 20 19:44:22 p2-mate: and basically, how do u do for putting a linux on it ? I mean if the PPC is just a core inside the virtex, I guess u have at least to say where the GPIO is, where the DDR is, dunno if there are already some DDR driver built into the core or not so you might have to use one or write it... Mar 20 19:44:59 key2: you need a FPGA design which has a memory controller, UART, GPIO etc yes Mar 20 19:45:21 there are already drivers for most of the xilinx provided blocks Mar 20 19:45:44 so it's a matter of assigning the right addresses Mar 20 19:46:00 p2-mate: so you have to change the kernel Mar 20 19:46:10 and say where are the addresses of the different chips? Mar 20 19:46:13 the DDR memory needs to be at address 0 Mar 20 19:46:20 yes, basically Mar 20 19:46:31 ok Mar 20 19:46:53 and there are already designs with MC, UART, GPIO ? Mar 20 19:47:05 or have to make them ? Mar 20 19:51:44 there are reference designs on the xilinx website yes Mar 20 20:21:56 and there are kernel already configured for that ? Mar 20 20:22:30 I mean It won't be enough to just take a crosscompiler and compile the kernel i guess Mar 20 20:33:25 key2: iirc most of the support is in the standard tree by now Mar 20 21:12:38 * ByronT-Away is now auto-away after 3h idle Mar 20 21:14:56 p2-mate: i didn't quite like the xilinx license on the plb cores when i looked at it Mar 20 21:16:16 they are by no means free indeed Mar 20 21:16:29 OTOH I don't know about any free PLB cores Mar 20 21:16:37 maybe it's time someone wrote some :-) Mar 20 21:16:46 feel free :) Mar 20 21:17:08 i have some evil-licensed intel microcode to rewrite first :) Mar 20 21:17:48 for ? Mar 20 21:18:06 ixp2300 Mar 20 21:18:11 ah Mar 20 21:18:36 at least there are gratis tools for that one iirc Mar 20 21:19:16 yeah, that's another thing that bugs me about xilinx Mar 20 21:19:47 i still don't like the intel license on their s/w so i reverse engineered the insns format and wrote a different assembler :-) Mar 20 21:19:47 well altera isn't any better I think Mar 20 21:20:06 true Mar 20 21:20:34 there's one brand that give away their tools.. lattice? Mar 20 21:20:39 can't remember now Mar 20 21:22:26 lattice ? hmm Mar 20 21:24:42 lennert: ixp2300 ?? Mar 20 21:24:54 the network ctrl ? **** ENDING LOGGING AT Tue Mar 21 10:59:57 2006