**** BEGIN LOGGING AT Fri Jul 14 02:59:57 2006 Jul 14 11:51:35 hey Jul 14 11:51:51 someone knows a chip that does h264 (mpg4) codec ? Jul 14 21:30:27 hey guys Jul 14 21:30:50 hey p2-mate... long time no see =] Jul 14 21:31:48 I was investigating a low-cost, easy and fast DIY EJTAG probe and I stumbled across the site you guys set up Jul 14 21:42:14 Anyone know if a JTAG adapter board using the FT2232 was ever built? Jul 14 21:42:27 I read about plans for it in an irc log of july last year Jul 14 21:55:41 Griffon26: I'm using it for ARM7/9 and XScale debugging Jul 14 21:56:14 you can even get one prebuilt from Amontec or (soon) from Olimex (sparkfun in the US) Jul 14 21:56:48 and this is using the DLP-2232M? Jul 14 21:57:07 they're both using the FT2232C, and I have a homebrew device with the DLP-2232M, yeah Jul 14 21:57:29 you basically only need level-shifters for non-5V targets Jul 14 21:57:55 yeah, I read about that Jul 14 21:58:46 do you have something I can google for to find prices? Jul 14 21:59:23 Amontec's JTAGkey is rather expensive (www.amontec.com, ~150$), but the Olimex dongle is supposed to sell for around 60$ Jul 14 21:59:35 though it's not available yet, but should be mid-july Jul 14 21:59:46 either way, you'll have to write software for the EJTAG stuff Jul 14 22:00:08 yeah.. as long as full specs are available, that shouldn't be a problem Jul 14 22:00:50 afaik EJTAG is well documented, and the FT2232C comes with a detailed description of the MPSSE (multi-protocol synchronous serial engine) used for JTAG Jul 14 22:01:09 the mpsse stuff is in an appnote available from ftdichip.com Jul 14 22:01:16 first I have Jul 14 22:01:36 let's hope it becomes a trend Jul 14 22:01:43 JTAG probe prices are outrageous Jul 14 22:02:17 yeah... but the money really isn't in the hardware, but the software driving it Jul 14 22:02:27 I was wondering though... is the speed limit in USB or something else? because it's only using full speed Jul 14 22:02:38 vmaster: I don't want the software... and I can't get a probe without it =] Jul 14 22:03:05 so anyway, I'm trying to get together an open probe and open software Jul 14 22:03:17 the FT2232C itself is more limitng than the USB 1.1 Jul 14 22:03:55 on my arm7/9 systems, i can get about 120kb/s download to target RAM, which equals about 1.5MHz effective TCK rate Jul 14 22:04:28 that's a shame Jul 14 22:04:58 oh well, a Wiggler does ~300kHz, so it's at least something Jul 14 22:05:12 definitely better than a wiggler =] Jul 14 22:05:56 atm I'm working on a bootloader (I work on embedded sw in my job) and it can't go fast enough Jul 14 22:08:09 I wonder if FTDI is working on a Hi-speed version Jul 14 22:08:27 mhh, i guess that wouldn't change too much Jul 14 22:08:53 if you want to achieve a lot more than the 120kb/s on an ARM7 for example you'd have to shift more logic into the JTAG probe Jul 14 22:09:10 how so? Jul 14 22:09:29 because often you're waiting for data to transmit back to the host, and even with USB 2.0 you have 125us latency Jul 14 22:09:59 like i have to poll some bits to see if the core completed the current operation Jul 14 22:10:38 I must admit, I have not found much about what a download is really doing with JTAG. Do you have any docs on this? Jul 14 22:11:15 IIRC, downloading stuff to memory was part of EJTAG, not JTAG (at least for MIPS), is that right? Jul 14 22:11:22 it really depends on your target architecture - i can only speak for the ARM7/9 and XScale (both are rather different) Jul 14 22:11:47 isn't EJTAG just what travels through JTAG? Jul 14 22:12:00 there are some extra commands Jul 14 22:12:09 same pins Jul 14 22:12:16 although... Jul 14 22:12:50 with jtag , you should be able to do tasks like , programming the device , boundry scan this gives you state info about the pins on the device ,, with cpus you should be able to get at the debug functions through jtag Jul 14 22:15:23 i just checked the EJTAG specs, and EJTAG really uses the JTAG TAP (test access port) to provide the debug functionality Jul 14 22:15:28 so it's more a naming issue Jul 14 22:15:37 got it... jtag has only 4 mandatory instructions and 6 optional ones Jul 14 22:15:49 ejtag has more instructions for accessing the bus of the device Jul 14 22:16:28 yeah, but that's just what they all do - noone's using the mandatory JTAG instructions for debugging Jul 14 22:17:00 that just means that data transfer to memory is always device specific, right? Jul 14 22:17:05 but the mode of operation remains the same, i.e. you select a JTAG instruction, and serially scan data into the device in Shift-DR Jul 14 22:17:09 right Jul 14 22:17:38 so what kind of communication does it involve for arm? Jul 14 22:17:53 lots of acks to wait for? Jul 14 22:19:51 on the ARM you have access to the data/instruction bus - you scan an instruction in, move through Run-Test/Idle to clock the core, so the instruction is "fetched", and then clock the instruction through the pipeline Jul 14 22:20:12 when for example a store-multiple instruction is in the execute stage, you can read the register content from the databus Jul 14 22:20:47 and for memory accesses, you scan in the desired load/store, make the core synchronise back to the memory clock, and wait for it to reenter debug state Jul 14 22:21:28 due to memory wait states, cache effects, and limitations on when the core might switch clocks, you don't know when it's back in debug state, so you have to poll Jul 14 22:21:38 you mean you have an ack for each word? Jul 14 22:21:54 you can read/write 14 words at a time Jul 14 22:22:02 so you have on ack for 56 byte Jul 14 22:22:24 ok Jul 14 22:22:47 you can also pretend that the core is always going to be faster than your JTAG interface, but that only holds when the processor is about ten times faster than the JTAG clock Jul 14 22:23:26 and Philips ARM's for example start with a ~14MHz crystal Jul 14 22:23:39 so there are times when you have to poll anyway Jul 14 22:24:26 although the max jtag rate on something like the ppc is 1/16th that of the cpu clock Jul 14 22:26:07 yeah, there are all kinds of restrictions, but my point was that you can't avoid polling in some cases Jul 14 22:26:14 but at 1.6Ghz thats a 100mhz jtag clock Jul 14 22:27:17 i have not looked but wonders what the spec is for the intel and amd chips jtag Jul 14 22:27:30 if they have it Jul 14 22:28:35 Griffon26: you can find my ARM7/9 (and soon XScale) debugger (oss) together with my thesis paper on ARM7/9 debugging at http://openocd.berlios.de/web/ - the JTAG layer would be suitable for EJTAG, too Jul 14 22:28:59 ah, ok, that would be nice *bookmark* Jul 14 22:29:04 what license btw? Jul 14 22:29:39 GPL Jul 14 22:30:22 the thesis documents an old version of the code, which has seen major improvements, but the theory remains the same Jul 14 22:30:54 thumbs up Jul 14 22:39:43 thanks for your insights. Bye for now Jul 14 22:40:03 yeah, cya... i'm off, too **** ENDING LOGGING AT Sat Jul 15 02:59:56 2006