**** BEGIN LOGGING AT Wed May 02 02:59:56 2007
May 02 11:51:17 <[g2]> http://www.sparkfun.com/commerce/product_info.php?products_id=8307# looks fun :)
May 02 12:30:20 <drath> hey [g2] 
May 02 12:30:28 <drath> yeah, just another FT2232 based dongle afaik
May 02 12:30:52 <drath> but that guy also has his own debugging software
May 02 12:44:02 <[g2]> drath, it's supposed to run with openocd
May 02 12:48:28 <drath> yeah, if he's using one of the included FT2232 pin configurations this should be no problem
May 02 15:22:11 <xela> Hey, drath
May 02 15:26:09 <drath> hey xela
May 02 15:26:13 <drath> sorry, been a bit busy last week
May 02 15:26:19 <xela> no problem
May 02 15:26:47 <xela> seems like we still have the STR750 flash error issue
May 02 15:26:58 <xela> only every other flash works without error
May 02 15:27:22 <xela> (jtag-tiny/jtag-amontec plus target and REva hardware)
May 02 15:28:43 <drath> you don't happen to have a backlog of our irc session?
May 02 15:29:21 <xela> na
May 02 15:29:33 <xela> hoped some daemon would log them :-(
May 02 15:29:48 <xela> cause i found some transcripts on the internet
May 02 15:29:53 <drath> iirc it was something about the algorithm timing out, because the PC goes off into the weeds
May 02 15:29:59 <drath> ah, sure
May 02 15:30:09 <drath> purl logs everything
May 02 15:32:20 <xela> yea
May 02 15:36:22 <xela> the guys from Raisonance state the JTAG timing for the STR750 is different
May 02 15:36:33 <xela> dont know whether that may be the reason
May 02 15:37:09 <drath> hmm, the STR750 is a -S core, which either requires the use of RTCK (not possible with the FT2232) or a jtag frequency of less than 1/6th of the CPU
May 02 15:37:27 <xela> ah ok
May 02 15:42:52 <xela> drath: http://purl.rikers.org/%23openjtag/20070321.html.gz
May 02 15:42:58 <xela> :-)
May 02 15:55:24 <drath> yeah, I downloaded the logs and grepped through them
May 02 15:55:33 <drath> problem is I don't know what else to check
May 02 15:55:50 <xela> maybe i debug direct in openocd?
May 02 15:56:07 <drath> is it failing exactly every other try?
May 02 15:56:12 <xela> yep
May 02 15:56:39 <drath> what's your current reset_config?
May 02 15:57:26 <xela> trst_and_srst srst_pulls_trst
May 02 15:58:17 <drath> could you try without srst_pulls_trst, and issue a "reset halt"
May 02 15:58:22 <drath> with the latest SVN revision
May 02 15:58:40 <drath> i've changed something that might allow debug out of reset on the str750
May 02 15:59:09 <xela> is there a nightly build?
May 02 16:00:03 <drath> are you on linux or on windows?
May 02 16:00:20 <xela> windows here
May 02 16:01:57 <drath> the necessary change is already in r141 available from yagarto
May 02 16:03:16 <xela> ah ok
May 02 16:03:35 <xela> Open On-Chip Debugger (2007-04-16 19:30 CEST)
May 02 16:03:37 <xela> ?
May 02 16:04:07 <drath> yeah, i think so
May 02 16:05:29 <xela> reset halt
May 02 16:05:32 <xela> seems to work
May 02 16:05:44 <drath> it halted at 0x0?
May 02 16:06:02 <drath> try another "poll" to be sure it's not running
May 02 16:06:19 <xela> nope
May 02 16:06:41 <xela> > poll
May 02 16:06:42 <xela> target state: running
May 02 16:06:47 <xela> :-(
May 02 16:08:07 <xela> do you have use for a Olimex STR-750-STK board?
May 02 16:11:18 <drath> heh, limited - i already have several olimex boards i use to test the OpenOCD, but other than that i have little time to do anything with them
May 02 16:30:03 <xela> nothing wrong with testing
May 02 16:30:28 <xela> wouldnt it be nice to have an automatic test suite that runs all kind of tests on different hardware?
May 02 16:32:33 <xela> well, just dreaming
May 02 16:32:38 <drath> heh, we've got test-monkeys^Wusers for that ;)
May 02 16:32:43 <xela> :-)
May 02 16:32:47 <xela> so true
May 02 16:34:08 <drath> when you tried the reset halt, was the target running or halted?
May 02 16:34:32 <xela> hm
May 02 16:34:37 <xela> i would say running
May 02 16:34:52 <drath> could you try again? it wont work if the target is halted
May 02 16:35:04 <drath> and make sure you haven't got "srst_pulls_trst" in the .cfg
May 02 16:35:21 <drath> just tried it on a STR912, and it's working fine here
May 02 16:35:41 <xela> Open On-Chip Debugger
May 02 16:35:42 <xela> > resume
May 02 16:35:44 <xela> Target 0 resumed
May 02 16:35:45 <xela> > poll
May 02 16:35:47 <xela> target state: running
May 02 16:35:48 <xela> > reset halt
May 02 16:35:50 <xela> > poll
May 02 16:35:52 <xela> target state: running
May 02 16:35:53 <xela> >
May 02 16:36:23 <drath> hmm, ok, it isn't working :/
May 02 16:36:57 <drath> the idea was that there might be something in your application that interferes with the flashing
May 02 16:37:04 <drath> that would explain why it works every other time
May 02 16:37:14 <drath> after it failed, the board is basically uninitialized, and flashing works
May 02 16:37:50 <xela> hm
May 02 16:38:05 <xela> thought while flashing jtag has "total" control
May 02 16:38:11 <xela> no interrupts or such
May 02 16:38:17 <xela> so no app code should be running
May 02 16:38:34 <xela> (i am stating a soft_reset_halt before every flash)
May 02 16:38:36 <drath> hmm, yeah, but the PLL for example got initialized
May 02 16:38:42 <drath> or a watchdog programmed
May 02 16:38:46 <xela> thats true
May 02 16:38:49 <xela> true as well
May 02 16:38:54 <drath> and the flash algorithm runs as normal code
May 02 16:38:57 <xela> the watchdog is programmed for sure
May 02 16:38:58 <drath> to the core there's no difference
May 02 16:39:01 <drath> it is?
May 02 16:39:03 <xela> sure
May 02 16:39:19 <drath> is it possible to disarm the watchdog on the STR750?
May 02 16:39:20 <xela> seems to explain a lot, huh?
May 02 16:41:25 <xela> just looked it up in the STR75x library code
May 02 16:41:38 <xela> but this only enabled the watchdog
May 02 16:41:44 <xela> I can look it up
May 02 16:41:52 <xela> (will be away for an hour)
May 02 16:42:34 <drath> hmm, the manual says you can't disable it after it was enabled
May 02 16:43:35 <drath> you might be able to work around this by erasing first, then issuing a reset run_and_halt, and then writing
May 02 16:43:41 <drath> this should disable the watchdog
May 02 16:43:47 <xela> true
May 02 16:43:50 <xela> good idea
May 02 17:15:32 <xela> another bad one: 
May 02 17:15:40 <xela> we have an app and a bootloader
May 02 17:16:01 <xela> and ideally i want to flash only the app
May 02 17:16:13 <xela> but the bootloader activates the watchdog already :-(
May 02 17:19:20 <xela> but what about soft_reset_and_halt?
May 02 17:19:27 <xela> watchdog still enabled?
May 02 17:30:40 <xela> drath: you still there?
May 02 18:07:57 <drath> xela: re
May 02 18:08:08 <xela> yea
May 02 18:08:12 <drath> soft_reset_halt only resets the core
May 02 18:08:17 <xela> i am trying a workaound now.
May 02 18:08:20 <drath> or rather simulates that
May 02 18:08:35 <drath> i.e. it loads the pc with 0x0, cpsr with svc etc.
May 02 18:08:36 <xela> added a non initialized memory cell for the bootloader
May 02 18:08:51 <xela> if a magic in there is set i dont initialize watchdog
May 02 18:10:45 <xela> hm
May 02 18:10:49 <xela> i am using this in a script
May 02 18:10:57 <xela> but command seem to be asynchronous
May 02 18:11:00 <xela> script:
May 02 18:11:22 <xela> halt
May 02 18:11:24 <xela> # Magic-Wert schaltet Watchdog im Bootloader ab
May 02 18:11:25 <xela> mww 0x40000010 0xfeede5e1
May 02 18:11:27 <xela> reset
May 02 18:11:28 <xela> halt
May 02 18:11:30 <xela> flash protect 0 0 2 off
May 02 18:11:31 <xela> flash erase 0 0 2 
May 02 18:11:33 <xela> flash write 0 ..\boot\source\output\boot-0.bin 0
May 02 18:11:34 <xela> flash protect 0 8 9 off
May 02 18:11:36 <xela> flash erase 0 8 9 
May 02 18:11:37 <xela> flash write 0 ..\boot\source\output\boot-1.bin 0xc0000
May 02 18:11:39 <xela> soft_reset_halt
May 02 18:11:45 <drath> use a wait_halt after the halt
May 02 18:11:53 <drath> to ensure the target is really halted
May 02 18:13:56 <xela> flash write 0 ..\app\source\output\app-crc.bin 0x6000
May 02 18:13:58 <xela> failed writing file ..\app\source\output\app-crc.bin to flash bank 0 at offset 0x00006000
May 02 18:13:59 <xela> flash program error
May 02 18:14:01 <xela> soft_reset_halt
May 02 18:14:02 <xela> :-(
May 02 18:14:05 <xela> didnt improve things
May 02 18:15:57 <drath> yeah, soft_reset_halt really doesn't change anything
May 02 18:16:02 <drath> it just sets core registers
May 02 18:16:07 <drath> but doesn't affect the peripherals
May 02 18:17:24 <xela> yea
May 02 18:17:36 <xela> i just changed the app flash script a bit:
May 02 18:17:43 <xela> 1. halt and set magic word
May 02 18:18:00 <xela> 2. erase app area
May 02 18:18:04 <xela> 3. reset and wait
May 02 18:18:17 <xela> 4. flash (now without watchdog hopefully)
May 02 18:26:21 <xela> hmm, looks better now
May 02 18:26:24 <xela> way better!
May 02 18:29:43 <drath> heh, cool
May 02 18:30:05 <xela> and the watchdog isnt set anymore
May 02 18:30:14 <xela> wish one could disable the watchdog
May 02 18:30:29 <xela> ok
May 02 18:30:35 <xela> will be gone for today
May 02 18:30:47 <xela> and again: thanks a lot for your help! its very appreciated!
May 02 18:31:04 <xela> gonna talk about the checksum/crc topic sometime soon?
May 02 18:31:29 <drath> sure, just ping me here
May 02 18:31:37 <drath> i'll try to answer ;)
May 02 21:03:02 <kas11> I see many of the usual suspects are here ;)
May 02 21:14:33 <kas11> if y'all insist on talking at once, I'm gonna have to increase my history length to more than 2 lines
May 02 21:19:45 <drath> heh, hi
May 02 21:19:59 <drath> it's been a bit quiet here lately
May 02 21:22:24 <kas11> hmmm ... sound configuration is screwed on this box..   hi drath
**** ENDING LOGGING AT Thu May 03 02:59:56 2007