**** BEGIN LOGGING AT Tue Oct 09 02:59:56 2007
Oct 09 18:14:34 <prpplague> drath: ping
Oct 09 18:24:59 <drath> prpplague: pong
Oct 09 18:25:09 <prpplague> drath: oh good you are there
Oct 09 18:25:24 <prpplague> drath: question, whats the syntax for configuring nand flash in the .cfg file?
Oct 09 18:39:14 <drath> prpplague: "nand device <driver> [driver options]"
Oct 09 18:39:31 <prpplague> drath: yea, just found it in the code
Oct 09 18:39:41 <prpplague> drath: so for example
Oct 09 18:39:47 <prpplague> drath: the lpc3180 would be
Oct 09 18:39:57 <prpplague> drath: nand device lpc3180
Oct 09 18:40:15 <drath> for the lpc3180 it's:
Oct 09 18:40:16 <drath> nand device lpc3180 <target#> <oscillator_frequency>
Oct 09 18:41:02 <prpplague> ahh gotcha
Oct 09 18:41:04 <drath> most NAND's are going to have a <target#>
Oct 09 18:41:22 <drath> because the NAND is always connected to a target
Oct 09 18:41:49 <drath> but I thought about a generic boundary-scan NAND driver, in which case you'd have a <jtag-index> instead
Oct 09 18:42:24 <drath> not sure about the S3C24xx, but for the LPC3180 you have to specify several timing parameters as well
Oct 09 18:42:56 <drath> the lpc3180 uses the <oscillator_frequency> to calculate the current clock configuration after reading some registers
Oct 09 18:44:17 <prpplague> drath: yea there are a few setups for the s3c24xx, but i'm not sure i understand about the "target" 
Oct 09 18:45:35 <drath> you mean the <target#>?
Oct 09 18:46:04 <prpplague> yea
Oct 09 18:46:40 <drath> the OpenOCD supports multiple, daisy chained targets
Oct 09 18:46:47 <drath> so you could have several jtag_device entries
Oct 09 18:46:52 <drath> and also several target xxxx entries
Oct 09 18:47:16 <prpplague> drath: ahh ok, so the target is the device that the specified nand flash is connected to
Oct 09 18:47:19 <drath> the NAND needs to know which target number it is connected to, starting with "0" for the first
Oct 09 18:48:07 <prpplague> drath: ahh ok so for my case the it will be 0
Oct 09 18:48:10 <drath> i should get a AT91SAM9260 board within a few days, that'll give me the chance to implement NAND support for another device
Oct 09 18:48:18 <drath> prpplague: yeah
Oct 09 18:48:36 <prpplague> drath: yea i copied the lpc3180 code and have started hacking it up
Oct 09 18:50:25 <drath> which s3c24xx are you working with?
Oct 09 18:50:37 <drath> they've got different NAND controllers iirc, right?
Oct 09 18:52:15 <prpplague> drath: its my understanding that the controllers on the s3c2410 and s3c2440 are the same
Oct 09 18:53:34 <prpplague> drath: yea a quick check looks to be the same
Oct 09 18:54:13 <drath> prpplague: ok, but 2442 for example seems to be different
Oct 09 18:54:41 <drath> prpplague: it supports 2kb pages whereas the 2410 supports only 512b pages
Oct 09 18:55:03 * prpplague looks
Oct 09 18:56:14 <prpplague> drath: yea thats a limitation of the 2410 configuration
Oct 09 18:56:54 <prpplague> drath: the 2442 and 2440 are the same core , with the 2442 having some additional features available such as ram and nand flash on the same silicon
Oct 09 18:57:05 <prpplague> drath: so if anything, the 2442 and 2440 would be identical
Oct 09 18:57:25 <prpplague> drath: all the address space is the same from what i'm seeing
Oct 09 19:00:16 * prpplague has to run an errand
Oct 09 19:00:20 <prpplague> drath: thanks for the info
Oct 09 19:00:23 <prpplague> bbiab
Oct 09 20:20:38 * prpplague returns
Oct 09 20:29:50 <prpplague> drath: greetings
Oct 09 20:30:51 <prpplague> drath: probing nand flash seems to be working
Oct 09 20:31:04 <prpplague> drath: you gonna want patches submitted for these?
Oct 09 20:31:37 <drath> prpplague: yeah, of course
Oct 09 20:32:10 <prpplague> drath: i've just about given up on submitting patches these days, so i just wanted to make sure before i wasted my time, hehe
Oct 09 20:35:00 <prpplague> drath: we submited a 208 patches in the last 6 months, only 3 were accepted, and around 100 really haven't even been looked at by the maintainers
Oct 09 20:37:23 <drath> prpplague: least i'll do is check them in for others to look at
Oct 09 20:37:40 <drath> prpplague: then, when i start working on the sam9 nand, i'll look at them again to see how the nand concept fits together
Oct 09 20:37:41 <prpplague> drath: thanks
Oct 09 20:37:52 <prpplague> drath: so far it looks good
Oct 09 20:37:59 <prpplague> drath: i like the feel of it
Oct 09 20:43:52 <prpplague> drath: hey, quick question
Oct 09 20:44:08 <prpplague> drath: the s3c24xx use a seperate flag to control the chip select
Oct 09 20:44:23 <prpplague> drath: i'm not seeing any routines setup for that in the lpc3180
Oct 09 20:51:05 <prpplague> hmm
Oct 09 20:51:14 <prpplague> drath: another problem
Oct 09 20:51:37 <prpplague> drath: the s3c2440 nand flash controller does 32bit data read/writes
Oct 09 20:59:00 <drath> prpplague: the lpc3180 is rather complicated
Oct 09 20:59:08 <drath> prpplague: you can't access the NAND bus on your own
Oct 09 21:00:22 <prpplague> drath: i wonder what the cortex nand flash controler is like
Oct 09 21:01:15 <prpplague> drath: i'm afraid i'm going to need to add a x32 buswidth 
Oct 09 21:01:21 <prpplague> drath: to the main nand.c code
Oct 09 21:01:39 <prpplague> drath: because the nand controller doesn't really perform in the same manner
Oct 09 21:02:58 <drath> hmm, the nand bus width refers to the nand chip itself, iirc
Oct 09 21:03:13 <drath> and i don't think i've seen 32-bit NAND chips?
Oct 09 21:04:28 <prpplague> drath: correct
Oct 09 21:04:48 <prpplague> drath: however the nand controller itself is geared for 32bit read/writes
Oct 09 21:05:16 <prpplague> drath: i.e. one read of the 32bit data register is the same as calling the 8bit read 4 times
Oct 09 21:05:42 <prpplague> drath: for instance on the vendor id
Oct 09 21:06:17 <drath> ah, yeah, but that's not what x8/x16 buswidth means
Oct 09 21:06:29 <prpplague> drath: if you do the vendor id command and do a single read of the 32bit register you get something like 0x00003520
Oct 09 21:06:40 <prpplague> drath: yea i know
Oct 09 21:07:03 <prpplague> drath: i was trying to think of the best way to handle it
Oct 09 21:07:29 <drath> heh, it's been 6 months since i last looked at that code
Oct 09 21:07:30 <prpplague> drath: since even though it is an 8-bit buswidth, all of that is actually hidden behind the controller
Oct 09 21:07:33 <drath> let me check some things
Oct 09 21:07:40 <prpplague> drath: np
Oct 09 21:14:09 <drath> according to the 2442 manual you should be able to just do multiple bus-width accesses
Oct 09 21:14:20 <drath> and each should return consecutive data
Oct 09 21:14:37 <drath> only if you read multiples of the bus-width you get multiple accesses
Oct 09 21:16:22 <prpplague> drath: hmm, that doesn't seem to be the case
Oct 09 21:16:31 * prpplague retests and looks at example code
Oct 09 21:17:43 <prpplague> drath: ahh, indeed if you do a 8 bit read you get 8 bit data
Oct 09 21:17:44 <prpplague> lovely
Oct 09 21:19:19 <prpplague> drath: kind of a waste, but oh well
Oct 09 21:19:53 <prpplague> "NAND flash device 'NAND 32MiB 1,8V 8-bit' found"
Oct 09 21:20:00 <prpplague> lovely
Oct 09 21:20:10 <drath> the write|read_page functions can be implemented for accelerated operation
Oct 09 21:20:20 <drath> iirc
Oct 09 21:20:30 <prpplague> > nand info 0
Oct 09 21:20:30 <prpplague> #0: NAND 32MiB 1,8V 8-bit (ST Micro) pagesize: 512, buswidth: 8, erasesize: 16384
Oct 09 21:20:30 <prpplague> 	#-1: 0x646e616e (0x819ddkB) erase state unknown (block condition unknown)
Oct 09 21:20:37 <drath> i'll have to go through all this again, but not at 11:20pm ;)
Oct 09 21:20:44 <prpplague> drath: hehe, np
Oct 09 21:20:48 <prpplague> drath: thanks for the info
Oct 09 21:21:01 <drath> the lpc3180 does pretty much everything on its own
Oct 09 21:21:01 <prpplague> drath: should have it working pretty well by tomorrow
Oct 09 21:21:12 <drath> especially in MLC mode
Oct 09 21:21:19 <prpplague> drath: i'll generate a patch and send your way to have a look at
Oct 09 21:21:21 <drath> the two modes are basically two different controllers
Oct 09 21:21:27 <drath> great, thanks
Oct 09 21:21:34 <prpplague> drath: my repo is of the svn from a couple weeks back
Oct 09 21:21:47 <drath> that code isn't likely to change
Oct 09 21:22:01 <drath> i'm off for today, bye
Oct 09 21:22:33 <prpplague> drath: later
Oct 09 21:45:14 <prpplague> drath: dump works
**** ENDING LOGGING AT Wed Oct 10 02:59:57 2007