**** BEGIN LOGGING AT Thu Mar 05 02:59:56 2009
Mar 05 08:35:30 <mwalle> hi
Mar 05 08:40:00 <mwalle> does anybody know how h/w debugging works without being able to halt the cpu? do you need special handling in the breakpoint exception?
Mar 05 08:41:49 <mwalle> (i have an lm32 softcpu inside an fpga, but the lm32 core is from lattice and i'm using it with xilinx and trying to create a new target for openocd, but doesn't understand how the h/w debug should work)
Mar 05 08:42:58 <mwalle> i have only jtag commands for reset, break, write control status register, read/write memory and single stepping
Mar 05 08:43:20 <mwalle> and the cpu cant be halted
Mar 05 08:44:19 <mwalle> i cant even read or write registers
Mar 05 08:45:20 <mwalle> so basically there have to be a special exception handler, that writes the registers into memory
Mar 05 10:29:25 <keesj> no sorry
**** ENDING LOGGING AT Fri Mar 06 02:59:57 2009