**** BEGIN LOGGING AT Thu Jul 08 02:59:57 2010 Jul 08 12:41:13 Hi, I just ran openocd 0.4.0 flash write_image but get error writing to flash at address 0x60000000 at offset 0x000c0000 (-902) Any ideas on how to solve this? I have work-area-phys 0x80014000 size 0x1000 and no backup. It is an EP9307 target using a olimex jtag tiny. Jul 08 12:46:20 ja2: rerun openocd with increased loglevel (-d) Jul 08 12:47:56 core.c:76 flash_driver_write(): error writing to flash at address 0x60000000 at offset 0x000c0000 (-902) Jul 08 12:47:56 So I look there. Jul 08 12:49:45 no other errors? Jul 08 12:52:41 what kind of flash do you use? an intel one? Jul 08 12:53:47 No errors I can see. MT28F640J3 flash. Jul 08 12:54:03 Dont know if it intel how manuf. those. Jul 08 12:54:17 +is Jul 08 12:56:02 i found only 3 positions where this error gets issued without error message, all are in functions for intel command NOR flashes Jul 08 12:58:44 I flashed a new u-boot just previously. this new u-boot change the (external) RAM from 32-bit to 16-bit. Thereby losing half of my RAM, but that is what I want. The work-area openocd uses is a MAC FIFO buffer in the EP9307 chip. Jul 08 12:58:53 I didnt think it would be affected. Jul 08 12:59:38 ja2: which actual command did you use? Jul 08 12:59:51 Well, this warning (-902) was issued in the first u-boot flash too. But power toggle/restart openocd solved that. Jul 08 13:00:19 flash write_image /tmp/uImage.bin 0x600c0000 Jul 08 13:01:19 try flash write_image erase /tmp/uImage.bin 0x600c0000 Jul 08 13:02:39 I did a soft_reset_halt. That solved the problem. Jul 08 13:02:57 By that I get control over the chip before u-boot change the ram width, Jul 08 13:03:30 doesn't this ARM have internal SRAM which you can use a workspace? Jul 08 13:03:30 6 sections was flashed, but then -902 again. Jul 08 13:03:54 No, it is just 0x10ff bytes of fifo that I can use. Jul 08 13:04:18 don't you need to setup PLL and stuff first? Jul 08 13:05:08 Doesnt seem to need to set up PLL. Maybe I run the jtag slow enough to work with the 14 Mhz crystal. Jul 08 13:06:54 Anyway, the flash write_image should work without erase. Just filling in 0's where there was 1's previously. Jul 08 13:08:19 ja2: i don't know if this also matches to EP93, but on AT91 I can run 1/6 of my slowclock which is 32kHz Jul 08 13:10:08 I never found the exact info on what jtag speed to use for this chip. My cfg files worked well with openocd 0.2.0, so I should fall back and test there, so nothing bad have happened with the hw. Have to change computer/login to do that though... Jul 08 13:14:04 you can do a svn checkout on version 0.2.0 and recompile Jul 08 13:14:22 Got a new error running the jtag at 1 khz; Jul 08 13:14:24 Error: 508 152841 arm7_9_common.c:718 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 5 Jul 08 13:14:32 Error: 509 152841 cfi.c:1141 cfi_intel_write_block(): Unable to write block write code to target Jul 08 13:14:38 *** glibc detected *** openocd: free(): invalid pointer: 0x00525819 *** Jul 08 13:14:43 +dump Jul 08 13:16:02 Well, maybe not so strange... Jul 08 13:17:51 ja2: the 1st 2 lines sound like real error messages, but the last one seem to be wrong error handling **** ENDING LOGGING AT Thu Jul 08 22:47:23 2010 **** BEGIN LOGGING AT Fri Jul 09 00:18:14 2010 **** ENDING LOGGING AT Fri Jul 09 02:59:57 2010